diff --git a/sys/arch/sparc/include/ctlreg.h b/sys/arch/sparc/include/ctlreg.h
index 1f5d8519aefe..a945e6c2868d 100644
--- a/sys/arch/sparc/include/ctlreg.h
+++ b/sys/arch/sparc/include/ctlreg.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: ctlreg.h,v 1.12 1996/05/16 15:57:00 abrown Exp $ */
+/*	$NetBSD: ctlreg.h,v 1.13 1997/03/22 19:15:53 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -201,35 +201,95 @@
 #define SRMMU_AFADDR	0x00000600	/* Asynchronous fault address reg (HS)*/
 #define SRMMU_TLBCTRL	0x00001000	/* TLB replacement control reg */
 
-/* [4m] Bits in SRMMU control register */
-#define SRMMU_PCR_ME	0x00000001	/* MMU Enable */
-#define SRMMU_PCR_NF	0x00000002	/* Fault inhibit bit */
-#define SRMMU_PCR_PSO	0x00000080	/* Partial Store Ordering enable */
-#define SRMMU_PCR_CE	0x00000100	/* HS: Cache enable bit (HyperSPARC) */
-#define SRMMU_PCR_DCE	0x00000100	/* SS: Data cache enable bit */
-#define SRMMU_PCR_ICE	0x00000200	/* SS: SuperSPARC instr. cache enable */
-#define SRMMU_PCR_CM	0x00000400	/* HS: Cache mode: 1 == write-back */
-#define SRMMU_PCR_SB	0x00000400	/* SS: Store buffer enable bit */
-#define	SRMMU_PCR_MR	0x00000800	/* HS: Memory reflection: 1 == on */
-#define SRMMU_PCR_MB	0x00000800	/* SS: MBus mode: 0=MXCC, 1=no MXCC */
-#define SRMMU_PCR_CS	0x00001000	/* HS: cache size: 1==256k, 0==128k */
-#define SRMMU_PCR_PE	0x00001000	/* SS: Enable memory parity checking */
-#define SRMMU_PCR_C	0x00002000	/* HS: enable cache when MMU off */
-#define SRMMU_PCR_SSBM	0x00002000	/* SS: 1 iff booting */
-#define SRMMU_PCR_HSBM	0x00004000	/* HS: 1 iff booting */
-#define SRMMU_PCR_SSSE	0x00004000	/* SS: Coherent bus snoop enable */
-#define SRMMU_PCR_AC	0x00008000	/* SS: 1=cache non-MMU accesses */
-#define	SRMMU_PCR_TC	0x00010000	/* SS: 1=cache table walks */
-#define SRMMU_PCR_MID	0x00078000	/* HS: MBus module ID MID<3:0> */
-#define SRMMU_PCR_WBE	0x00080000	/* HS: Write buffer enable */
-#define SRMMU_PCR_HSSE	0x00100000	/* HS: Coherent bus snoop enable */
-#define SRMMU_PCR_CWR	0x00200000	/* HS: Cache wrap enable */
+
+/*
+ * [4m] Bits in SRMMU control register. One set per module.
+ */
+#define VIKING_PCR_ME	0x00000001	/* MMU Enable */
+#define VIKING_PCR_NF	0x00000002	/* Fault inhibit bit */
+#define VIKING_PCR_PSO	0x00000080	/* Partial Store Ordering enable */
+#define VIKING_PCR_DCE	0x00000100	/* Data cache enable bit */
+#define VIKING_PCR_ICE	0x00000200	/* SuperSPARC instr. cache enable */
+#define VIKING_PCR_SB	0x00000400	/* Store buffer enable bit */
+#define VIKING_PCR_MB	0x00000800	/* MBus mode: 0=MXCC, 1=no MXCC */
+#define VIKING_PCR_PE	0x00001000	/* Enable memory parity checking */
+#define VIKING_PCR_BM	0x00002000	/* 1 iff booting */
+#define VIKING_PCR_SE	0x00004000	/* Coherent bus snoop enable */
+#define VIKING_PCR_AC	0x00008000	/* 1=cache non-MMU accesses */
+#define	VIKING_PCR_TC	0x00010000	/* 1=cache table walks */
+
+#define HYPERSPARC_PCR_ME	0x00000001	/* MMU Enable */
+#define HYPERSPARC_PCR_NF	0x00000002	/* Fault inhibit bit */
+#define HYPERSPARC_PCR_CE	0x00000100	/* Cache enable bit */
+#define HYPERSPARC_PCR_CM	0x00000400	/* Cache mode: 1=write-back */
+#define	HYPERSPARC_PCR_MR	0x00000800	/* Memory reflection: 1 = on */
+#define HYPERSPARC_PCR_CS	0x00001000	/* cache size: 1=256k, 0=128k */
+#define HYPERSPARC_PCR_C	0x00002000	/* enable cache when MMU off */
+#define HYPERSPARC_PCR_BM	0x00004000	/* 1 iff booting */
+#define HYPERSPARC_PCR_MID	0x00078000	/* MBus module ID MID<3:0> */
+#define HYPERSPARC_PCR_WBE	0x00080000	/* Write buffer enable */
+#define HYPERSPARC_PCR_SE	0x00100000	/* Coherent bus snoop enable */
+#define HYPERSPARC_PCR_CWR	0x00200000	/* Cache wrap enable */
+
+#define CYPRESS_PCR_ME	0x00000001	/* MMU Enable */
+#define CYPRESS_PCR_NF	0x00000002	/* Fault inhibit bit */
+#define CYPRESS_PCR_CE	0x00000100	/* Cache enable bit */
+#define CYPRESS_PCR_CL	0x00000200	/* Cache Lock (604 only) */
+#define CYPRESS_PCR_CM	0x00000400	/* Cache mode: 1=write-back */
+#define	CYPRESS_PCR_MR	0x00000800	/* Memory reflection: 1=on (605 only) */
+#define CYPRESS_PCR_C	0x00002000	/* enable cache when MMU off */
+#define CYPRESS_PCR_BM	0x00004000	/* 1 iff booting */
+#define CYPRESS_PCR_MID	0x00078000	/* MBus module ID MID<3:0> (605 only) */
+#define CYPRESS_PCR_MV	0x00080000	/* Multichip Valid */
+#define CYPRESS_PCR_MCM	0x00300000	/* Multichip Mask */
+#define CYPRESS_PCR_MCA	0x00c00000	/* Multichip Address */
+
+#define MS1_PCR_ME	0x00000001	/* MMU Enable */
+#define MS1_PCR_NF	0x00000002	/* Fault inhibit bit */
+#define MS1_PCR_DCE	0x00000100	/* Data cache enable */
+#define MS1_PCR_ICE	0x00000200	/* Instruction cache enable */
+#define MS1_PCR_RC	0x00000c00	/* DRAM Refresh control */
+#define MS1_PCR_PE	0x00001000	/* Enable memory parity checking */
+#define MS1_PCR_BM	0x00004000	/* 1 iff booting */
+#define MS1_PCR_AC	0x00008000	/* 1=cache if ME==0 (and [ID]CE on) */
+#define	MS1_PCR_ID	0x00010000	/* 1=disable ITBR */
+#define	MS1_PCR_PC	0x00020000	/* Parity control: 0=even,1=odd */
+#define	MS1_PCR_MV	0x00100000	/* Memory data View (diag) */
+#define	MS1_PCR_DV	0x00200000	/* Data View (diag) */
+#define	MS1_PCR_AV	0x00400000	/* Address View (diag) */
+#define	MS1_PCR_STW	0x00800000	/* Software Tablewalk enable */
+
+#define SWIFT_PCR_ME	0x00000001	/* MMU Enable */
+#define SWIFT_PCR_NF	0x00000002	/* Fault inhibit bit */
+#define SWIFT_PCR_DCE	0x00000100	/* Data cache enable */
+#define SWIFT_PCR_ICE	0x00000200	/* Instruction cache enable */
+#define SWIFT_PCR_RC	0x00003c00	/* DRAM Refresh control */
+#define SWIFT_PCR_BM	0x00004000	/* 1 iff booting */
+#define SWIFT_PCR_AC	0x00008000	/* 1=cache if ME=0 (and [ID]CE on) */
+#define	SWIFT_PCR_PA	0x00010000	/* TCX/SX control */
+#define	SWIFT_PCR_PC	0x00020000	/* Parity control: 0=even,1=odd */
+#define SWIFT_PCR_PE	0x00040000	/* Enable memory parity checking */
+#define	SWIFT_PCR_PMC	0x00180000	/* Page mode control */
+#define	SWIFT_PCR_BF	0x00200000	/* Branch Folding */
+#define	SWIFT_PCR_WP	0x00400000	/* Watch point enable */
+#define	SWIFT_PCR_STW	0x00800000	/* Software Tablewalk enable */
+
+#define TURBOSPARC_PCR_ME	0x00000001	/* MMU Enable */
+#define TURBOSPARC_PCR_NF	0x00000002	/* Fault inhibit bit */
+#define TURBOSPARC_PCR_ICS	0x00000004	/* I-cache snoop enable */
+#define TURBOSPARC_PCR_PSO	0x00000008	/* Partial Store order (ro!) */
+#define TURBOSPARC_PCR_DCE	0x00000100	/* Data cache enable */
+#define TURBOSPARC_PCR_ICE	0x00000200	/* Instruction cache enable */
+#define TURBOSPARC_PCR_RC	0x00003c00	/* DRAM Refresh control */
+#define TURBOSPARC_PCR_BM	0x00004000	/* 1 iff booting */
+#define	TURBOSPARC_PCR_PC	0x00020000	/* Parity ctrl: 0=even,1=odd */
+#define TURBOSPARC_PCR_PE	0x00040000	/* Enable parity checking */
+#define	TURBOSPARC_PCR_PMC	0x00180000	/* Page mode control */
+
+/* Implementation and Version fields are common to all modules */
 #define SRMMU_PCR_VER	0x0f000000	/* Version of MMU implementation */
 #define SRMMU_PCR_IMPL	0xf0000000	/* Implementation number of MMU */
 
-#ifdef notyet
-#define SRMMU_PCR_INITIAL (SRMMU_PCR_ME | SRMMU_PCR_TC)
-#endif
 
 /* [4m] Bits in the Synchronous Fault Status Register */
 #define SFSR_EM		0x00020000	/* Error mode watchdog reset occurred */
diff --git a/sys/arch/sparc/sparc/cache.c b/sys/arch/sparc/sparc/cache.c
index 99f72c708be5..2a298f201887 100644
--- a/sys/arch/sparc/sparc/cache.c
+++ b/sys/arch/sparc/sparc/cache.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache.c,v 1.21 1997/03/21 15:35:51 pk Exp $ */
+/*	$NetBSD: cache.c,v 1.22 1997/03/22 19:17:03 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -123,7 +123,7 @@ ms1_cache_enable()
 
 	/* Turn on caches via MMU */
 	sta(SRMMU_PCR, ASI_SRMMU,
-	    lda(SRMMU_PCR,ASI_SRMMU) | SRMMU_PCR_DCE | SRMMU_PCR_ICE);
+	    lda(SRMMU_PCR,ASI_SRMMU) | MS1_PCR_DCE | MS1_PCR_ICE);
 
 	CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
 
@@ -147,7 +147,7 @@ viking_cache_enable()
 
 	/* Turn on caches via MMU */
 	sta(SRMMU_PCR, ASI_SRMMU,
-	    lda(SRMMU_PCR,ASI_SRMMU) | SRMMU_PCR_DCE | SRMMU_PCR_ICE);
+	    lda(SRMMU_PCR,ASI_SRMMU) | VIKING_PCR_DCE | VIKING_PCR_ICE);
 
 	CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
 
@@ -176,7 +176,7 @@ hypersparc_cache_enable()
 	 * First we determine what type of cache we have, and
 	 * setup the anti-aliasing constants appropriately.
 	 */
-	if (i & SRMMU_PCR_CS) {
+	if (i & HYPERSPARC_PCR_CS) {
 		cache_alias_bits = CACHE_ALIAS_BITS_HS256k;
 		cache_alias_dist = CACHE_ALIAS_DIST_HS256k;
 	} else {
@@ -188,7 +188,7 @@ hypersparc_cache_enable()
 		sta(i, ASI_DCACHETAG, 0);
 
 	sta(SRMMU_PCR, ASI_SRMMU, /* Enable write-back cache */
-	    lda(SRMMU_PCR, ASI_SRMMU) | SRMMU_PCR_CE | SRMMU_PCR_CM);
+	    lda(SRMMU_PCR, ASI_SRMMU) | HYPERSPARC_PCR_CE | HYPERSPARC_PCR_CM);
 	CACHEINFO.c_enabled = 1;
 
 	CACHEINFO.c_vactype = VAC_NONE;
@@ -219,11 +219,11 @@ cypress_cache_enable()
 	cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
 
 	scr = lda(SRMMU_PCR, ASI_SRMMU);
-	scr &= ~(SRMMU_PCR_CE | SRMMU_PCR_CM);
-	scr |= SRMMU_PCR_CE;
+	scr &= ~(CYPRESS_PCR_CE | CYPRESS_PCR_CM);
+	scr |= CYPRESS_PCR_CE;
 	/* If put in write-back mode, turn it on */
 	if (CACHEINFO.c_vactype == VAC_WRITEBACK)
-		scr |= SRMMU_PCR_CM;
+		scr |= CYPRESS_PCR_CM;
 	sta(SRMMU_PCR, ASI_SRMMU, scr);
 	CACHEINFO.c_enabled = 1;
 	printf("cache enabled\n");
diff --git a/sys/arch/sparc/sparc/cpu.c b/sys/arch/sparc/sparc/cpu.c
index dc334811e355..5b6f6ec29830 100644
--- a/sys/arch/sparc/sparc/cpu.c
+++ b/sys/arch/sparc/sparc/cpu.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.34 1997/03/21 14:30:20 pk Exp $ */
+/*	$NetBSD: cpu.c,v 1.35 1997/03/22 19:17:05 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -787,7 +787,7 @@ viking_hotfix(sc)
 	struct cpu_softc *sc;
 {
 	/* Test if we're directly on the MBus */
-	if (!(lda(SRMMU_PCR, ASI_SRMMU) & SRMMU_PCR_MB)) {
+	if (!(lda(SRMMU_PCR, ASI_SRMMU) & VIKING_PCR_MB)) {
 		sc->mxcc = 1;
 		sc->flags |= CPUFLG_CACHEPAGETABLES;
 		sc->flags |= CPUFLG_CACHE_MANDATORY;
@@ -816,9 +816,9 @@ viking_mmu_enable()
 
 	pcr = lda(SRMMU_PCR, ASI_SRMMU);
 	if (cpuinfo.mxcc)
-		pcr |= SRMMU_PCR_TC;
+		pcr |= VIKING_PCR_TC;
 	else
-		pcr &= ~SRMMU_PCR_TC;
+		pcr &= ~VIKING_PCR_TC;
 	sta(SRMMU_PCR, ASI_SRMMU, pcr);
 }
 
@@ -852,8 +852,13 @@ cpumatch_hypersparc(sc, mp, node)
 void
 hypersparc_mmu_enable()
 {
-	int pcr = lda(SRMMU_PCR, ASI_SRMMU);
-	sta(SRMMU_PCR, ASI_SRMMU, (pcr | SRMMU_PCR_C) & ~SRMMU_PCR_CE);
+	int pcr;
+
+	pcr = lda(SRMMU_PCR, ASI_SRMMU);
+	pcr |= HYPERSPARC_PCR_C;
+	pcr &= ~HYPERSPARC_PCR_CE;
+
+	sta(SRMMU_PCR, ASI_SRMMU, pcr);
 }
 
 /* Cypress 605 */
diff --git a/sys/arch/sparc/sparc/iommu.c b/sys/arch/sparc/sparc/iommu.c
index 21c279dfd7b0..cde2a604fed0 100644
--- a/sys/arch/sparc/sparc/iommu.c
+++ b/sys/arch/sparc/sparc/iommu.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: iommu.c,v 1.9 1997/03/10 23:13:59 pk Exp $ */
+/*	$NetBSD: iommu.c,v 1.10 1997/03/22 19:17:06 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -122,12 +122,12 @@ iommu_attach(parent, self, aux)
 	register int node;
 	register char *name;
 	register u_int pbase, pa;
-	register int i, mmupcrsav, s, wierdviking = 0;
+	register int i, mmupcrsave, s;
 	register iopte_t *tpte_p;
 	extern u_int *kernel_iopte_table;
 	extern u_int kernel_iopte_table_pa;
 
-/*XXX-GCC!*/mmupcrsav=0;
+/*XXX-GCC!*/mmupcrsave=0;
 	iommu_sc = sc;
 	/*
 	 * XXX there is only one iommu, for now -- do not know how to
@@ -194,10 +194,10 @@ iommu_attach(parent, self, aux)
 	 *
 	 * XXX: PGOFSET, NBPG assume same page size as SRMMU
 	 */
-	if ((getpsr() & 0x40000000) && (!(lda(SRMMU_PCR,ASI_SRMMU) & 0x800))) {
-		wierdviking = 1;
-		sta(SRMMU_PCR, ASI_SRMMU, 	/* set MMU AC bit */
-		    ((mmupcrsav = lda(SRMMU_PCR,ASI_SRMMU)) | SRMMU_PCR_AC));
+	if (cpuinfo.cpu_vers == 4 && cpuinfo.mxcc) {
+		/* set MMU AC bit */
+		sta(SRMMU_PCR, ASI_SRMMU,
+		    ((mmupcrsave = lda(SRMMU_PCR, ASI_SRMMU)) | VIKING_PCR_AC));
 	}
 
 	for (tpte_p = &sc->sc_ptes[((0 - DVMA4M_BASE)/NBPG) - 1],
@@ -210,8 +210,9 @@ iommu_attach(parent, self, aux)
 			        (tpte_p - &sc->sc_ptes[0])*NBPG + DVMA4M_BASE);
 		*tpte_p = lda(pa, ASI_BYPASS);
 	}
-	if (wierdviking) {	/* restore mmu after bug-avoidance */
-		sta(SRMMU_PCR, ASI_SRMMU, mmupcrsav);
+	if (cpuinfo.cpu_vers == 4 && cpuinfo.mxcc) {
+		/* restore mmu after bug-avoidance */
+		sta(SRMMU_PCR, ASI_SRMMU, mmupcrsave);
 	}
 
 	/*
diff --git a/sys/arch/sparc/sparc/memreg.c b/sys/arch/sparc/sparc/memreg.c
index 1e116cd85fa6..b8eb3cd96f6d 100644
--- a/sys/arch/sparc/sparc/memreg.c
+++ b/sys/arch/sparc/sparc/memreg.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: memreg.c,v 1.18 1996/12/10 23:17:45 pk Exp $ */
+/*	$NetBSD: memreg.c,v 1.19 1997/03/22 19:17:07 pk Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -56,6 +56,7 @@
 #include <sparc/sparc/memreg.h>
 #include <sparc/sparc/vaddrs.h>
 #include <sparc/sparc/asm.h>
+#include <sparc/sparc/cpuvar.h>
 
 #include <machine/reg.h>	/* for trapframe */
 #include <machine/trap.h>	/* for trap types */
@@ -265,9 +266,12 @@ memerr4m(type, sfsr, sfva, afsr, afva, tf)
 		addrold = afva;
 		addroldtop = afsr & AFSR_AFA;
 
-	} else if (type == T_STOREBUFFAULT) {
-		/* We try to reenable the store buffers to force a retry */
+	} else if (type == T_STOREBUFFAULT && cpuinfo.cpu_vers == 4) {
 
+		/*
+		 * On Supersparc, we try to reenable the store buffers
+		 * to force a retry.
+		 */
 		printf("store buffer copy-back failure at 0x%x. Retrying...\n",
 		       sfva);
 
@@ -278,8 +282,9 @@ memerr4m(type, sfsr, sfva, afsr, afva, tf)
 		oldtype = T_STOREBUFFAULT;
 		addrold = sfva;
 
-		sta(SRMMU_PCR, ASI_SRMMU, lda(SRMMU_PCR, ASI_SRMMU) |
-			SRMMU_PCR_SB);	/* reenable store buffer */
+		/* reenable store buffer */
+		sta(SRMMU_PCR, ASI_SRMMU,
+		    lda(SRMMU_PCR, ASI_SRMMU) | VIKING_PCR_SB);
 
 	} else if (type == T_DATAFAULT && !(sfsr & SFSR_FAV)) { /* bizarre */
 		/* XXX: Should handle better. See SuperSPARC manual pg. 9-35 */
diff --git a/sys/arch/sparc/sparc/pmap.c b/sys/arch/sparc/sparc/pmap.c
index 3d4429583e14..6bdba8cf3768 100644
--- a/sys/arch/sparc/sparc/pmap.c
+++ b/sys/arch/sparc/sparc/pmap.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.74 1997/03/21 16:29:34 pk Exp $ */
+/*	$NetBSD: pmap.c,v 1.75 1997/03/22 19:17:09 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -1022,7 +1022,7 @@ mmu_reservemon4m(kpmap, kmemtop)
 	 */
 	if (cpuinfo.cpu_vers == 4 && cpuinfo.mxcc) {
 		sta(SRMMU_PCR, ASI_SRMMU, 	/* set MMU AC bit */
-		    ((mmupcrsave = lda(SRMMU_PCR,ASI_SRMMU)) | SRMMU_PCR_AC));
+		    ((mmupcrsave = lda(SRMMU_PCR,ASI_SRMMU)) | VIKING_PCR_AC));
 	}
 
 	te = lda(rom_ctxtbl, ASI_BYPASS);	/* i.e. context 0 */