Include support for sun4m timers and counters: hardware register layout
has changed. There is a counter for each CPU (currently, just one supported).
This commit is contained in:
pk
parent
df2a68f25b
commit
7b55c61c27
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@ -1,10 +1,13 @@
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/* $NetBSD: clock.c,v 1.35 1996/03/17 02:01:39 thorpej Exp $ */
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/* $NetBSD: clock.c,v 1.36 1996/03/31 23:07:59 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1993 Adam Glass
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* Copyright (c) 1996 Paul Kranenburg
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* Copyright (c) 1996
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* The President and Fellows of Harvard University. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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@ -12,12 +15,14 @@
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University.
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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@ -27,6 +32,8 @@
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* This product includes software developed by Paul Kranenburg.
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* This product includes software developed by Harvard University.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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@ -44,6 +51,7 @@
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* SUCH DAMAGE.
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*
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* @(#)clock.c 8.1 (Berkeley) 6/11/93
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*
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*/
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/*
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@ -69,6 +77,7 @@
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#include <machine/eeprom.h>
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#include <machine/cpu.h>
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#include <sparc/sparc/vaddrs.h>
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#include <sparc/sparc/clockreg.h>
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#include <sparc/sparc/intreg.h>
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#include <sparc/sparc/timerreg.h>
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@ -87,13 +96,9 @@ int statvar = 8192;
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int statmin; /* statclock interval - 1/2*variance */
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int timerok;
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#if defined(SUN4)
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#include <sparc/sparc/intersil7170.h>
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extern struct idprom idprom;
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static int oldclk = 0;
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volatile struct intersil7170 *i7;
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#define intersil_command(run, interrupt) \
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(run | interrupt | INTERSIL_CMD_FREQ_32K | INTERSIL_CMD_24HR_MODE | \
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INTERSIL_CMD_NORMAL_MODE)
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@ -108,15 +113,20 @@ volatile struct intersil7170 *i7;
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#define intersil_clear(CLOCK) CLOCK->clk_intr_reg
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#if defined(SUN4)
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/*
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* OCLOCK support: 4/100's and 4/200's have the old clock.
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* OCLOCK support: 4/100's and 4/200's have the old clock.
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*/
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static int oldclk = 0;
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volatile struct intersil7170 *i7;
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static long oclk_get_secs __P((void));
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static void oclk_get_dt __P((struct date_time *));
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static void dt_to_gmt __P((struct date_time *, long *));
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static void oclk_set_dt __P((struct date_time *));
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static void oclk_set_secs __P((long));
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static void gmt_to_dt __P((long *, struct date_time *));
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#endif
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static int oclockmatch __P((struct device *, void *, void *));
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static void oclockattach __P((struct device *, struct device *, void *));
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@ -129,8 +139,6 @@ struct cfdriver oclock_cd = {
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NULL, "oclock", DV_DULL
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};
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#endif /* SUN4 */
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/*
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* Sun 4 machines use the old-style (a'la Sun 3) EEPROM. On the
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* 4/100's and 4/200's, this is at a separate obio space. On the
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@ -175,6 +183,10 @@ struct cfdriver clock_cd = {
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static int timermatch __P((struct device *, void *, void *));
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static void timerattach __P((struct device *, struct device *, void *));
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volatile struct timer_4m *timerreg_4m; /* XXX - need more cleanup */
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volatile struct counter_4m *counterreg_4m;
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#define timerreg4 ((volatile struct timerreg_4 *)TIMERREG_VA)
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struct cfattach timer_ca = {
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sizeof(struct device), timermatch, timerattach
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};
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@ -192,8 +204,6 @@ void timetochip __P((struct chiptime *));
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/*
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* old clock match routine
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*/
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#if defined(SUN4)
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static int
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oclockmatch(parent, vcf, aux)
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struct device *parent;
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@ -201,7 +211,7 @@ oclockmatch(parent, vcf, aux)
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{
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register struct confargs *ca = aux;
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if (cputyp == CPU_SUN4) {
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if (CPU_ISSUN4) {
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if (cpumod == SUN4_100 || cpumod == SUN4_200)
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return (strcmp(oclock_cd.cd_name, ca->ca_ra.ra_name) == 0);
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return (0);
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@ -215,6 +225,7 @@ oclockattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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#if defined(SUN4)
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struct confargs *ca = aux;
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struct romaux *ra = &ca->ca_ra;
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struct idprom *idp;
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@ -232,8 +243,8 @@ oclockattach(parent, self, aux)
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h |= idp->id_hostid[1] << 8;
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h |= idp->id_hostid[2];
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hostid = h;
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}
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#endif /* SUN4 */
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}
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/*
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* Sun 4/100, 4/200 EEPROM match routine.
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@ -243,11 +254,10 @@ eeprom_match(parent, vcf, aux)
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struct device *parent;
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void *aux, *vcf;
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{
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#if defined(SUN4)
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struct cfdata *cf = vcf;
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struct confargs *ca = aux;
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if (cputyp == CPU_SUN4) {
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if (CPU_ISSUN4) {
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if (cf->cf_unit != 0)
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return (0);
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@ -263,7 +273,6 @@ eeprom_match(parent, vcf, aux)
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return (1);
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}
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}
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#endif /* SUN4 */
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return (0);
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}
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@ -295,14 +304,12 @@ clockmatch(parent, vcf, aux)
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{
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register struct confargs *ca = aux;
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#if defined(SUN4)
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if (cputyp == CPU_SUN4) {
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if (CPU_ISSUN4) {
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if (cpumod == SUN4_300 || cpumod == SUN4_400)
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return (strcmp(clock_cd.cd_name,
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ca->ca_ra.ra_name) == 0);
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return (0);
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}
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#endif /* SUN4 */
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return (strcmp("eeprom", ca->ca_ra.ra_name) == 0);
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}
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@ -319,19 +326,18 @@ clockattach(parent, self, aux)
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struct romaux *ra = &ca->ca_ra;
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char *prop = NULL;
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#if defined(SUN4)
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if (cputyp == CPU_SUN4)
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if (CPU_ISSUN4)
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prop = "mk48t02";
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#endif
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#if defined(SUN4C) || defined(SUN4M)
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if (cputyp == CPU_SUN4C || cputyp == CPU_SUN4M)
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if (CPU_ISSUN4COR4M)
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prop = getpropstring(ra->ra_node, "model");
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#endif
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#ifdef DIAGNOSTIC
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if (prop == NULL)
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panic("no prop");
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#endif
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printf(": %s (eeprom)\n", prop);
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/*
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* We ignore any existing virtual address as we need to map
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* this read-only and make it read-write only temporarily,
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@ -362,7 +368,7 @@ clockattach(parent, self, aux)
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idp = &cl->cl_idprom;
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#if defined(SUN4)
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if (cputyp == CPU_SUN4) {
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if (CPU_ISSUN4) {
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idp = &idprom;
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if (cpumod == SUN4_300 || cpumod == SUN4_400) {
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@ -371,6 +377,7 @@ clockattach(parent, self, aux)
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}
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}
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#endif
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h = idp->id_machine << 24;
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h |= idp->id_hostid[0] << 16;
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h |= idp->id_hostid[1] << 8;
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@ -389,23 +396,20 @@ timermatch(parent, vcf, aux)
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{
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register struct confargs *ca = aux;
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#if defined(SUN4)
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if (cputyp == CPU_SUN4) {
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if (CPU_ISSUN4) {
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if (cpumod == SUN4_300 || cpumod == SUN4_400)
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return (strcmp("timer", ca->ca_ra.ra_name) == 0);
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return (0);
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}
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#endif /* SUN4 */
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#if defined(SUN4C)
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if (cputyp == CPU_SUN4C) {
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if (CPU_ISSUN4C) {
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return (strcmp("counter-timer", ca->ca_ra.ra_name) == 0);
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}
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#endif /* SUN4C */
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#if defined(SUN4M)
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if (cputyp == CPU_SUN4M) {
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if (CPU_ISSUN4M) {
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return (strcmp("counter", ca->ca_ra.ra_name) == 0);
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}
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#endif /* SUN4M */
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return (0);
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}
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@ -419,13 +423,28 @@ timerattach(parent, self, aux)
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register struct romaux *ra = &ca->ca_ra;
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printf("\n");
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/*
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* This time, we ignore any existing virtual address because
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* we have a fixed virtual address for the timer, to make
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* microtime() faster.
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*/
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(void)mapdev(ra->ra_reg, TIMERREG_VA, 0, sizeof(struct timerreg),
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ca->ca_bustype);
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if (CPU_ISSUN4M) {
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(void)mapdev(&ra->ra_reg[ra->ra_nreg-1], TIMERREG_VA, 0,
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sizeof(struct timer_4m), ca->ca_bustype);
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(void)mapdev(&ra->ra_reg[0], COUNTERREG_VA, 0,
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sizeof(struct counter_4m), ca->ca_bustype);
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timerreg_4m = (volatile struct timer_4m *)TIMERREG_VA;
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counterreg_4m = (volatile struct counter_4m *)COUNTERREG_VA;
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/* Put processor counter in "timer" mode */
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timerreg_4m->t_cfg = 0;
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}
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if (CPU_ISSUN4OR4C)
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/*
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* This time, we ignore any existing virtual address because
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* we have a fixed virtual address for the timer, to make
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* microtime() faster (in SUN4/SUN4C kernel only).
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*/
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(void)mapdev(ra->ra_reg, TIMERREG_VA, 0,
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sizeof(struct timerreg_4), ca->ca_bustype);
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timerok = 1;
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/* should link interrupt handlers here, rather than compiled-in? */
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}
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@ -465,9 +484,10 @@ myetheraddr(cp)
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register struct idprom *idp = &cl->cl_idprom;
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#if defined(SUN4)
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if (cputyp == CPU_SUN4)
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if (CPU_ISSUN4)
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idp = &idprom;
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#endif
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cp[0] = idp->id_ether[0];
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cp[1] = idp->id_ether[1];
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cp[2] = idp->id_ether[2];
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@ -515,11 +535,24 @@ delay(n)
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if (timer_cd.cd_ndevs == 0)
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panic("delay");
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c = TIMERREG->t_c10.t_counter;
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while (n-- > 0) {
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while ((t = TIMERREG->t_c10.t_counter) == c)
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continue;
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c = t;
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if (CPU_ISSUN4M) {
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n <<= 1; /* Clock ticks with 500ns period */
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c = timerreg_4m->t_counter;
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while (n-- > 0) {
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while ((t = timerreg_4m->t_counter) == c)
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continue;
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c = t;
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}
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}
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if (CPU_ISSUN4OR4C) {
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c = timerreg4->t_c10.t_counter;
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while (n-- > 0) {
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while ((t = timerreg4->t_c10.t_counter) == c)
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continue;
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c = t;
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}
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}
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}
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@ -537,20 +570,17 @@ cpu_initclocks()
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#if defined(SUN4)
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if (oldclk) {
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int dummy;
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profhz = hz = 100;
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tick = 1000000 / hz;
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i7->clk_intr_reg = INTERSIL_INTER_CSECONDS; /* 1/100 sec */
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ienab_bic(IE_L14 | IE_L10); /* disable all clock intrs */
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intersil_disable(i7); /* disable clock */
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dummy = intersil_clear(i7); /* clear interrupts */
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ienab_bis(IE_L10); /* enable l10 interrupt */
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intersil_enable(i7); /* enable clock */
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ienab_bic(IE_L14 | IE_L10); /* disable all clock intrs */
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intersil_disable(i7); /* disable clock */
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dummy = intersil_clear(i7); /* clear interrupts */
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ienab_bis(IE_L10); /* enable l10 interrupt */
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intersil_enable(i7); /* enable clock */
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return;
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}
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@ -573,10 +603,27 @@ cpu_initclocks()
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minint = statint / 2 + 100;
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while (statvar > minint)
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statvar >>= 1;
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TIMERREG->t_c10.t_limit = tmr_ustolim(tick);
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TIMERREG->t_c14.t_limit = tmr_ustolim(statint);
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if (CPU_ISSUN4M) {
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timerreg_4m->t_limit = tmr_ustolim(tick);
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counterreg_4m->t_limit = tmr_ustolim(statint);
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}
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if (CPU_ISSUN4OR4C) {
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timerreg4->t_c10.t_limit = tmr_ustolim(tick);
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timerreg4->t_c14.t_limit = tmr_ustolim(statint);
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}
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statmin = statint - (statvar >> 1);
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ienab_bis(IE_L14 | IE_L10);
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#if defined(SUN4M)
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if (CPU_ISSUN4M)
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ienab_bic(SINTR_T);
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#endif
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if (CPU_ISSUN4OR4C)
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ienab_bis(IE_L14 | IE_L10);
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}
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/*
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@ -620,7 +667,13 @@ clockintr(cap)
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}
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#endif
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/* read the limit register to clear the interrupt */
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discard = TIMERREG->t_c10.t_limit;
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if (CPU_ISSUN4M) {
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discard = timerreg_4m->t_limit;
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}
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if (CPU_ISSUN4OR4C) {
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discard = timerreg4->t_c10.t_limit;
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}
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#if defined(SUN4)
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forward:
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#endif
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@ -651,7 +704,20 @@ statintr(cap)
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#endif
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/* read the limit register to clear the interrupt */
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discard = TIMERREG->t_c14.t_limit;
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if (CPU_ISSUN4M) {
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discard = counterreg_4m->t_limit;
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if (timerok == 0) {
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/* Stop the clock */
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counterreg_4m->t_limit = 0;
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counterreg_4m->t_ss = 0;
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timerreg_4m->t_cfg = TMR_CFG_USER;
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return 1;
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}
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}
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if (CPU_ISSUN4OR4C) {
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discard = timerreg4->t_c14.t_limit;
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}
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statclock((struct clockframe *)cap);
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/*
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@ -665,7 +731,13 @@ statintr(cap)
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} while (r == 0);
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newint = statmin + r;
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TIMERREG->t_c14.t_limit = tmr_ustolim(newint);
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if (CPU_ISSUN4M) {
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counterreg_4m->t_limit = tmr_ustolim(newint);
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}
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if (CPU_ISSUN4OR4C) {
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timerreg4->t_c14.t_limit = tmr_ustolim(newint);
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}
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return (1);
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}
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@ -1116,7 +1188,7 @@ eeprom_uio(uio)
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u_int cnt, bcnt;
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caddr_t buf = NULL;
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if (cputyp != CPU_SUN4)
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if (!CPU_ISSUN4)
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return (ENODEV);
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off = uio->uio_offset;
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