Add sun4m VA definitions (for clock and interrupt).
Make these generic for all architectures (i.e. avoid `#if defined(SUN4*)'s).
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pk
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ff109a19a3
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@ -1,4 +1,4 @@
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/* $NetBSD: intreg.h,v 1.4 1996/02/01 22:32:45 mycroft Exp $ */
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/* $NetBSD: intreg.h,v 1.5 1996/03/31 23:03:39 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -44,6 +44,8 @@
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* @(#)intreg.h 8.1 (Berkeley) 6/11/93
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*/
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#include <sparc/sparc/vaddrs.h>
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/*
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* sun4c interrupt enable register.
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*
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@ -75,7 +77,16 @@ void ienab_bic __P((int bic)); /* clear given bits */
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#endif
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#if defined(SUN4M)
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#define ICR_REG_PHYSADR 0x71e00000 /* XXX - phys addr in IOspace */
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#ifdef notyet
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#define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc)
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#define IENAB_P0 0x0008
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#define IENAB_P1 0x1008
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#define IENAB_P2 0x2008
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#define IENAB_P3 0x3008
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#endif /* notyet */
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#endif
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#if defined(SUN4M)
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/*
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* Interrupt Control Registers, located in IO space.
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* (mapped to `locore' for now..)
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@ -83,21 +94,27 @@ void ienab_bic __P((int bic)); /* clear given bits */
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* and `System Interrupts'. The `Processor' set corresponds to the 15
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* interrupt levels as seen by the CPU. The `System' set corresponds to
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* a set of devices supported by the implementing chip-set.
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*
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* Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are
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* system-wide interrupts, and the ICR_ITR selects the processor to get
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* the system's interrupts.
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*/
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#define ICR_PI_PEND (IE_reg_addr + 0x0)
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#define ICR_PI_CLR (IE_reg_addr + 0x4)
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#define ICR_PI_SET (IE_reg_addr + 0x8)
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#define ICR_SI_PEND (IE_reg_addr + 0x1000)
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#define ICR_SI_MASK (IE_reg_addr + 0x1004)
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#define ICR_SI_CLR (IE_reg_addr + 0x1008)
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#define ICR_SI_SET (IE_reg_addr + 0x100c)
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#define ICR_PI_PEND (PI_INTR_VA + 0x0)
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#define ICR_PI_CLR (PI_INTR_VA + 0x4)
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#define ICR_PI_SET (PI_INTR_VA + 0x8)
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#define ICR_SI_PEND (SI_INTR_VA)
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#define ICR_SI_MASK (SI_INTR_VA + 0x4)
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#define ICR_SI_CLR (SI_INTR_VA + 0x8)
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#define ICR_SI_SET (SI_INTR_VA + 0xc)
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#define ICR_ITR (SI_INTR_VA + 0x10)
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/*
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* Bits in interrupt registers. Software interrupt requests must
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* be cleared in software. This is done in locore.s.
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* There are separate registers for reading pending interrupts and
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* setting/clearing (software) interrupts.
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*/
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#define PINTR_SOFTINTR(n) ((n)) << 16)
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#define PINTR_SINTRLEV(n) (1 << (16 + (n)))
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#define PINTR_IC 0x8000 /* Level 15 clear */
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#define SINTR_MA 0x80000000 /* Mask All interrupts */
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@ -1,6 +1,8 @@
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/* $NetBSD: vaddrs.h,v 1.5 1994/12/06 08:34:14 deraadt Exp $ */
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/* $NetBSD: vaddrs.h,v 1.6 1996/03/31 23:03:31 pk Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard University. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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@ -25,6 +27,7 @@
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* This product includes software developed by Harvard University.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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@ -59,24 +62,57 @@
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* the Zilog ZSCC serial port chips to be mapped at fixed VAs to make
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* microtime() and the zs hardware interrupt handlers faster.
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*
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* [sun4/sun4c:]
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* Ideally, we should map the interrupt enable register here as well,
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* but that would require allocating pmegs in locore.s, so instead we
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* use one of the two `wasted' pages at KERNBASE+2*NBPG (see locore.s).
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* use one of the two `wasted' pages at KERNBASE+_MAXNBPG (see locore.s).
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*/
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#ifndef IODEV_0
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#define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */
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#define _MAXNBPG 8192 /* fixed VAs, independent of actual NBPG */
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#define _MAXNCPU 4 /* fixed VA allocation allows 4 CPUs */
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/* [4m:] interrupt and counter registers take (1 + NCPU) pages. */
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#define TIMERREG_VA (IODEV_0)
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#define ZS0_VA (IODEV_0 + 1*NBPG)
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#define ZS1_VA (IODEV_0 + 2*NBPG)
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#define AUXREG_VA (IODEV_0 + 3*NBPG)
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#define TMPMAP_VA (IODEV_0 + 4*NBPG)
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#define MSGBUF_VA (IODEV_0 + 5*NBPG)
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#define IODEV_BASE (IODEV_0 + 6*NBPG)
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#define COUNTERREG_VA ( TIMERREG_VA + _MAXNBPG*_MAXNCPU) /* [4m] */
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#define ZS0_VA (COUNTERREG_VA + _MAXNBPG)
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#define ZS1_VA ( ZS0_VA + _MAXNBPG)
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#define AUXREG_VA ( ZS1_VA + _MAXNBPG)
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#define TMPMAP_VA ( AUXREG_VA + _MAXNBPG)
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#define MSGBUF_VA ( TMPMAP_VA + _MAXNBPG)
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#define PI_INTR_VA ( MSGBUF_VA + _MAXNBPG) /* [4m] */
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#define SI_INTR_VA ( PI_INTR_VA + _MAXNBPG*_MAXNCPU) /* [4m] */
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#define IODEV_BASE ( SI_INTR_VA + _MAXNBPG)
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#define IODEV_END 0xff000000 /* 16 MB of iospace */
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#define DVMA_BASE 0xfff00000
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#define DVMA_END 0xfffc0000
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/*
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* The next constant defines the amount of reserved DVMA space on the
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* Sun4m. The amount of space *must* be a multiple of 16MB, and thus
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* (((u_int)0) - DVMA4M_BASE) must be divisible by 16*1024*1024!
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* Note that pagetables must be allocated at a cost of 1k per MB of DVMA
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* space, plus severe alignment restrictions. So don't make DVMA4M_BASE too
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* low (max space = 2G).
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*
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* Since DVMA space overlaps with normal kernel address space (notably
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* the device mappings and the PROM), we don't want to put any DVMA
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* mappings where any of this useful stuff is (i.e. if we dvma_malloc
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* a buffer, we want to still have a SRMMU mapping to it, and we can't
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* have that if its on top of kernel code). Thus the last two
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* constants define the actual DVMA addresses used. These can be anything
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* as long as they are within the bounds setup by the first 2 constants.
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* This is especially important on MP systems with cache coherency: to
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* avoid consistency problems, DVMA addresses must map to the same place
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* in both processor and IOMMU space.
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*/
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#define DVMA4M_BASE 0xfc000000 /* can change subject to above rule */
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#define DVMA4M_TOP 0xffffffff /* do not modify */
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#define DVMA4M_START 0xfd000000 /* 16M of DVMA */
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#define DVMA4M_END 0xfe000000 /* XXX is this enough? */
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#endif /* IODEV_0 */
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