add plumbing to support bus_space_mmap() with:
- write combining allowed via BUS_SPACE_MAP_PREFETCHABLE - byte order translation via BUS_SPACE_MAP_LITTLE
This commit is contained in:
macallan
parent
374e459041
commit
7a874cfdc6
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@ -1,4 +1,4 @@
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/* $NetBSD: bus_defs.h,v 1.3 2016/07/07 06:55:38 msaitoh Exp $ */
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/* $NetBSD: bus_defs.h,v 1.4 2016/11/04 05:41:01 macallan Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
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@ -171,6 +171,7 @@ struct sparc_bus_space_tag {
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#define BUS_SPACE_MAP_BUS2 0x0200
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#define BUS_SPACE_MAP_BUS3 0x0400
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#define BUS_SPACE_MAP_BUS4 0x0800
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#define BUS_SPACE_MAP_LITTLE 0x1000
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/* sparc uses this, it's not supposed to do anything on sparc64 */
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#define BUS_SPACE_MAP_LARGE 0
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.60 2015/09/06 23:48:39 nakayama Exp $ */
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/* $NetBSD: pmap.h,v 1.61 2016/11/04 05:41:01 macallan Exp $ */
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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@ -164,7 +164,7 @@ struct prom_map {
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uint64_t tte;
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};
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#define PMAP_NC 0x001 /* Set the E bit in the page */
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#define PMAP_NC 0x001 /* Don't cache, set the E bit in the page */
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#define PMAP_NVC 0x002 /* Don't enable the virtual cache */
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#define PMAP_LITTLE 0x004 /* Map in little endian mode */
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/* Large page size hints --
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@ -177,6 +177,7 @@ struct prom_map {
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/* If these bits are different in va's to the same PA
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then there is an aliasing in the d$ */
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#define VA_ALIAS_MASK (1 << 13)
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#define PMAP_WC 0x20 /* allow write combinimg */
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#ifdef _KERNEL
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#ifdef PMAP_COUNT_DEBUG
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@ -1,4 +1,4 @@
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/* $NetBSD: pte.h,v 1.27 2015/04/03 10:07:57 palle Exp $ */
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/* $NetBSD: pte.h,v 1.28 2016/11/04 05:41:01 macallan Exp $ */
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/*
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* Copyright (c) 1996-1999 Eduardo Horvath
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@ -254,21 +254,21 @@ typedef struct sun4u_tte pte_t;
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#define SUN4V_TLB_W 0x0000000000000040LL
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#define SUN4V_TLB_G 0x0000000000000000LL
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#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
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#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) \
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(((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|(((uint64_t)(pa))&SUN4U_TLB_PA_MASK)|\
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((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):SUN4U_TLB_E)|\
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((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):((wc)?0LL:SUN4U_TLB_E))|\
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((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|((ie)?SUN4U_TLB_IE:0LL))
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#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
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#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) \
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(((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\
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(((u_int64_t)(pa))&SUN4V_TLB_PA_MASK)|\
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((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):SUN4V_TLB_E)|\
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((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):((wc)?0LL:SUN4V_TLB_E))|\
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((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\
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((ie)?SUN4V_TLB_IE:0LL))
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#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
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(CPU_ISSUN4V ? SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) : \
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SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie))
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#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) \
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(CPU_ISSUN4V ? SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) : \
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SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc))
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#define TLB_EXEC (CPU_ISSUN4V ? SUN4V_TLB_EXEC : SUN4U_TLB_EXEC)
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#define TLB_V (CPU_ISSUN4V ? SUN4V_TLB_V : SUN4U_TLB_V)
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@ -283,6 +283,7 @@ typedef struct sun4u_tte pte_t;
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#define TLB_EXEC_ONLY (CPU_ISSUN4V ? SUN4V_TLB_EXEC_ONLY : SUN4U_TLB_EXEC_ONLY)
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#define TLB_L (CPU_ISSUN4V ? 0 : SUN4U_TLB_L)
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#define TLB_CV (CPU_ISSUN4V ? SUN4V_TLB_CV : SUN4U_TLB_CV)
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#define TLB_IE (CPU_ISSUN4V ? SUN4V_TLB_IE : SUN4U_TLB_IE)
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#define MMU_CACHE_VIRT 0x3
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#define MMU_CACHE_PHYS 0x2
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.285 2016/07/07 06:55:38 msaitoh Exp $ */
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/* $NetBSD: machdep.c,v 1.286 2016/11/04 05:41:01 macallan Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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@ -71,7 +71,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.285 2016/07/07 06:55:38 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.286 2016/11/04 05:41:01 macallan Exp $");
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#include "opt_ddb.h"
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#include "opt_multiprocessor.h"
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@ -2357,8 +2357,14 @@ paddr_t
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sparc_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot,
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int flags)
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{
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paddr_t pa;
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/* Devices are un-cached... although the driver should do that */
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return ((paddr+off)|PMAP_NC);
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pa = (paddr + off) | PMAP_NC;
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if (flags & BUS_SPACE_MAP_LITTLE)
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pa |= PMAP_LITTLE;
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if (flags & BUS_SPACE_MAP_PREFETCHABLE)
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pa |= PMAP_WC;
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return pa;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.303 2016/07/07 06:55:38 msaitoh Exp $ */
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/* $NetBSD: pmap.c,v 1.304 2016/11/04 05:41:01 macallan Exp $ */
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/*
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*
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* Copyright (C) 1996-1999 Eduardo Horvath.
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@ -26,7 +26,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.303 2016/07/07 06:55:38 msaitoh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.304 2016/11/04 05:41:01 macallan Exp $");
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#undef NO_VCACHE /* Don't forget the locked TLB in dostart */
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#define HWREF
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@ -560,7 +560,8 @@ pmap_mp_init(void)
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1, /* cache */
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1, /* aliased */
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1, /* valid */
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0 /* ie */);
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0, /* ie */
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0 /* wc */);
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tp[i].data |= TLB_L | TLB_CV;
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if (i >= kernel_itlb_slots) {
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@ -1076,7 +1077,8 @@ pmap_bootstrap(u_long kernelstart, u_long kernelend)
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1 /* Cacheable */,
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FORCE_ALIAS /* ALIAS -- Disable D$ */,
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1 /* valid */,
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0 /* IE */);
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0 /* IE */,
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0 /* wc */);
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pmap_enter_kpage(va, data);
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va += PAGE_SIZE;
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msgbufsiz -= PAGE_SIZE;
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@ -1137,7 +1139,8 @@ pmap_bootstrap(u_long kernelstart, u_long kernelend)
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1 /* Cacheable */,
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FORCE_ALIAS /* ALIAS -- Disable D$ */,
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1 /* valid */,
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0 /* IE */);
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0 /* ei */,
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0 /* WC */);
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pmap_enter_kpage(vmmap, data1);
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vmmap += PAGE_SIZE;
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}
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@ -1179,7 +1182,8 @@ pmap_bootstrap(u_long kernelstart, u_long kernelend)
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1 /* Cacheable */,
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FORCE_ALIAS /* ALIAS -- Disable D$ */,
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1 /* valid */,
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0 /* IE */);
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0 /* IE */,
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0 /* wc */);
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pmap_enter_kpage(vmmap, data1);
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vmmap += PAGE_SIZE;
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pa += PAGE_SIZE;
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@ -1366,7 +1370,8 @@ pmap_init(void)
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1 /* Cacheable */,
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FORCE_ALIAS /* ALIAS -- Disable D$ */,
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1 /* valid */,
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0 /* IE */);
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0 /* IE */,
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0 /* wc */);
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pmap_enter_kpage(va, data);
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va += PAGE_SIZE;
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}
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@ -1656,7 +1661,8 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
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tte.data = TSB_DATA(0, PGSZ_8K, pa, 1 /* Privileged */,
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(VM_PROT_WRITE & prot),
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!(pa & PMAP_NC), pa & (PMAP_NVC), 1, 0);
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!(pa & PMAP_NC), pa & (PMAP_NVC), 1,
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pa & (PMAP_LITTLE), pa & PMAP_WC);
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/* We don't track mod/ref here. */
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if (prot & VM_PROT_WRITE)
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tte.data |= TLB_REAL_W|TLB_W;
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@ -1879,7 +1885,7 @@ pmap_enter(struct pmap *pm, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags)
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}
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tte.data = TSB_DATA(0, size, pa, pm == pmap_kernel(),
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flags & VM_PROT_WRITE, !(pa & PMAP_NC),
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uncached, 1, pa & PMAP_LITTLE);
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uncached, 1, pa & PMAP_LITTLE, pa & PMAP_WC);
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#ifdef HWREF
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if (prot & VM_PROT_WRITE)
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tte.data |= TLB_REAL_W;
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1 /* Cacheable */,
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FORCE_ALIAS /* ALIAS -- Disable D$ */,
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1 /* valid */,
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0 /* IE */);
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0 /* IE */,
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0 /* wc */);
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hv_rc = hv_mmu_map_perm_addr(INTSTACK, data, MAP_DTLB);
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if ( hv_rc != H_EOK ) {
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panic("hv_mmu_map_perm_addr() failed - rc = %" PRId64 "\n",
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