Support for several new cards pulled from magnum branch.
Format police.
This commit is contained in:
mycroft
parent
8519570fa2
commit
6839509d86
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@ -1,35 +1,7 @@
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/*
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* National Semiconductor DS8390 NIC register definitions
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*
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* $Id: if_edreg.h,v 1.5 1993/10/01 02:01:46 davidg Exp $
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*
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* Modification history
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*
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* Revision 2.0 93/09/29 00:37:15 davidg
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* changed double buffering flag to multi buffering
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* made changes/additions for 3c503 multi-buffering
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* ...companion to Rev. 2.0 of 'ed' driver.
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*
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* Revision 1.6 93/09/28 17:20:03 davidg
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* first cut at PIO (e.g. NE1000/2000) support
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*
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* Revision 1.5 93/08/25 20:38:34 davidg
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* added define for card type WD8013WC (10BaseT)
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*
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* Revision 1.4 93/08/14 20:07:55 davidg
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* fix board type definition for 8013EP
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*
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* Revision 1.3 93/07/20 15:25:25 davidg
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* added config flags for forcing 8/16bit mode and disabling double
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* xmit buffers.
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*
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* Revision 1.2 93/06/23 03:03:05 davidg
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* added some additional definitions for the 83C584 bus interface
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* chip (SMC/WD boards)
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*
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* Revision 1.1 93/06/23 03:01:07 davidg
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* Initial revision
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*
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* $Id: if_edreg.h,v 1.6 1994/02/12 07:16:33 mycroft Exp $
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*/
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/*
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@ -614,6 +586,11 @@ struct ed_ring {
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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#ifdef TOSH_ETHER
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#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
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#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
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#define ED_WD_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */
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#endif
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/*
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* Interface Configuration Register (ICR)
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@ -628,6 +605,14 @@ struct ed_ring {
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#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
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#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
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#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
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#ifdef TOSH_ETHER
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#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
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#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
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0x02 = 16K, 0x01 = 8K */
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/* 64K can only be used if mem address
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above 1MB */
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/* IAR holds address A23-A16 (R/W) */
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#endif
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/*
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* IO Address Register (IAR)
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@ -687,10 +672,17 @@ struct ed_ring {
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#define ED_TYPE_WD8003S 0x02
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#define ED_TYPE_WD8003E 0x03
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#define ED_TYPE_WD8013EBT 0x05
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#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
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#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
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#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
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#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
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#define ED_TYPE_WD8013W 0x26
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#define ED_TYPE_WD8013EP 0x27
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#define ED_TYPE_WD8013WC 0x28
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#define ED_TYPE_WD8013EBP 0x2c
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#define ED_TYPE_WD8013EPC 0x29
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#define ED_TYPE_SMC8216T 0x2a
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#define ED_TYPE_SMC8216C 0x2b
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/* Bit definitions in card ID */
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#define ED_WD_REV_MASK 0x1f /* Revision mask */
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@ -701,7 +693,11 @@ struct ed_ring {
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/*
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* Checksum total. All 8 bytes in station address PROM will add up to this
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*/
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#ifdef TOSH_ETHER
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#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
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#else
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#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
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#endif
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#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
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#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
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1780
sys/dev/isa/if_ed.c
1780
sys/dev/isa/if_ed.c
File diff suppressed because it is too large
Load Diff
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@ -1,35 +1,7 @@
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/*
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* National Semiconductor DS8390 NIC register definitions
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*
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* $Id: if_edreg.h,v 1.5 1993/10/01 02:01:46 davidg Exp $
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*
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* Modification history
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*
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* Revision 2.0 93/09/29 00:37:15 davidg
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* changed double buffering flag to multi buffering
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* made changes/additions for 3c503 multi-buffering
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* ...companion to Rev. 2.0 of 'ed' driver.
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*
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* Revision 1.6 93/09/28 17:20:03 davidg
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* first cut at PIO (e.g. NE1000/2000) support
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*
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* Revision 1.5 93/08/25 20:38:34 davidg
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* added define for card type WD8013WC (10BaseT)
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*
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* Revision 1.4 93/08/14 20:07:55 davidg
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* fix board type definition for 8013EP
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*
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* Revision 1.3 93/07/20 15:25:25 davidg
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* added config flags for forcing 8/16bit mode and disabling double
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* xmit buffers.
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*
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* Revision 1.2 93/06/23 03:03:05 davidg
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* added some additional definitions for the 83C584 bus interface
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* chip (SMC/WD boards)
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*
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* Revision 1.1 93/06/23 03:01:07 davidg
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* Initial revision
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*
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* $Id: if_edreg.h,v 1.6 1994/02/12 07:16:33 mycroft Exp $
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*/
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/*
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@ -614,6 +586,11 @@ struct ed_ring {
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#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define ED_WD_MSR_MENB 0x40 /* Memory enable */
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#define ED_WD_MSR_RST 0x80 /* Reset board */
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#ifdef TOSH_ETHER
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#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
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#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
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#define ED_WD_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */
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#endif
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/*
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* Interface Configuration Register (ICR)
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@ -628,6 +605,14 @@ struct ed_ring {
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#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
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#define ED_WD_ICR_RIO 0x40 /* recall i/o address */
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#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
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#ifdef TOSH_ETHER
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#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
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#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
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0x02 = 16K, 0x01 = 8K */
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/* 64K can only be used if mem address
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above 1MB */
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/* IAR holds address A23-A16 (R/W) */
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#endif
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/*
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* IO Address Register (IAR)
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@ -687,10 +672,17 @@ struct ed_ring {
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#define ED_TYPE_WD8003S 0x02
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#define ED_TYPE_WD8003E 0x03
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#define ED_TYPE_WD8013EBT 0x05
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#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
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#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
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#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
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#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
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#define ED_TYPE_WD8013W 0x26
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#define ED_TYPE_WD8013EP 0x27
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#define ED_TYPE_WD8013WC 0x28
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#define ED_TYPE_WD8013EBP 0x2c
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#define ED_TYPE_WD8013EPC 0x29
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#define ED_TYPE_SMC8216T 0x2a
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#define ED_TYPE_SMC8216C 0x2b
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/* Bit definitions in card ID */
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#define ED_WD_REV_MASK 0x1f /* Revision mask */
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@ -701,7 +693,11 @@ struct ed_ring {
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/*
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* Checksum total. All 8 bytes in station address PROM will add up to this
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*/
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#ifdef TOSH_ETHER
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#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
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#else
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#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
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#endif
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#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
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#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
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