Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't

Browse Source 
require flushing (even in the instruction cache handlers).  This gives
about a 4% improvement in a "make depend" benchmark.

Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers.  This gives about
a 5% improvement in a "make depend" benchmark.
This commit is contained in:
simonb 2002-12-17 12:07:50 +00:00
parent 2c1a832f25
commit 5b6caeca74
1 changed files with 18 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.155 2002/11/15 01:16:18 simonb Exp $ */ /* $NetBSD: mips_machdep.c,v 1.156 2002/12/17 12:07:50 simonb Exp $ */
/* /*
* Copyright 2002 Wasabi Systems, Inc. * Copyright 2002 Wasabi Systems, Inc.
@ -120,7 +120,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.155 2002/11/15 01:16:18 simonb Exp $"); __KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.156 2002/12/17 12:07:50 simonb Exp $");
#include "opt_cputype.h" #include "opt_cputype.h"
@ -380,26 +380,33 @@ static const struct pridtab cputab[] = {
MIPS64_FLAGS, "20Kc" }, MIPS64_FLAGS, "20Kc" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0, { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 1 core)" }, MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
"Au1000 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0, { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 2 core)" }, MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
"Au1000 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0, { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1500 (Rev 1 core)" }, MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
"Au1500 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0, { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1500 (Rev 2 core)" }, MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
"Au1500 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0, { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1100 (Rev 1 core)" }, MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
"Au1100 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0, { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1100 (Rev 2 core)" }, MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
"Au1100 (Rev 2 core)" },
/* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */ /* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */
{ MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, -1, 0, { MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, -1, 0,
MIPS64_FLAGS | CPU_MIPS_HAVE_SPECIAL_CCA | \ MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT |
(5 << CPU_MIPS_CACHED_CCA_SHIFT), "SB1" }, CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT),
"SB1" },
{ 0, 0, 0, 0, 0, 64, { 0, 0, 0, 0, 0, 0,
0, NULL } 0, NULL }
}; };