Use the free-running microsecond counter on the Maxine for high-resolution
clock.
This commit is contained in:
mhitch
parent
4c88f43717
commit
5170e3eccc
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@ -1,4 +1,4 @@
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/* $NetBSD: machdep.c,v 1.95 1997/08/12 01:52:10 jonathan Exp $ */
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/* $NetBSD: machdep.c,v 1.96 1997/08/17 18:13:22 mhitch Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -227,7 +227,7 @@ static void asic_init __P((int isa_maxine));
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#endif
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extern int atoi __P((const char *cp));
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int initcpu __P((void));
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#ifdef DS5000_240
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#if defined(DS5000_240) || defined(DS5000_25)
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static u_long clkread __P((void)); /* get usec-resolution clock */
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#endif
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void dumpsys __P((void)); /* do a dump */
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@ -257,7 +257,6 @@ void xine_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
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#ifdef DS5000_240
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u_long kn03_tc3_imask;
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extern u_long latched_cycle_cnt;
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void kn03_tc_reset __P((void)); /* XXX unused? */
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void kn03_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
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intr_arg_t sc, int onoff));
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@ -1185,12 +1184,13 @@ haltsys:
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* the current microsecond offset from time-of-day.
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*/
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#ifndef DS5000_240
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#if !defined(DS5000_240) && !defined(DS5000_25)
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# define clkread() (0)
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#else
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/*
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* IOASIC TC cycle counter, latched on every interrupt from RTC chip.
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* [Or free-running microsecond counter on Maxine.]
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*/
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u_long latched_cycle_cnt;
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@ -1199,22 +1199,32 @@ u_long latched_cycle_cnt;
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* to interpolate micro-seconds since the last RTC clock tick.
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* The interpolation base is the copy of the bus cycle-counter taken
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* by the RTC interrupt handler.
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* XXX on XINE, use the microsecond free-running counter.
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* On XINE, use the microsecond free-running counter.
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*
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*/
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static inline u_long
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clkread()
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{
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#ifdef DS5000_240
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register u_long usec, cycles; /* really 32 bits? */
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#endif
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/* only support 5k/240 TC bus counter */
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if (pmax_boardtype != DS_3MAXPLUS) {
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return (0);
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}
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#ifdef DS5000_25
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if (pmax_boardtype == DS_MAXINE)
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return (*(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR)) -
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latched_cycle_cnt);
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else
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#endif
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#ifdef DS5000_240
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if (pmax_boardtype == DS_3MAXPLUS)
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/* 5k/240 TC bus counter */
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cycles = *(u_long*)IOASIC_REG_CTR(ioasic_base);
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else
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#endif
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return (0);
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#ifdef DS5000_240
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/* Compute difference in cycle count from last hardclock() to now */
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#if 1
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/* my code, using u_ints */
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@ -1243,6 +1253,7 @@ clkread()
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}
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#endif /*CLOCK_DEBUG*/
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return usec;
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#endif /*DS5000_240*/
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}
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#if 0
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@ -1252,7 +1263,7 @@ microset()
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latched_cycle_cnt = *(u_long*)(IOASIC_REG_CTR(ioasic_base));
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}
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#endif
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#endif /*DS5000_240*/
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#endif /*DS5000_240 || DS5000_25*/
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: pmax_trap.c,v 1.49 1997/08/06 12:03:34 jonathan Exp $ */
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/* $NetBSD: pmax_trap.c,v 1.50 1997/08/17 18:13:25 mhitch Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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@ -122,18 +122,21 @@ static void kn02_errintr __P((void)), kn02ba_errintr __P((void));
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#ifdef DS5000_240
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static void kn03_errintr __P ((void));
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extern u_long kn03_tc3_imask;
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extern u_long ioasic_base; /* Base address of I/O asic */
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#endif /*DS5000_240*/
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/*
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* IOASIC 40ns bus-cycle counter, used as hi-resolution clock:
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* may also be present on (some) XINE, 3min hardware, but not tested there.
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* [doesn't work on my 5000/25 or 5000/50 - mhitch]
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*/
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extern u_long ioasic_base; /* Base address of I/O asic */
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#if defined(DS5000_240) || defined(DS5000_25)
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u_long latched_cycle_cnt; /*
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* IOASIC cycle counter, latched on every
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* interrupt from RTC chip (64Hz).
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* [free-running counter on Maxine]
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*/
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#endif /*DS5000_240*/
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#endif /*DS5000_240 || DS5000_25*/
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static unsigned kn02ba_recover_erradr __P((u_int phys, u_int mer));
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extern tc_option_t tc_slot_info[TC_MAX_LOGICAL_SLOTS];
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@ -454,6 +457,7 @@ kmin_intr(mask, pc, statusReg, causeReg)
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MIPS_SR_INT_ENA_CUR);
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}
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#ifdef DS5000_25
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/*
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* Maxine hardware interrupts. (Personal DECstation 5000/xx)
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*/
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@ -486,6 +490,8 @@ xine_intr(mask, pc, statusReg, causeReg)
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temp = c->regc; /* XXX clear interrupt bits */
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cf.pc = pc;
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cf.sr = statusReg;
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latched_cycle_cnt =
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*(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR));
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hardclock(&cf);
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intrcnt[HARDCLOCK]++;
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/* keep clock interrupts enabled when we return */
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@ -591,6 +597,7 @@ xine_intr(mask, pc, statusReg, causeReg)
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return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
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MIPS_SR_INT_ENA_CUR);
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}
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#endif /* DS5000_25 */
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#ifdef DS5000_240
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/*
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