diff --git a/sys/arch/pmax/pmax/machdep.c b/sys/arch/pmax/pmax/machdep.c
index d56ab1ca12b3..8df0833aeff1 100644
--- a/sys/arch/pmax/pmax/machdep.c
+++ b/sys/arch/pmax/pmax/machdep.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.95 1997/08/12 01:52:10 jonathan Exp $	*/
+/*	$NetBSD: machdep.c,v 1.96 1997/08/17 18:13:22 mhitch Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -227,7 +227,7 @@ static	void asic_init __P((int isa_maxine));
 #endif
 extern	int	atoi __P((const char *cp));
 int	initcpu __P((void));
-#ifdef DS5000_240
+#if defined(DS5000_240) || defined(DS5000_25)
 static	u_long	clkread __P((void));	/* get usec-resolution clock */
 #endif
 void	dumpsys __P((void));		/* do a dump */
@@ -257,7 +257,6 @@ void	xine_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
 
 #ifdef DS5000_240
 u_long	kn03_tc3_imask;
-extern	u_long latched_cycle_cnt;
 void	kn03_tc_reset __P((void));		/* XXX unused? */
 void	kn03_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
 			       intr_arg_t sc, int onoff));
@@ -1185,12 +1184,13 @@ haltsys:
  * the current microsecond offset from time-of-day.
  */
 
-#ifndef DS5000_240
+#if !defined(DS5000_240) && !defined(DS5000_25)
 # define clkread() (0)
 #else
 
 /*
  * IOASIC TC cycle counter, latched on every interrupt from RTC chip.
+ * [Or free-running microsecond counter on Maxine.]
  */
 u_long latched_cycle_cnt;
 
@@ -1199,22 +1199,32 @@ u_long latched_cycle_cnt;
  * to interpolate micro-seconds since the  last RTC clock tick.
  * The interpolation base is the copy of the bus cycle-counter taken
  * by the RTC interrupt handler.
- * XXX on XINE, use the microsecond free-running counter.
+ * On XINE, use the microsecond free-running counter.
  *
  */
 static inline u_long
 clkread()
 {
 
+#ifdef DS5000_240
 	register u_long usec, cycles;	/* really 32 bits? */
+#endif
 
-	/* only support 5k/240 TC bus counter */
-	if (pmax_boardtype != DS_3MAXPLUS) {
+#ifdef DS5000_25
+	if (pmax_boardtype == DS_MAXINE)
+		return (*(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR)) -
+		    latched_cycle_cnt);
+	else
+#endif
+#ifdef DS5000_240
+	if (pmax_boardtype == DS_3MAXPLUS)
+		/* 5k/240 TC bus counter */
+		cycles = *(u_long*)IOASIC_REG_CTR(ioasic_base);
+	else
+#endif
 		return (0);
-	}
-
-	cycles = *(u_long*)IOASIC_REG_CTR(ioasic_base);
 
+#ifdef DS5000_240
 	/* Compute difference in cycle count from last hardclock() to now */
 #if 1
 	/* my code, using u_ints */
@@ -1243,6 +1253,7 @@ clkread()
 	}
 #endif /*CLOCK_DEBUG*/
 	return usec;
+#endif /*DS5000_240*/
 }
 
 #if 0
@@ -1252,7 +1263,7 @@ microset()
 		latched_cycle_cnt = *(u_long*)(IOASIC_REG_CTR(ioasic_base));
 }
 #endif
-#endif /*DS5000_240*/
+#endif /*DS5000_240 || DS5000_25*/
 
 
 /*
diff --git a/sys/arch/pmax/pmax/pmax_trap.c b/sys/arch/pmax/pmax/pmax_trap.c
index b3b080ea7110..9292acebe00b 100644
--- a/sys/arch/pmax/pmax/pmax_trap.c
+++ b/sys/arch/pmax/pmax/pmax_trap.c
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmax_trap.c,v 1.49 1997/08/06 12:03:34 jonathan Exp $	*/
+/*	$NetBSD: pmax_trap.c,v 1.50 1997/08/17 18:13:25 mhitch Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -122,18 +122,21 @@ static void kn02_errintr __P((void)), kn02ba_errintr __P((void));
 #ifdef DS5000_240
 static void kn03_errintr __P ((void));
 extern u_long kn03_tc3_imask;
+extern u_long ioasic_base;	/* Base address of I/O asic */
+#endif /*DS5000_240*/
 
 /*
-
  * IOASIC 40ns bus-cycle counter, used as hi-resolution clock:
  * may also be present on (some) XINE, 3min hardware, but not tested there.
+ * [doesn't work on my 5000/25 or 5000/50 - mhitch]
  */
-extern u_long ioasic_base;	/* Base address of I/O asic */
+#if defined(DS5000_240) || defined(DS5000_25)
 u_long latched_cycle_cnt;	/*
 				 * IOASIC cycle counter, latched on every
 				 * interrupt from RTC chip (64Hz).
+				 * [free-running counter on Maxine]
 				 */
-#endif /*DS5000_240*/
+#endif /*DS5000_240 || DS5000_25*/
 
 static unsigned kn02ba_recover_erradr __P((u_int phys, u_int mer));
 extern tc_option_t tc_slot_info[TC_MAX_LOGICAL_SLOTS];
@@ -454,6 +457,7 @@ kmin_intr(mask, pc, statusReg, causeReg)
 		MIPS_SR_INT_ENA_CUR);
 }
 
+#ifdef DS5000_25
 /*
  * Maxine hardware interrupts. (Personal DECstation 5000/xx)
  */
@@ -486,6 +490,8 @@ xine_intr(mask, pc, statusReg, causeReg)
 		temp = c->regc;	/* XXX clear interrupt bits */
 		cf.pc = pc;
 		cf.sr = statusReg;
+		latched_cycle_cnt =
+		    *(u_long*)(MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR));
 		hardclock(&cf);
 		intrcnt[HARDCLOCK]++;
 		/* keep clock interrupts enabled when we return */
@@ -591,6 +597,7 @@ xine_intr(mask, pc, statusReg, causeReg)
 	return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
 		MIPS_SR_INT_ENA_CUR);
 }
+#endif /* DS5000_25 */
 
 #ifdef DS5000_240
 /*