Post-1.1.1pre2 patches from me and Richard Earnshaw. Fixes problems with
allocation of the r10 register, and some cases where code would fail to compile.
This commit is contained in:
mycroft
parent
facb3de742
commit
500c26b496
58
gnu/dist/gcc/config/arm/arm.c
vendored
58
gnu/dist/gcc/config/arm/arm.c
vendored
@ -213,6 +213,16 @@ static struct processors all_procs[] =
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{NULL, 0, 0}
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};
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int
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arm_preserved_register (regno)
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int regno;
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{
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if (flag_pic && regno == PIC_OFFSET_TABLE_REGNUM)
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return 1;
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return ! call_used_regs[regno];
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}
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/* Fix up any incompatible options that the user has specified.
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This has now turned into a maze. */
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void
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@ -376,13 +386,13 @@ use_return_insn ()
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stacked */
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if (TARGET_THUMB_INTERWORK)
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for (regno = 0; regno < 16; regno++)
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if (regs_ever_live[regno] && ! call_used_regs[regno])
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if (regs_ever_live[regno] && arm_preserved_register (regno))
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return 0;
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/* Can't be done if any of the FPU regs are pushed, since this also
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requires an insn */
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for (regno = 16; regno < 24; regno++)
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if (regs_ever_live[regno] && ! call_used_regs[regno])
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if (regs_ever_live[regno] && arm_preserved_register (regno))
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return 0;
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/* If a function is naked, don't use the "return" insn. */
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@ -3585,8 +3595,10 @@ find_barrier (from, max_count)
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while (from && count < max_count)
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{
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rtx tmp;
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if (GET_CODE (from) == BARRIER)
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return from;
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found_barrier = from;
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/* Count the length of this insn */
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if (GET_CODE (from) == INSN
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@ -3594,6 +3606,24 @@ find_barrier (from, max_count)
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&& CONSTANT_P (SET_SRC (PATTERN (from)))
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&& CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
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count += 8;
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/* Handle table jumps as a single entity. */
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else if (GET_CODE (from) == JUMP_INSN
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&& JUMP_LABEL (from) != 0
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&& ((tmp = next_real_insn (JUMP_LABEL (from)))
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== next_real_insn (from))
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&& tmp != NULL
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&& GET_CODE (tmp) == JUMP_INSN
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&& (GET_CODE (PATTERN (tmp)) == ADDR_VEC
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|| GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
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{
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int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
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count += (get_attr_length (from)
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+ GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
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/* Continue after the dispatch table. */
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last = from;
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from = NEXT_INSN (tmp);
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continue;
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}
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else
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count += get_attr_length (from);
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@ -4749,7 +4779,7 @@ output_return_instruction (operand, really_return, reverse)
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abort();
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for (reg = 0; reg <= 10; reg++)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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live_regs++;
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if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
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@ -4771,7 +4801,7 @@ output_return_instruction (operand, really_return, reverse)
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reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
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for (reg = 0; reg <= 10; reg++)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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{
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strcat (instr, "%|");
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strcat (instr, reg_names[reg]);
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@ -4868,7 +4898,7 @@ output_func_prologue (f, frame_size)
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store_arg_regs = 1;
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for (reg = 0; reg <= 10; reg++)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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live_regs_mask |= (1 << reg);
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if (frame_pointer_needed)
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@ -4940,7 +4970,7 @@ output_func_epilogue (f, frame_size)
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}
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for (reg = 0; reg <= 10; reg++)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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{
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live_regs_mask |= (1 << reg);
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floats_offset += 4;
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@ -4951,7 +4981,7 @@ output_func_epilogue (f, frame_size)
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if (arm_fpu_arch == FP_SOFT2)
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{
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for (reg = 23; reg > 15; reg--)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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{
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floats_offset += 12;
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fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
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@ -4964,7 +4994,7 @@ output_func_epilogue (f, frame_size)
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for (reg = 23; reg > 15; reg--)
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{
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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{
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floats_offset += 12;
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/* We can't unstack more than four registers at once */
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@ -5021,7 +5051,7 @@ output_func_epilogue (f, frame_size)
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if (arm_fpu_arch == FP_SOFT2)
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{
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for (reg = 16; reg < 24; reg++)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
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reg_names[reg], REGISTER_PREFIX);
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}
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@ -5031,7 +5061,7 @@ output_func_epilogue (f, frame_size)
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for (reg = 16; reg < 24; reg++)
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{
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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{
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if (reg - start_reg == 3)
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{
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@ -5201,7 +5231,7 @@ arm_expand_prologue ()
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if (! volatile_func)
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for (reg = 0; reg <= 10; reg++)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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live_regs_mask |= 1 << reg;
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if (! volatile_func && regs_ever_live[14])
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@ -5239,7 +5269,7 @@ arm_expand_prologue ()
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if (arm_fpu_arch == FP_SOFT2)
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{
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for (reg = 23; reg > 15; reg--)
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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emit_insn (gen_rtx (SET, VOIDmode,
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gen_rtx (MEM, XFmode,
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gen_rtx (PRE_DEC, XFmode,
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@ -5252,7 +5282,7 @@ arm_expand_prologue ()
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for (reg = 23; reg > 15; reg--)
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{
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if (regs_ever_live[reg] && ! call_used_regs[reg])
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if (regs_ever_live[reg] && arm_preserved_register (reg))
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{
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if (start_reg - reg == 3)
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{
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7
gnu/dist/gcc/config/arm/arm.h
vendored
7
gnu/dist/gcc/config/arm/arm.h
vendored
@ -678,7 +678,7 @@ extern int arm_arch4;
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if (flag_pic) \
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{ \
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fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
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call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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} \
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}
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@ -1182,10 +1182,10 @@ do { \
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if (! volatile_func) \
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{ \
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for (regno = 0; regno <= 10; regno++) \
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if (regs_ever_live[regno] && ! call_used_regs[regno]) \
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if (regs_ever_live[regno] && arm_preserved_register (regno))\
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saved_hard_reg = 1, offset += 4; \
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for (regno = 16; regno <=23; regno++) \
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if (regs_ever_live[regno] && ! call_used_regs[regno]) \
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if (regs_ever_live[regno] && arm_preserved_register (regno))\
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offset += 12; \
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} \
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if ((FROM) == FRAME_POINTER_REGNUM) \
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@ -2013,6 +2013,7 @@ do { \
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/* Prototypes for arm.c -- actually, they aren't since the types aren't
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fully defined yet. */
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int arm_preserved_register (/* int */);
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void arm_override_options (/* void */);
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int use_return_insn (/* void */);
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int const_ok_for_arm (/* HOST_WIDE_INT */);
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124
gnu/dist/gcc/config/arm/arm.md
vendored
124
gnu/dist/gcc/config/arm/arm.md
vendored
@ -1856,7 +1856,7 @@
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(define_insn "abssi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
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(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"@
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cmp\\t%0, #0\;rsblt\\t%0, %0, #0
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@ -1867,7 +1867,7 @@
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(define_insn "*neg_abssi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
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(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"@
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cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
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@ -4635,7 +4635,7 @@
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(match_operator 1 "comparison_operator"
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[(match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 3 "arm_add_operand" "rI,L")]))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"*
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if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx)
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@ -4693,7 +4693,7 @@
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[(match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
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(match_operand:SI 1 "s_register_operand" "0,?r")]))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"*
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if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
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@ -4717,7 +4717,7 @@
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(match_operator:SI 4 "comparison_operator"
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[(match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"*
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output_asm_insn (\"cmp\\t%2, %3\", operands);
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@ -4798,7 +4798,7 @@
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(neg:SI (match_operator 3 "comparison_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rI")])))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"*
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if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx)
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@ -4825,7 +4825,7 @@
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(match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
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(match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
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(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"*
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if (GET_CODE (operands[5]) == LT
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@ -4887,69 +4887,65 @@
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(plus:SI
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(match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
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(match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")))
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(clobber (reg 24))]
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(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
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(clobber (reg:CC 24))]
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""
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"#"
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[(set_attr "conds" "clob")
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(set_attr "length" "8,12")])
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(define_insn "*if_plus_move"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r")
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
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(if_then_else:SI
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(match_operator 4 "comparison_operator"
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[(match_operand 5 "cc_register" "") (const_int 0)])
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(plus:SI
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(match_operand:SI 2 "s_register_operand" "r,r,r,r,r,r")
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(match_operand:SI 3 "arm_add_operand" "rI,L,rI,L,rI,L"))
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(match_operand:SI 1 "arm_rhsm_operand" "0,0,?rI,?rI,m,m")))]
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(match_operand:SI 2 "s_register_operand" "r,r,r,r")
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(match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))
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(match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))]
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""
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"@
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add%d4\\t%0, %2, %3
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sub%d4\\t%0, %2, #%n3
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add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
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sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1
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add%d4\\t%0, %2, %3\;ldr%D4\\t%0, %1
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sub%d4\\t%0, %2, #%n3\;ldr%D4\\t%0, %1"
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sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1"
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[(set_attr "conds" "use")
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(set_attr "length" "4,4,8,8,8,8")
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(set_attr "type" "*,*,*,*,load,load")])
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(set_attr "length" "4,4,8,8")
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(set_attr "type" "*,*,*,*")])
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(define_insn "*ifcompare_move_plus"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(if_then_else:SI (match_operator 6 "comparison_operator"
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[(match_operand:SI 4 "s_register_operand" "r,r")
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(match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
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(match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")
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(match_operand:SI 1 "arm_rhs_operand" "0,?rI")
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(plus:SI
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(match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"#"
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[(set_attr "conds" "clob")
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(set_attr "length" "8,12")])
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(define_insn "*if_move_plus"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r")
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
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(if_then_else:SI
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(match_operator 4 "comparison_operator"
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[(match_operand 5 "cc_register" "") (const_int 0)])
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(match_operand:SI 1 "arm_rhsm_operand" "0,0,?rI,?rI,m,m")
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(match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")
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(plus:SI
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(match_operand:SI 2 "s_register_operand" "r,r,r,r,r,r")
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(match_operand:SI 3 "arm_add_operand" "rI,L,rI,L,rI,L"))))]
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(match_operand:SI 2 "s_register_operand" "r,r,r,r")
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(match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))]
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""
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"@
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add%D4\\t%0, %2, %3
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sub%D4\\t%0, %2, #%n3
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add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
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sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1
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add%D4\\t%0, %2, %3\;ldr%d4\\t%0, %1
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sub%D4\\t%0, %2, #%n3\;ldr%d4\\t%0, %1"
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sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
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[(set_attr "conds" "use")
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(set_attr "length" "4,4,8,8,8,8")
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(set_attr "type" "*,*,*,*,load,load")])
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(set_attr "length" "4,4,8,8")
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(set_attr "type" "*,*,*,*")])
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(define_insn "*ifcompare_arith_arith"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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@ -4962,7 +4958,7 @@
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(match_operator:SI 7 "shiftable_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "arm_rhs_operand" "rI")])))
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(clobber (reg 24))]
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(clobber (reg:CC 24))]
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""
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"#"
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[(set_attr "conds" "clob")
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@ -4991,8 +4987,8 @@
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(match_operator:SI 7 "shiftable_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r,r")
|
||||
(match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
|
||||
(match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")))
|
||||
(clobber (reg 24))]
|
||||
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"*
|
||||
/* If we have an operation where (op x 0) is the identity operation and
|
||||
@ -5017,44 +5013,38 @@
|
||||
output_asm_insn (\"cmp\\t%2, %3\", operands);
|
||||
output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands);
|
||||
if (which_alternative != 0)
|
||||
{
|
||||
if (GET_CODE (operands[1]) == MEM)
|
||||
return \"ldr%D6\\t%0, %1\";
|
||||
else
|
||||
return \"mov%D6\\t%0, %1\";
|
||||
}
|
||||
return \"mov%D6\\t%0, %1\";
|
||||
return \"\";
|
||||
"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "8,12")])
|
||||
|
||||
(define_insn "*if_arith_move"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
(if_then_else:SI (match_operator 4 "comparison_operator"
|
||||
[(match_operand 6 "cc_register" "") (const_int 0)])
|
||||
(match_operator:SI 5 "shiftable_operator"
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI")])
|
||||
(match_operand:SI 1 "arm_rhsm_operand" "0,?rI,m")))]
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
|
||||
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")))]
|
||||
""
|
||||
"@
|
||||
%I5%d4\\t%0, %2, %3
|
||||
%I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
|
||||
%I5%d4\\t%0, %2, %3\;ldr%D4\\t%0, %1"
|
||||
%I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "4,8,8")
|
||||
(set_attr "type" "*,*,load")])
|
||||
(set_attr "length" "4,8")
|
||||
(set_attr "type" "*,*")])
|
||||
|
||||
(define_insn "*ifcompare_move_arith"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
(if_then_else:SI (match_operator 6 "comparison_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r,r")
|
||||
(match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
|
||||
(match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")
|
||||
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")
|
||||
(match_operator:SI 7 "shiftable_operator"
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"*
|
||||
/* If we have an operation where (op x 0) is the identity operation and
|
||||
@ -5080,34 +5070,28 @@
|
||||
output_asm_insn (\"cmp\\t%4, %5\", operands);
|
||||
|
||||
if (which_alternative != 0)
|
||||
{
|
||||
if (GET_CODE (operands[1]) == MEM)
|
||||
output_asm_insn (\"ldr%d6\\t%0, %1\", operands);
|
||||
else
|
||||
output_asm_insn (\"mov%d6\\t%0, %1\", operands);
|
||||
}
|
||||
output_asm_insn (\"mov%d6\\t%0, %1\", operands);
|
||||
return \"%I7%D6\\t%0, %2, %3\";
|
||||
"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "8,12")])
|
||||
|
||||
(define_insn "*if_move_arith"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
(if_then_else:SI
|
||||
(match_operator 4 "comparison_operator"
|
||||
[(match_operand 6 "cc_register" "") (const_int 0)])
|
||||
(match_operand:SI 1 "arm_rhsm_operand" "0,?rI,m")
|
||||
(match_operand:SI 1 "arm_rhs_operand" "0,?rI")
|
||||
(match_operator:SI 5 "shiftable_operator"
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI")])))]
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))]
|
||||
""
|
||||
"@
|
||||
%I5%D4\\t%0, %2, %3
|
||||
%I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
|
||||
%I5%D4\\t%0, %2, %3\;ldr%d4\\t%0, %1"
|
||||
%I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "4,8,8")
|
||||
(set_attr "type" "*,*,load")])
|
||||
(set_attr "length" "4,8")
|
||||
(set_attr "type" "*,*")])
|
||||
|
||||
(define_insn "*ifcompare_move_not"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
@ -5118,7 +5102,7 @@
|
||||
(match_operand:SI 1 "arm_not_operand" "0,?rIK")
|
||||
(not:SI
|
||||
(match_operand:SI 2 "s_register_operand" "r,r"))))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -5148,7 +5132,7 @@
|
||||
(not:SI
|
||||
(match_operand:SI 2 "s_register_operand" "r,r"))
|
||||
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -5179,7 +5163,7 @@
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
|
||||
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -5212,7 +5196,7 @@
|
||||
(match_operator:SI 7 "shift_operator"
|
||||
[(match_operand:SI 2 "s_register_operand" "r,r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -5247,7 +5231,7 @@
|
||||
(match_operator:SI 9 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "arm_rhs_operand" "rM")])))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -5279,7 +5263,7 @@
|
||||
(match_operator:SI 7 "shiftable_operator"
|
||||
[(match_operand:SI 2 "s_register_operand" "r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI")])))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -5309,7 +5293,7 @@
|
||||
[(match_operand:SI 2 "s_register_operand" "r")
|
||||
(match_operand:SI 3 "arm_rhs_operand" "rI")])
|
||||
(not:SI (match_operand:SI 1 "s_register_operand" "r"))))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "conds" "clob")
|
||||
@ -6102,7 +6086,7 @@
|
||||
[(match_operand 2 "" "") (match_operand 3 "" "")])
|
||||
(match_operand 4 "" "")
|
||||
(match_operand 5 "" "")))
|
||||
(clobber (reg 24))]
|
||||
(clobber (reg:CC 24))]
|
||||
"reload_completed"
|
||||
[(set (match_dup 6) (match_dup 7))
|
||||
(set (match_dup 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user