From 500c26b496b0cbb38b2f73ac52a84e6a69027f56 Mon Sep 17 00:00:00 2001 From: mycroft Date: Sat, 21 Nov 1998 22:09:32 +0000 Subject: [PATCH] Post-1.1.1pre2 patches from me and Richard Earnshaw. Fixes problems with allocation of the r10 register, and some cases where code would fail to compile. --- gnu/dist/gcc/config/arm/arm.c | 58 +++++++++++---- gnu/dist/gcc/config/arm/arm.h | 7 +- gnu/dist/gcc/config/arm/arm.md | 124 ++++++++++++++------------------- 3 files changed, 102 insertions(+), 87 deletions(-) diff --git a/gnu/dist/gcc/config/arm/arm.c b/gnu/dist/gcc/config/arm/arm.c index a418d03c5d75..1f8a21875404 100644 --- a/gnu/dist/gcc/config/arm/arm.c +++ b/gnu/dist/gcc/config/arm/arm.c @@ -213,6 +213,16 @@ static struct processors all_procs[] = {NULL, 0, 0} }; +int +arm_preserved_register (regno) + int regno; +{ + if (flag_pic && regno == PIC_OFFSET_TABLE_REGNUM) + return 1; + + return ! call_used_regs[regno]; +} + /* Fix up any incompatible options that the user has specified. This has now turned into a maze. */ void @@ -376,13 +386,13 @@ use_return_insn () stacked */ if (TARGET_THUMB_INTERWORK) for (regno = 0; regno < 16; regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) + if (regs_ever_live[regno] && arm_preserved_register (regno)) return 0; /* Can't be done if any of the FPU regs are pushed, since this also requires an insn */ for (regno = 16; regno < 24; regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) + if (regs_ever_live[regno] && arm_preserved_register (regno)) return 0; /* If a function is naked, don't use the "return" insn. */ @@ -3585,8 +3595,10 @@ find_barrier (from, max_count) while (from && count < max_count) { + rtx tmp; + if (GET_CODE (from) == BARRIER) - return from; + found_barrier = from; /* Count the length of this insn */ if (GET_CODE (from) == INSN @@ -3594,6 +3606,24 @@ find_barrier (from, max_count) && CONSTANT_P (SET_SRC (PATTERN (from))) && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from)))) count += 8; + /* Handle table jumps as a single entity. */ + else if (GET_CODE (from) == JUMP_INSN + && JUMP_LABEL (from) != 0 + && ((tmp = next_real_insn (JUMP_LABEL (from))) + == next_real_insn (from)) + && tmp != NULL + && GET_CODE (tmp) == JUMP_INSN + && (GET_CODE (PATTERN (tmp)) == ADDR_VEC + || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)) + { + int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0; + count += (get_attr_length (from) + + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt)); + /* Continue after the dispatch table. */ + last = from; + from = NEXT_INSN (tmp); + continue; + } else count += get_attr_length (from); @@ -4749,7 +4779,7 @@ output_return_instruction (operand, really_return, reverse) abort(); for (reg = 0; reg <= 10; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) live_regs++; if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated)) @@ -4771,7 +4801,7 @@ output_return_instruction (operand, really_return, reverse) reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {"); for (reg = 0; reg <= 10; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) { strcat (instr, "%|"); strcat (instr, reg_names[reg]); @@ -4868,7 +4898,7 @@ output_func_prologue (f, frame_size) store_arg_regs = 1; for (reg = 0; reg <= 10; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) live_regs_mask |= (1 << reg); if (frame_pointer_needed) @@ -4940,7 +4970,7 @@ output_func_epilogue (f, frame_size) } for (reg = 0; reg <= 10; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) { live_regs_mask |= (1 << reg); floats_offset += 4; @@ -4951,7 +4981,7 @@ output_func_epilogue (f, frame_size) if (arm_fpu_arch == FP_SOFT2) { for (reg = 23; reg > 15; reg--) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) { floats_offset += 12; fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX, @@ -4964,7 +4994,7 @@ output_func_epilogue (f, frame_size) for (reg = 23; reg > 15; reg--) { - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) { floats_offset += 12; /* We can't unstack more than four registers at once */ @@ -5021,7 +5051,7 @@ output_func_epilogue (f, frame_size) if (arm_fpu_arch == FP_SOFT2) { for (reg = 16; reg < 24; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX, reg_names[reg], REGISTER_PREFIX); } @@ -5031,7 +5061,7 @@ output_func_epilogue (f, frame_size) for (reg = 16; reg < 24; reg++) { - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) { if (reg - start_reg == 3) { @@ -5201,7 +5231,7 @@ arm_expand_prologue () if (! volatile_func) for (reg = 0; reg <= 10; reg++) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) live_regs_mask |= 1 << reg; if (! volatile_func && regs_ever_live[14]) @@ -5239,7 +5269,7 @@ arm_expand_prologue () if (arm_fpu_arch == FP_SOFT2) { for (reg = 23; reg > 15; reg--) - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (MEM, XFmode, gen_rtx (PRE_DEC, XFmode, @@ -5252,7 +5282,7 @@ arm_expand_prologue () for (reg = 23; reg > 15; reg--) { - if (regs_ever_live[reg] && ! call_used_regs[reg]) + if (regs_ever_live[reg] && arm_preserved_register (reg)) { if (start_reg - reg == 3) { diff --git a/gnu/dist/gcc/config/arm/arm.h b/gnu/dist/gcc/config/arm/arm.h index ed5e4de97290..44e5d0877a2a 100644 --- a/gnu/dist/gcc/config/arm/arm.h +++ b/gnu/dist/gcc/config/arm/arm.h @@ -678,7 +678,7 @@ extern int arm_arch4; if (flag_pic) \ { \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \ + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } \ } @@ -1182,10 +1182,10 @@ do { \ if (! volatile_func) \ { \ for (regno = 0; regno <= 10; regno++) \ - if (regs_ever_live[regno] && ! call_used_regs[regno]) \ + if (regs_ever_live[regno] && arm_preserved_register (regno))\ saved_hard_reg = 1, offset += 4; \ for (regno = 16; regno <=23; regno++) \ - if (regs_ever_live[regno] && ! call_used_regs[regno]) \ + if (regs_ever_live[regno] && arm_preserved_register (regno))\ offset += 12; \ } \ if ((FROM) == FRAME_POINTER_REGNUM) \ @@ -2013,6 +2013,7 @@ do { \ /* Prototypes for arm.c -- actually, they aren't since the types aren't fully defined yet. */ +int arm_preserved_register (/* int */); void arm_override_options (/* void */); int use_return_insn (/* void */); int const_ok_for_arm (/* HOST_WIDE_INT */); diff --git a/gnu/dist/gcc/config/arm/arm.md b/gnu/dist/gcc/config/arm/arm.md index 18093c784e7e..31c120fd86fa 100644 --- a/gnu/dist/gcc/config/arm/arm.md +++ b/gnu/dist/gcc/config/arm/arm.md @@ -1856,7 +1856,7 @@ (define_insn "abssi2" [(set (match_operand:SI 0 "s_register_operand" "=r,&r") (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "@ cmp\\t%0, #0\;rsblt\\t%0, %0, #0 @@ -1867,7 +1867,7 @@ (define_insn "*neg_abssi2" [(set (match_operand:SI 0 "s_register_operand" "=r,&r") (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "@ cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 @@ -4635,7 +4635,7 @@ (match_operator 1 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rI,L")])) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "* if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx) @@ -4693,7 +4693,7 @@ [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "* if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) @@ -4717,7 +4717,7 @@ (match_operator:SI 4 "comparison_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "* output_asm_insn (\"cmp\\t%2, %3\", operands); @@ -4798,7 +4798,7 @@ (neg:SI (match_operator 3 "comparison_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "* if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx) @@ -4825,7 +4825,7 @@ (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")]) (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "* if (GET_CODE (operands[5]) == LT @@ -4887,69 +4887,65 @@ (plus:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rIL,rIL")) - (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm"))) - (clobber (reg 24))] + (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") (set_attr "length" "8,12")]) (define_insn "*if_plus_move" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") (if_then_else:SI (match_operator 4 "comparison_operator" [(match_operand 5 "cc_register" "") (const_int 0)]) (plus:SI - (match_operand:SI 2 "s_register_operand" "r,r,r,r,r,r") - (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L,rI,L")) - (match_operand:SI 1 "arm_rhsm_operand" "0,0,?rI,?rI,m,m")))] + (match_operand:SI 2 "s_register_operand" "r,r,r,r") + (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L")) + (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))] "" "@ add%d4\\t%0, %2, %3 sub%d4\\t%0, %2, #%n3 add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1 - sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1 - add%d4\\t%0, %2, %3\;ldr%D4\\t%0, %1 - sub%d4\\t%0, %2, #%n3\;ldr%D4\\t%0, %1" + sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1" [(set_attr "conds" "use") - (set_attr "length" "4,4,8,8,8,8") - (set_attr "type" "*,*,*,*,load,load")]) + (set_attr "length" "4,4,8,8") + (set_attr "type" "*,*,*,*")]) (define_insn "*ifcompare_move_plus" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) - (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm") + (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (plus:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_add_operand" "rIL,rIL")))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") (set_attr "length" "8,12")]) (define_insn "*if_move_plus" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") (if_then_else:SI (match_operator 4 "comparison_operator" [(match_operand 5 "cc_register" "") (const_int 0)]) - (match_operand:SI 1 "arm_rhsm_operand" "0,0,?rI,?rI,m,m") + (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI") (plus:SI - (match_operand:SI 2 "s_register_operand" "r,r,r,r,r,r") - (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L,rI,L"))))] + (match_operand:SI 2 "s_register_operand" "r,r,r,r") + (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))] "" "@ add%D4\\t%0, %2, %3 sub%D4\\t%0, %2, #%n3 add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1 - sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1 - add%D4\\t%0, %2, %3\;ldr%d4\\t%0, %1 - sub%D4\\t%0, %2, #%n3\;ldr%d4\\t%0, %1" + sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" [(set_attr "conds" "use") - (set_attr "length" "4,4,8,8,8,8") - (set_attr "type" "*,*,*,*,load,load")]) + (set_attr "length" "4,4,8,8") + (set_attr "type" "*,*,*,*")]) (define_insn "*ifcompare_arith_arith" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -4962,7 +4958,7 @@ (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_rhs_operand" "rI")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -4991,8 +4987,8 @@ (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_rhs_operand" "rI,rI")]) - (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm"))) - (clobber (reg 24))] + (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) + (clobber (reg:CC 24))] "" "* /* If we have an operation where (op x 0) is the identity operation and @@ -5017,44 +5013,38 @@ output_asm_insn (\"cmp\\t%2, %3\", operands); output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands); if (which_alternative != 0) - { - if (GET_CODE (operands[1]) == MEM) - return \"ldr%D6\\t%0, %1\"; - else - return \"mov%D6\\t%0, %1\"; - } + return \"mov%D6\\t%0, %1\"; return \"\"; " [(set_attr "conds" "clob") (set_attr "length" "8,12")]) (define_insn "*if_arith_move" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 4 "comparison_operator" [(match_operand 6 "cc_register" "") (const_int 0)]) (match_operator:SI 5 "shiftable_operator" - [(match_operand:SI 2 "s_register_operand" "r,r,r") - (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI")]) - (match_operand:SI 1 "arm_rhsm_operand" "0,?rI,m")))] + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) + (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))] "" "@ %I5%d4\\t%0, %2, %3 - %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1 - %I5%d4\\t%0, %2, %3\;ldr%D4\\t%0, %1" + %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1" [(set_attr "conds" "use") - (set_attr "length" "4,8,8") - (set_attr "type" "*,*,load")]) + (set_attr "length" "4,8") + (set_attr "type" "*,*")]) (define_insn "*ifcompare_move_arith" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "comparison_operator" [(match_operand:SI 4 "s_register_operand" "r,r") (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) - (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm") + (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "* /* If we have an operation where (op x 0) is the identity operation and @@ -5080,34 +5070,28 @@ output_asm_insn (\"cmp\\t%4, %5\", operands); if (which_alternative != 0) - { - if (GET_CODE (operands[1]) == MEM) - output_asm_insn (\"ldr%d6\\t%0, %1\", operands); - else - output_asm_insn (\"mov%d6\\t%0, %1\", operands); - } + output_asm_insn (\"mov%d6\\t%0, %1\", operands); return \"%I7%D6\\t%0, %2, %3\"; " [(set_attr "conds" "clob") (set_attr "length" "8,12")]) (define_insn "*if_move_arith" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 4 "comparison_operator" [(match_operand 6 "cc_register" "") (const_int 0)]) - (match_operand:SI 1 "arm_rhsm_operand" "0,?rI,m") + (match_operand:SI 1 "arm_rhs_operand" "0,?rI") (match_operator:SI 5 "shiftable_operator" - [(match_operand:SI 2 "s_register_operand" "r,r,r") - (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI")])))] + [(match_operand:SI 2 "s_register_operand" "r,r") + (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))] "" "@ %I5%D4\\t%0, %2, %3 - %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1 - %I5%D4\\t%0, %2, %3\;ldr%d4\\t%0, %1" + %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1" [(set_attr "conds" "use") - (set_attr "length" "4,8,8") - (set_attr "type" "*,*,load")]) + (set_attr "length" "4,8") + (set_attr "type" "*,*")]) (define_insn "*ifcompare_move_not" [(set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -5118,7 +5102,7 @@ (match_operand:SI 1 "arm_not_operand" "0,?rIK") (not:SI (match_operand:SI 2 "s_register_operand" "r,r")))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -5148,7 +5132,7 @@ (not:SI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -5179,7 +5163,7 @@ [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rM,rM")]) (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -5212,7 +5196,7 @@ (match_operator:SI 7 "shift_operator" [(match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 3 "arm_rhs_operand" "rM,rM")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -5247,7 +5231,7 @@ (match_operator:SI 9 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "arm_rhs_operand" "rM")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -5279,7 +5263,7 @@ (match_operator:SI 7 "shiftable_operator" [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rI")]))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -5309,7 +5293,7 @@ [(match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 3 "arm_rhs_operand" "rI")]) (not:SI (match_operand:SI 1 "s_register_operand" "r")))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "" "#" [(set_attr "conds" "clob") @@ -6102,7 +6086,7 @@ [(match_operand 2 "" "") (match_operand 3 "" "")]) (match_operand 4 "" "") (match_operand 5 "" ""))) - (clobber (reg 24))] + (clobber (reg:CC 24))] "reload_completed" [(set (match_dup 6) (match_dup 7)) (set (match_dup 0)