ep93xx processor on-chip UART driver
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/* $NetBSD: epcomreg.h,v 1.1 2004/12/22 19:10:25 joff Exp $ */
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/*
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* Copyright (c) 2004 Jesse Off
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
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* HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EPCOMREG_H_
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#define _EPCOMREG_H_
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#define EPCOM_FREQ 7372800
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#define EPCOMSPEED2BRD(b) ((EPCOM_FREQ / (16 * (b))) - 1)
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/* UART Data Register */
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#define EPCOM_Data 0x00000000UL
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/* UART Receive Status/Error Clear Register */
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#define EPCOM_RXSts 0x00000004UL
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#define RXSts_FE 0x01
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#define RXSts_PE 0x02
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#define RXSts_BE 0x04
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#define RXSts_OE 0x08
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/* UART Line Control Register High */
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#define EPCOM_LinCtrlHigh 0x00000008UL
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#define LinCtrlHigh_BRK 0x01
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#define LinCtrlHigh_PEN 0x02
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#define LinCtrlHigh_EPS 0x04
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#define LinCtrlHigh_STP2 0x08
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#define LinCtrlHigh_FEN 0x10
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#define LinCtrlHigh_WLEN 0x60
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/* UART Line Control Register Middle */
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#define EPCOM_LinCtrlMid 0x0000000cUL
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/* UART Line Control Register Low */
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#define EPCOM_LinCtrlLow 0x00000010UL
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/* UART control register */
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#define EPCOM_Ctrl 0x00000014UL
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#define Ctrl_UARTE 0x01 /* UART Enable */
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#define Ctrl_MSIE 0x08 /* Modem Status Interrupt Enable */
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#define Ctrl_RIE 0x10 /* Receive Interrupt Enable */
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#define Ctrl_TIE 0x20 /* Transmit Interrupt Enable */
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#define Ctrl_RTIE 0x40 /* Receive Timeout Enable */
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#define Ctrl_LBE 0x80 /* Loopback Enable */
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/* UART Flag register */
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#define EPCOM_Flag 0x00000018UL
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#define Flag_CTS 0x01 /* Clear To Send status */
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#define Flag_DSR 0x02 /* Data Set Ready status */
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#define Flag_DCD 0x04 /* Data Carrier Detect status */
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#define Flag_BUSY 0x08 /* UART Busy */
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#define Flag_RXFE 0x10 /* Receive FIFO Empty */
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#define Flag_TXFF 0x20 /* Transmit FIFO Full */
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#define Flag_RXFF 0x40 /* Receive FIFO Full */
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#define Flag_TXFE 0x80 /* Transmit FIFO Empty */
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/* UART Interrupt Identification and Interrupt Clear Register */
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#define EPCOM_IntIDIntClr 0x0000001cUL
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#define IntIDIntClr_MIS 0x01 /* Modem Interrupt Status */
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#define IntIDIntClr_RIS 0x01 /* Receive Interrupt Status */
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#define IntIDIntClr_TIS 0x01 /* Transmit Interrupt Status */
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#define IntIDIntClr_RTIS 0x01 /* Receive Timeout Interrupt Status */
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/* UART Modem Control Register */
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#define EPCOM_ModemCtrl 0x00000100UL
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#define ModemCtrl_DTR 0x01 /* DTR output signal */
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#define ModemCtrl_RTS 0x02 /* RTS output signal */
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/* UART Modem Status Register */
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#define EPCOM_ModemSts 0x00000104UL
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#define ModemSts_DCTS 0x01 /* Delta CTS */
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#define ModemSts_DDSR 0x02 /* Delta DSR */
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#define ModemSts_TERI 0x04 /* Trailing Edge Ring Indicator */
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#define ModemSts_DDCD 0x08 /* Delta DCD */
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#define ModemSts_CTS 0x10 /* Inverse CTSn input pin */
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#define ModemSts_DSR 0x20 /* Inverse of the DSRn pin */
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#define ModemSts_RI 0x40 /* Inverse of RI input pin */
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#define ModemSts_DCD 0x80 /* Inverse of DCDn input pin */
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#endif /* _EPCOMREG_H_ */
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/* $NetBSD: epcomvar.h,v 1.1 2004/12/22 19:10:25 joff Exp $ */
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/*-
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* Copyright (c) 2004 Jesse Off
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _EPCOMVAR_H_
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#define _EPCOMVAR_H_
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/* Hardware flag masks */
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#define COM_HW_NOIEN 0x01
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#define COM_HW_DEV_OK 0x20
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#define COM_HW_CONSOLE 0x40
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#define COM_HW_KGDB 0x80
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#define RX_TTY_BLOCKED 0x01
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#define RX_TTY_OVERFLOWED 0x02
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#define RX_IBUF_BLOCKED 0x04
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#define RX_IBUF_OVERFLOWED 0x08
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#define RX_ANY_BLOCK 0x0f
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#define EPCOM_RING_SIZE 2048
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struct epcom_softc {
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struct device sc_dev;
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bus_addr_t sc_hwbase;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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void *sc_si;
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struct tty *sc_tty;
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u_char *sc_rbuf, *sc_ebuf;
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u_char *sc_tba;
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u_int sc_tbc, sc_heldtbc;
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u_char *volatile sc_rbget,
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*volatile sc_rbput;
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volatile u_int sc_rbavail;
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/* status flags */
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int sc_hwflags, sc_swflags;
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volatile u_int sc_rx_flags,
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sc_tx_busy,
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sc_tx_done,
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sc_tx_stopped,
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sc_st_check,
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sc_rx_ready;
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volatile int sc_heldchange;
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/* control registers */
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u_int sc_lcrlo;
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u_int sc_lcrmid;
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u_int sc_lcrhi;
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u_int sc_ctrl;
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/* power management hooks */
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int (*enable)(struct epcom_softc *);
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int (*disable)(struct epcom_softc *);
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int enabled;
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#if NRND > 0 && defined(RND_COM)
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rndsource_element_t rnd_source;
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#endif
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};
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void epcom_attach_subr(struct epcom_softc *);
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int epcomintr(void* arg);
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int epcomcnattach(bus_space_tag_t, bus_addr_t, bus_space_handle_t,
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int, tcflag_t);
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#endif /* _EPCOMVAR_H_ */
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