Add definitions for several more registers on the AMD Elan SC520
System Controller.
This commit is contained in:
dyoung
parent
14002ac9c8
commit
396e67c2e6
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@ -1,4 +1,4 @@
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/* $NetBSD: elan520reg.h,v 1.7 2007/10/17 19:54:58 garbled Exp $ */
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/* $NetBSD: elan520reg.h,v 1.8 2007/12/20 20:44:58 dyoung Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -43,6 +43,8 @@
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#ifndef _I386_PCI_ELAN520REG_H_
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#define _I386_PCI_ELAN520REG_H_
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#include <sys/cdefs.h>
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#define MMCR_BASE_ADDR 0xfffef000
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/*
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@ -90,55 +92,178 @@
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#define MMCR_HBCTL_M_WPOST_ENB __BIT(3)
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#define MMCR_SYSARBCTL 0x0070 /* System Arbiter Control */
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#define MMCR_SYSARBCTL_CNCR_MODE_ENB __BIT(1)
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#define MMCR_SYSARBCTL_GNT_TO_INT_ENB __BIT(0) /* 1: interrupt when the
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* PCI bus arbiter
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* detects a time-out
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*/
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#define MMCR_PCIARBSTA 0x71 /* PCI Bus Arbiter Status */
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#define MMCR_PCIARBSTA_GNT_TO_STA __BIT(7)
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#define MMCR_PCIARBSTA_GNT_TO_ID __BITS(3, 0)
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/*
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* PCI Host Bridge Registers
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*/
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#define MMCR_HBMSTIRQCTL 0x66 /* Host Bridge Master Interrupt Ctrl */
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#define MMCR_M_RTRTO_IRQ_SEL __BIT(13) /* Master Retry Time-Out
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* Interrupt Select
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*/
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#define MMCR_M_TABRT_IRQ_SEL __BIT(12) /* Master Target Abort
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* Interrupt Select
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*/
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#define MMCR_M_MABRT_IRQ_SEL __BIT(11) /* Master Abort
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* Interrupt Select
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*/
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#define MMCR_M_SERR_IRQ_SEL __BIT(10) /* Master System Error
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* Interrupt Select
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*/
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#define MMCR_M_RPER_IRQ_SEL __BIT(9) /* Master Received PERR
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* Interrupt Select
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*/
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#define MMCR_M_DPER_IRQ_SEL __BIT(8) /* Master Detected PERR
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* Interrupt Select
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*/
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#define MMCR_M_RTRTO_IRQ_ENB __BIT(5) /* Master Retry Time-Out
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* Interrupt Enable
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*/
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#define MMCR_M_TABRT_IRQ_ENB __BIT(4) /* Master Target Abort
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* Interrupt Enable
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*/
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#define MMCR_M_MABRT_IRQ_ENB __BIT(3) /* Master Abort
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* Interrupt Enable
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*/
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#define MMCR_M_SERR_IRQ_ENB __BIT(2) /* Master System Error
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* Interrupt Enable
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*/
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#define MMCR_M_RPER_IRQ_ENB __BIT(1) /* Master Received PERR
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* Interrupt Enable
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*/
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#define MMCR_M_DPER_IRQ_ENB __BIT(0) /* Master Detected PERR
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* Interrupt Enable
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*/
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#define MMCR_HBTGTIRQCTL 0x62 /* Host Bridge Target Interrupt Ctrl */
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#define MMCR_HBMSTIRQCTL_RSVD0 __BITS(15, 14)
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/* Interrupt Selects
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*
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* 0: generate maskable interrupt (see MMCR_PCIHOSTMAP)
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* 1: generate NMI
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*/
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/* Master Retry Time-Out */
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#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL __BIT(13)
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/* Master Target Abort */
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#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL __BIT(12)
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/* Master Abort */
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#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL __BIT(11)
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/* Master System Error */
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#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL __BIT(10)
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/* Master Received PERR */
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#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL __BIT(9)
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/* Master Detected PERR */
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#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL __BIT(8)
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#define MMCR_HBMSTIRQCTL_RSVD1 __BITS(7, 6)
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/* Interrupt Enables */
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/* Master Retry Time-Out */
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#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB __BIT(5)
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/* Master Target Abort */
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#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB __BIT(4)
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/* Master Abort */
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#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB __BIT(3)
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/* Master System Error */
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#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB __BIT(2)
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/* Master Received PERR */
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#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB __BIT(1)
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/* Master Detected PERR */
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#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB __BIT(0)
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/* Host Bridge Target Interrupt Ctrl. 16 bits. */
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#define MMCR_HBTGTIRQCTL 0x62
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#define MMCR_HBTGTIRQCTL_RSVD0 __BITS(15, 11)
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/* Interrupt Selects
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*
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* 0: generate maskable interrupt (see MMCR_PCIHOSTMAP)
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* 1: generate NMI
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*/
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#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL __BIT(10)
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#define MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL __BIT(9)
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#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL __BIT(8)
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#define MMCR_HBTGTIRQCTL_RSVD1 __BITS(7, 3)
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/* Interrupt Enables */
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/* Target Delayed Transaction Time-out */
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#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB __BIT(2)
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/* Target Address Parity */
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#define MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB __BIT(1)
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/* Target Data Parity */
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#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB __BIT(0)
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/* Host Bridge Master Interrupt Status. 16 bits. */
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#define MMCR_HBMSTIRQSTA 0x68
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/* Host Bridge Master Interrupt Address */
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#define MMCR_MSTINTADD 0x6c
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#define MMCR_HBMSTIRQSTA_RSVD0 __BITS(15, 12)
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#define MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID __BITS(11, 8)
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#define MMCR_HBMSTIRQSTA_RSVD1 __BITS(7, 6)
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#define MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA __BIT(5)
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#define MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA __BIT(4)
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#define MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA __BIT(3)
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#define MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA __BIT(2)
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#define MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA __BIT(1)
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#define MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA __BIT(0)
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/* The PCI master interrupts that NetBSD is interested in. */
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#define MMCR_MSTIRQ_ACT (MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB)
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/* Host Bridge Target Interrupt Status. 16 bits. */
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#define MMCR_HBTGTIRQSTA 0x64
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#define MMCR_HBTGTIRQSTA_RSVD0 __BITS(15, 12)
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/* Target Interrupt Identification */
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#define MMCR_HBTGTIRQSTA_T_IRQ_ID __BITS(11, 8)
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#define MMCR_HBTGTIRQSTA_RSVD1 __BITS(7, 3)
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/* Status bits. Write 1 to clear. */
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#define MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA __BIT(2)
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#define MMCR_HBTGTIRQSTA_T_APER_IRQ_STA __BIT(1)
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#define MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA __BIT(0)
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/* The PCI target interrupts that NetBSD is interested in. */
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#define MMCR_TGTIRQ_ACT (MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA |\
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MMCR_HBTGTIRQSTA_T_APER_IRQ_STA |\
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MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA)
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#define MMCR_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mapping */
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#define MMCR_PCIHOSTMAP_PCI_NMI_ENB __BIT(8)
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#define MMCR_PCIHOSTMAP_PCI_IRQ_MAP __BITS(4, 0)
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/* Programmable Interrupt Controller. 8 bits. */
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#define MMCR_PICICR 0xd00
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#define MMCR_PICICR_NMI_DONE __BIT(7)
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#define MMCR_PICICR_NMI_ENB __BIT(6)
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#define MMCR_PICICR_RSVD0 __BITS(5, 3)
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#define MMCR_PICICR_S2_GINT_MODE __BIT(2)
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#define MMCR_PICICR_S1_GINT_MODE __BIT(1)
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#define MMCR_PICICR_M_GINT_MODE __BIT(0)
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#define MMCR_MPICMODE 0xd02
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#define MMCR_SL1PICMODE 0xd03
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#define MMCR_SL2PICMODE 0xd04
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#define MMCR_WPVMAP 0xd44
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#define MMCR_WPVMAP_RSVD0 __BITS(7, 5)
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#define MMCR_WPVMAP_INT_MAP __BITS(4, 0)
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#define MMCR_ADDDECCTL 0x80
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#define MMCR_ADDDECCTL_WPV_INT_ENB __BIT(7)
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#define MMCR_WPVSTA 0x82
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#define MMCR_WPVSTA_WPV_STA __BIT(15)
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#define MMCR_WPVSTA_WPV_RSVD0 __BITS(14, 10)
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#define MMCR_WPVSTA_WPV_MSTR __BITS(9, 8)
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#define MMCR_WPVSTA_WPV_MSTR_CPU __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_MSTR_PCI __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_MSTR_GP __SHIFTIN(2, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_MSTR_RSVD __SHIFTIN(3, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_RSVD1 __BITS(7, 4)
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#define MMCR_WPVSTA_WPV_WINDOW __BITS(3, 0)
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#define MMCR_PAR(__i) (0x88 + 4 * (__i))
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#define MMCR_PAR_TARGET __BITS(31, 29)
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#define MMCR_PAR_TARGET_OFF __SHIFTIN(0, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_GPIO __SHIFTIN(1, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_GPMEM __SHIFTIN(2, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_PCI __SHIFTIN(3, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_BOOTCS __SHIFTIN(4, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_ROMCS1 __SHIFTIN(5, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_ROMCS2 __SHIFTIN(6, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_SDRAM __SHIFTIN(7, MMCR_PAR_TARGET)
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#define MMCR_PAR_ATTR __BITS(28, 26)
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#define MMCR_PAR_ATTR_NOEXEC __SHIFTIN(__BIT(2), MMCR_PAR_ATTR)
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#define MMCR_PAR_ATTR_NOCACHE __SHIFTIN(__BIT(1), MMCR_PAR_ATTR)
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#define MMCR_PAR_ATTR_NOWRITE __SHIFTIN(__BIT(0), MMCR_PAR_ATTR)
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#define MMCR_PAR_PG_SZ __BIT(25)
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#define MMCR_PAR_SZ_ST_ADR __BITS(24, 0)
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#define MMCR_PAR_4KB_SZ __BITS(24, 18)
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#define MMCR_PAR_4KB_ST_ADR __BITS(17, 0)
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#define MMCR_PAR_64KB_SZ __BITS(24, 14)
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#define MMCR_PAR_64KB_ST_ADR __BITS(13, 0)
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#define MMCR_PAR_IO_SZ __BITS(24, 16)
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#define MMCR_PAR_IO_ST_ADR __BITS(15, 0)
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/*
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* General Purpose Bus Registers
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*/
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