diff --git a/sys/arch/i386/pci/elan520reg.h b/sys/arch/i386/pci/elan520reg.h index e62051827abb..52a61ececfc9 100644 --- a/sys/arch/i386/pci/elan520reg.h +++ b/sys/arch/i386/pci/elan520reg.h @@ -1,4 +1,4 @@ -/* $NetBSD: elan520reg.h,v 1.7 2007/10/17 19:54:58 garbled Exp $ */ +/* $NetBSD: elan520reg.h,v 1.8 2007/12/20 20:44:58 dyoung Exp $ */ /*- * Copyright (c) 2002 The NetBSD Foundation, Inc. @@ -43,6 +43,8 @@ #ifndef _I386_PCI_ELAN520REG_H_ #define _I386_PCI_ELAN520REG_H_ +#include + #define MMCR_BASE_ADDR 0xfffef000 /* @@ -90,55 +92,178 @@ #define MMCR_HBCTL_M_WPOST_ENB __BIT(3) #define MMCR_SYSARBCTL 0x0070 /* System Arbiter Control */ #define MMCR_SYSARBCTL_CNCR_MODE_ENB __BIT(1) +#define MMCR_SYSARBCTL_GNT_TO_INT_ENB __BIT(0) /* 1: interrupt when the + * PCI bus arbiter + * detects a time-out + */ + +#define MMCR_PCIARBSTA 0x71 /* PCI Bus Arbiter Status */ +#define MMCR_PCIARBSTA_GNT_TO_STA __BIT(7) +#define MMCR_PCIARBSTA_GNT_TO_ID __BITS(3, 0) /* * PCI Host Bridge Registers */ #define MMCR_HBMSTIRQCTL 0x66 /* Host Bridge Master Interrupt Ctrl */ -#define MMCR_M_RTRTO_IRQ_SEL __BIT(13) /* Master Retry Time-Out - * Interrupt Select - */ -#define MMCR_M_TABRT_IRQ_SEL __BIT(12) /* Master Target Abort - * Interrupt Select - */ -#define MMCR_M_MABRT_IRQ_SEL __BIT(11) /* Master Abort - * Interrupt Select - */ -#define MMCR_M_SERR_IRQ_SEL __BIT(10) /* Master System Error - * Interrupt Select - */ -#define MMCR_M_RPER_IRQ_SEL __BIT(9) /* Master Received PERR - * Interrupt Select - */ -#define MMCR_M_DPER_IRQ_SEL __BIT(8) /* Master Detected PERR - * Interrupt Select - */ -#define MMCR_M_RTRTO_IRQ_ENB __BIT(5) /* Master Retry Time-Out - * Interrupt Enable - */ -#define MMCR_M_TABRT_IRQ_ENB __BIT(4) /* Master Target Abort - * Interrupt Enable - */ -#define MMCR_M_MABRT_IRQ_ENB __BIT(3) /* Master Abort - * Interrupt Enable - */ -#define MMCR_M_SERR_IRQ_ENB __BIT(2) /* Master System Error - * Interrupt Enable - */ -#define MMCR_M_RPER_IRQ_ENB __BIT(1) /* Master Received PERR - * Interrupt Enable - */ -#define MMCR_M_DPER_IRQ_ENB __BIT(0) /* Master Detected PERR - * Interrupt Enable - */ -#define MMCR_HBTGTIRQCTL 0x62 /* Host Bridge Target Interrupt Ctrl */ +#define MMCR_HBMSTIRQCTL_RSVD0 __BITS(15, 14) + +/* Interrupt Selects + * + * 0: generate maskable interrupt (see MMCR_PCIHOSTMAP) + * 1: generate NMI + */ +/* Master Retry Time-Out */ +#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL __BIT(13) +/* Master Target Abort */ +#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL __BIT(12) +/* Master Abort */ +#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL __BIT(11) +/* Master System Error */ +#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL __BIT(10) +/* Master Received PERR */ +#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL __BIT(9) +/* Master Detected PERR */ +#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL __BIT(8) +#define MMCR_HBMSTIRQCTL_RSVD1 __BITS(7, 6) + +/* Interrupt Enables */ +/* Master Retry Time-Out */ +#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB __BIT(5) +/* Master Target Abort */ +#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB __BIT(4) +/* Master Abort */ +#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB __BIT(3) +/* Master System Error */ +#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB __BIT(2) +/* Master Received PERR */ +#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB __BIT(1) +/* Master Detected PERR */ +#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB __BIT(0) + +/* Host Bridge Target Interrupt Ctrl. 16 bits. */ +#define MMCR_HBTGTIRQCTL 0x62 + +#define MMCR_HBTGTIRQCTL_RSVD0 __BITS(15, 11) + +/* Interrupt Selects + * + * 0: generate maskable interrupt (see MMCR_PCIHOSTMAP) + * 1: generate NMI + */ +#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL __BIT(10) +#define MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL __BIT(9) +#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL __BIT(8) +#define MMCR_HBTGTIRQCTL_RSVD1 __BITS(7, 3) + +/* Interrupt Enables */ +/* Target Delayed Transaction Time-out */ +#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB __BIT(2) +/* Target Address Parity */ +#define MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB __BIT(1) +/* Target Data Parity */ +#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB __BIT(0) + +/* Host Bridge Master Interrupt Status. 16 bits. */ +#define MMCR_HBMSTIRQSTA 0x68 + +/* Host Bridge Master Interrupt Address */ +#define MMCR_MSTINTADD 0x6c + +#define MMCR_HBMSTIRQSTA_RSVD0 __BITS(15, 12) +#define MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID __BITS(11, 8) +#define MMCR_HBMSTIRQSTA_RSVD1 __BITS(7, 6) +#define MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA __BIT(5) +#define MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA __BIT(4) +#define MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA __BIT(3) +#define MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA __BIT(2) +#define MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA __BIT(1) +#define MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA __BIT(0) + +/* The PCI master interrupts that NetBSD is interested in. */ +#define MMCR_MSTIRQ_ACT (MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB |\ + MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB |\ + MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB |\ + MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB |\ + MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB |\ + MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB) + +/* Host Bridge Target Interrupt Status. 16 bits. */ +#define MMCR_HBTGTIRQSTA 0x64 + +#define MMCR_HBTGTIRQSTA_RSVD0 __BITS(15, 12) +/* Target Interrupt Identification */ +#define MMCR_HBTGTIRQSTA_T_IRQ_ID __BITS(11, 8) +#define MMCR_HBTGTIRQSTA_RSVD1 __BITS(7, 3) +/* Status bits. Write 1 to clear. */ +#define MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA __BIT(2) +#define MMCR_HBTGTIRQSTA_T_APER_IRQ_STA __BIT(1) +#define MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA __BIT(0) + +/* The PCI target interrupts that NetBSD is interested in. */ +#define MMCR_TGTIRQ_ACT (MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA |\ + MMCR_HBTGTIRQSTA_T_APER_IRQ_STA |\ + MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA) #define MMCR_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mapping */ #define MMCR_PCIHOSTMAP_PCI_NMI_ENB __BIT(8) #define MMCR_PCIHOSTMAP_PCI_IRQ_MAP __BITS(4, 0) +/* Programmable Interrupt Controller. 8 bits. */ +#define MMCR_PICICR 0xd00 +#define MMCR_PICICR_NMI_DONE __BIT(7) +#define MMCR_PICICR_NMI_ENB __BIT(6) +#define MMCR_PICICR_RSVD0 __BITS(5, 3) +#define MMCR_PICICR_S2_GINT_MODE __BIT(2) +#define MMCR_PICICR_S1_GINT_MODE __BIT(1) +#define MMCR_PICICR_M_GINT_MODE __BIT(0) + +#define MMCR_MPICMODE 0xd02 +#define MMCR_SL1PICMODE 0xd03 +#define MMCR_SL2PICMODE 0xd04 + +#define MMCR_WPVMAP 0xd44 +#define MMCR_WPVMAP_RSVD0 __BITS(7, 5) +#define MMCR_WPVMAP_INT_MAP __BITS(4, 0) + +#define MMCR_ADDDECCTL 0x80 +#define MMCR_ADDDECCTL_WPV_INT_ENB __BIT(7) + +#define MMCR_WPVSTA 0x82 +#define MMCR_WPVSTA_WPV_STA __BIT(15) +#define MMCR_WPVSTA_WPV_RSVD0 __BITS(14, 10) +#define MMCR_WPVSTA_WPV_MSTR __BITS(9, 8) +#define MMCR_WPVSTA_WPV_MSTR_CPU __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR) +#define MMCR_WPVSTA_WPV_MSTR_PCI __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR) +#define MMCR_WPVSTA_WPV_MSTR_GP __SHIFTIN(2, MMCR_WPVSTA_WPV_MSTR) +#define MMCR_WPVSTA_WPV_MSTR_RSVD __SHIFTIN(3, MMCR_WPVSTA_WPV_MSTR) +#define MMCR_WPVSTA_WPV_RSVD1 __BITS(7, 4) +#define MMCR_WPVSTA_WPV_WINDOW __BITS(3, 0) + +#define MMCR_PAR(__i) (0x88 + 4 * (__i)) +#define MMCR_PAR_TARGET __BITS(31, 29) +#define MMCR_PAR_TARGET_OFF __SHIFTIN(0, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_GPIO __SHIFTIN(1, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_GPMEM __SHIFTIN(2, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_PCI __SHIFTIN(3, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_BOOTCS __SHIFTIN(4, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_ROMCS1 __SHIFTIN(5, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_ROMCS2 __SHIFTIN(6, MMCR_PAR_TARGET) +#define MMCR_PAR_TARGET_SDRAM __SHIFTIN(7, MMCR_PAR_TARGET) +#define MMCR_PAR_ATTR __BITS(28, 26) +#define MMCR_PAR_ATTR_NOEXEC __SHIFTIN(__BIT(2), MMCR_PAR_ATTR) +#define MMCR_PAR_ATTR_NOCACHE __SHIFTIN(__BIT(1), MMCR_PAR_ATTR) +#define MMCR_PAR_ATTR_NOWRITE __SHIFTIN(__BIT(0), MMCR_PAR_ATTR) +#define MMCR_PAR_PG_SZ __BIT(25) +#define MMCR_PAR_SZ_ST_ADR __BITS(24, 0) +#define MMCR_PAR_4KB_SZ __BITS(24, 18) +#define MMCR_PAR_4KB_ST_ADR __BITS(17, 0) +#define MMCR_PAR_64KB_SZ __BITS(24, 14) +#define MMCR_PAR_64KB_ST_ADR __BITS(13, 0) +#define MMCR_PAR_IO_SZ __BITS(24, 16) +#define MMCR_PAR_IO_ST_ADR __BITS(15, 0) + /* * General Purpose Bus Registers */