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Added BUS_DMA_COHERENT flag to bus_dmamem_map() to improve stability on aarch64. 

In ixgbe, TX/RX descriptor rings are configured in 16-byte units.
If BUS_DMA_COHERENT is not specified, cpu cache (writeback/invalidate)
operations by bus_dmamap_sync() in aarch64 (arm/arm32/bus_dma.c) are done per
cache line size (usually 64 bytes). As a result, adjacent descriptors conflict
with the DMA operation, resulting in unstable operation.

To avoid this, descriptors area should be mapped as non-cache with BUS_DMA_COHERENT.


thanks to msaitoh@ for his help in debugging.
This commit is contained in:
ryo 2021-05-20 01:02:42 +00:00
parent 8a7b619378
commit 3489cf27b4
1 changed files with 3 additions and 3 deletions
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6
sys/dev/pci/ixgbe/ix_txrx.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ix_txrx.c,v 1.75 2021/05/18 05:29:15 msaitoh Exp $ */
/* $NetBSD: ix_txrx.c,v 1.76 2021/05/20 01:02:42 ryo Exp $ */
/******************************************************************************
@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.75 2021/05/18 05:29:15 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.76 2021/05/20 01:02:42 ryo Exp $");
#include "opt_inet.h"
#include "opt_inet6.h"
@ -2208,7 +2208,7 @@ ixgbe_dma_malloc(struct adapter *adapter, const bus_size_t size,
}
r = bus_dmamem_map(dma->dma_tag->dt_dmat, &dma->dma_seg, rsegs,
size, &dma->dma_vaddr, BUS_DMA_NOWAIT);
size, &dma->dma_vaddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
if (r != 0) {
aprint_error_dev(dev, "%s: bus_dmamem_map failed; error %d\n",
__func__, r);