From 3489cf27b4571b1cb291ce0d97ea44b35dd1b5c2 Mon Sep 17 00:00:00 2001 From: ryo Date: Thu, 20 May 2021 01:02:42 +0000 Subject: [PATCH] Added BUS_DMA_COHERENT flag to bus_dmamem_map() to improve stability on aarch64. In ixgbe, TX/RX descriptor rings are configured in 16-byte units. If BUS_DMA_COHERENT is not specified, cpu cache (writeback/invalidate) operations by bus_dmamap_sync() in aarch64 (arm/arm32/bus_dma.c) are done per cache line size (usually 64 bytes). As a result, adjacent descriptors conflict with the DMA operation, resulting in unstable operation. To avoid this, descriptors area should be mapped as non-cache with BUS_DMA_COHERENT. thanks to msaitoh@ for his help in debugging. --- sys/dev/pci/ixgbe/ix_txrx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/dev/pci/ixgbe/ix_txrx.c b/sys/dev/pci/ixgbe/ix_txrx.c index 1f5da61f582d..e4d8770ee7ff 100644 --- a/sys/dev/pci/ixgbe/ix_txrx.c +++ b/sys/dev/pci/ixgbe/ix_txrx.c @@ -1,4 +1,4 @@ -/* $NetBSD: ix_txrx.c,v 1.75 2021/05/18 05:29:15 msaitoh Exp $ */ +/* $NetBSD: ix_txrx.c,v 1.76 2021/05/20 01:02:42 ryo Exp $ */ /****************************************************************************** @@ -64,7 +64,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.75 2021/05/18 05:29:15 msaitoh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ix_txrx.c,v 1.76 2021/05/20 01:02:42 ryo Exp $"); #include "opt_inet.h" #include "opt_inet6.h" @@ -2208,7 +2208,7 @@ ixgbe_dma_malloc(struct adapter *adapter, const bus_size_t size, } r = bus_dmamem_map(dma->dma_tag->dt_dmat, &dma->dma_seg, rsegs, - size, &dma->dma_vaddr, BUS_DMA_NOWAIT); + size, &dma->dma_vaddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); if (r != 0) { aprint_error_dev(dev, "%s: bus_dmamem_map failed; error %d\n", __func__, r);