Add peripheral clock defines, from FreeBSD.
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@ -1,4 +1,4 @@
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/* $NetBSD: am335x_prcm.h,v 1.6 2013/08/29 15:50:41 riz Exp $ */
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/* $NetBSD: am335x_prcm.h,v 1.7 2014/07/16 18:24:35 bouyer Exp $ */
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/*
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* TI OMAP Power, Reset, and Clock Management on the AM335x
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@ -44,8 +44,73 @@ struct omap_module {
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};
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#define AM335X_PRCM_CM_PER 0x0000
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#define CM_PER_L4LS_CLKSTCTRL 0x000
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#define CM_PER_L3S_CLKSTCTRL 0x004
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#define CM_PER_L3_CLKSTCTRL 0x00C
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#define CM_PER_CPGMAC0_CLKCTRL 0x014
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#define CM_PER_LCDC_CLKCTRL 0x018
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#define CM_PER_USB0_CLKCTRL 0x01C
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#define CM_PER_TPTC0_CLKCTRL 0x024
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#define CM_PER_UART5_CLKCTRL 0x038
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#define CM_PER_MMC0_CLKCTRL 0x03C
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#define CM_PER_I2C2_CLKCTRL 0x044
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#define CM_PER_I2C1_CLKCTRL 0x048
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#define CM_PER_UART1_CLKCTRL 0x06C
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#define CM_PER_UART2_CLKCTRL 0x070
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#define CM_PER_UART3_CLKCTRL 0x074
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#define CM_PER_UART4_CLKCTRL 0x078
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#define CM_PER_TIMER7_CLKCTRL 0x07C
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#define CM_PER_TIMER2_CLKCTRL 0x080
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#define CM_PER_TIMER3_CLKCTRL 0x084
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#define CM_PER_TIMER4_CLKCTRL 0x088
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#define CM_PER_GPIO1_CLKCTRL 0x0AC
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#define CM_PER_GPIO2_CLKCTRL 0x0B0
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#define CM_PER_GPIO3_CLKCTRL 0x0B4
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#define CM_PER_TPCC_CLKCTRL 0x0BC
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#define CM_PER_EPWMSS1_CLKCTRL 0x0CC
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#define CM_PER_EPWMSS0_CLKCTRL 0x0D4
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#define CM_PER_EPWMSS2_CLKCTRL 0x0D8
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#define CM_PER_L3_INSTR_CLKCTRL 0x0DC
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#define CM_PER_L3_CLKCTRL 0x0E0
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#define CM_PER_PRUSS_CLKCTRL 0x0E8
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#define CM_PER_TIMER5_CLKCTRL 0x0EC
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#define CM_PER_TIMER6_CLKCTRL 0x0F0
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#define CM_PER_MMC1_CLKCTRL 0x0F4
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#define CM_PER_MMC2_CLKCTRL 0x0F8
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#define CM_PER_TPTC1_CLKCTRL 0x0FC
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#define CM_PER_TPTC2_CLKCTRL 0x100
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#define CM_PER_SPINLOCK0_CLKCTRL 0x10C
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#define CM_PER_MAILBOX0_CLKCTRL 0x110
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#define CM_PER_OCPWP_L3_CLKSTCTRL 0x12C
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#define CM_PER_OCPWP_CLKCTRL 0x130
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#define CM_PER_CPSW_CLKSTCTRL 0x144
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#define CM_PER_PRUSS_CLKSTCTRL 0x140
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#define AM335X_PRCM_CM_WKUP 0x0400
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#define CM_WKUP_CLKSTCTRL 0x000
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#define CM_WKUP_CONTROL_CLKCTRL 0x004
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#define CM_WKUP_GPIO0_CLKCTRL 0x008
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#define CM_WKUP_CM_L3_AON_CLKSTCTRL 0x01C
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#define CM_WKUP_CM_CLKSEL_DPLL_MPU 0x02C
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#define CM_WKUP_CM_IDLEST_DPLL_DISP 0x048
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#define CM_WKUP_CM_CLKSEL_DPLL_DISP 0x054
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#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER 0x07C
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#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER_CLKDCOLDO_ST 0x200
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#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER_CLKDCOLDO_GATE_CTRL 0x100
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#define CM_WKUP_CM_CLKMODE_DPLL_DISP 0x098
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#define CM_WKUP_I2C0_CLKCTRL 0x0B8
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#define CM_WKUP_ADC_TSC_CLKCTRL 0x0BC
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#define AM335X_PRCM_CM_DPLL 0x0500
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#define CLKSEL_TIMER7_CLK 0x004
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#define CLKSEL_TIMER2_CLK 0x008
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#define CLKSEL_TIMER3_CLK 0x00C
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#define CLKSEL_TIMER4_CLK 0x010
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#define CLKSEL_TIMER5_CLK 0x018
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#define CLKSEL_TIMER6_CLK 0x01C
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#define CLKSEL_PRUSS_OCP_CLK 0x030
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#define AM335X_PRCM_CM_MPU 0x0600
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#define AM335X_PRCM_CM_DEVICE 0x0700
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#define AM335X_PRCM_CM_RTC 0x0800
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