From 3234e472fa0d17ecba85120564b83283ae9cb599 Mon Sep 17 00:00:00 2001 From: bouyer Date: Wed, 16 Jul 2014 18:24:35 +0000 Subject: [PATCH] Add peripheral clock defines, from FreeBSD. --- sys/arch/arm/omap/am335x_prcm.h | 67 ++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/sys/arch/arm/omap/am335x_prcm.h b/sys/arch/arm/omap/am335x_prcm.h index 0d0934c97598..aeae91e92c7a 100644 --- a/sys/arch/arm/omap/am335x_prcm.h +++ b/sys/arch/arm/omap/am335x_prcm.h @@ -1,4 +1,4 @@ -/* $NetBSD: am335x_prcm.h,v 1.6 2013/08/29 15:50:41 riz Exp $ */ +/* $NetBSD: am335x_prcm.h,v 1.7 2014/07/16 18:24:35 bouyer Exp $ */ /* * TI OMAP Power, Reset, and Clock Management on the AM335x @@ -44,8 +44,73 @@ struct omap_module { }; #define AM335X_PRCM_CM_PER 0x0000 +#define CM_PER_L4LS_CLKSTCTRL 0x000 +#define CM_PER_L3S_CLKSTCTRL 0x004 +#define CM_PER_L3_CLKSTCTRL 0x00C +#define CM_PER_CPGMAC0_CLKCTRL 0x014 +#define CM_PER_LCDC_CLKCTRL 0x018 +#define CM_PER_USB0_CLKCTRL 0x01C +#define CM_PER_TPTC0_CLKCTRL 0x024 +#define CM_PER_UART5_CLKCTRL 0x038 +#define CM_PER_MMC0_CLKCTRL 0x03C +#define CM_PER_I2C2_CLKCTRL 0x044 +#define CM_PER_I2C1_CLKCTRL 0x048 +#define CM_PER_UART1_CLKCTRL 0x06C +#define CM_PER_UART2_CLKCTRL 0x070 +#define CM_PER_UART3_CLKCTRL 0x074 +#define CM_PER_UART4_CLKCTRL 0x078 +#define CM_PER_TIMER7_CLKCTRL 0x07C +#define CM_PER_TIMER2_CLKCTRL 0x080 +#define CM_PER_TIMER3_CLKCTRL 0x084 +#define CM_PER_TIMER4_CLKCTRL 0x088 +#define CM_PER_GPIO1_CLKCTRL 0x0AC +#define CM_PER_GPIO2_CLKCTRL 0x0B0 +#define CM_PER_GPIO3_CLKCTRL 0x0B4 +#define CM_PER_TPCC_CLKCTRL 0x0BC +#define CM_PER_EPWMSS1_CLKCTRL 0x0CC +#define CM_PER_EPWMSS0_CLKCTRL 0x0D4 +#define CM_PER_EPWMSS2_CLKCTRL 0x0D8 +#define CM_PER_L3_INSTR_CLKCTRL 0x0DC +#define CM_PER_L3_CLKCTRL 0x0E0 +#define CM_PER_PRUSS_CLKCTRL 0x0E8 +#define CM_PER_TIMER5_CLKCTRL 0x0EC +#define CM_PER_TIMER6_CLKCTRL 0x0F0 +#define CM_PER_MMC1_CLKCTRL 0x0F4 +#define CM_PER_MMC2_CLKCTRL 0x0F8 +#define CM_PER_TPTC1_CLKCTRL 0x0FC +#define CM_PER_TPTC2_CLKCTRL 0x100 +#define CM_PER_SPINLOCK0_CLKCTRL 0x10C +#define CM_PER_MAILBOX0_CLKCTRL 0x110 +#define CM_PER_OCPWP_L3_CLKSTCTRL 0x12C +#define CM_PER_OCPWP_CLKCTRL 0x130 +#define CM_PER_CPSW_CLKSTCTRL 0x144 +#define CM_PER_PRUSS_CLKSTCTRL 0x140 + #define AM335X_PRCM_CM_WKUP 0x0400 +#define CM_WKUP_CLKSTCTRL 0x000 +#define CM_WKUP_CONTROL_CLKCTRL 0x004 +#define CM_WKUP_GPIO0_CLKCTRL 0x008 +#define CM_WKUP_CM_L3_AON_CLKSTCTRL 0x01C +#define CM_WKUP_CM_CLKSEL_DPLL_MPU 0x02C +#define CM_WKUP_CM_IDLEST_DPLL_DISP 0x048 +#define CM_WKUP_CM_CLKSEL_DPLL_DISP 0x054 +#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER 0x07C +#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER_CLKDCOLDO_ST 0x200 +#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER_CLKDCOLDO_GATE_CTRL 0x100 + +#define CM_WKUP_CM_CLKMODE_DPLL_DISP 0x098 +#define CM_WKUP_I2C0_CLKCTRL 0x0B8 +#define CM_WKUP_ADC_TSC_CLKCTRL 0x0BC + #define AM335X_PRCM_CM_DPLL 0x0500 +#define CLKSEL_TIMER7_CLK 0x004 +#define CLKSEL_TIMER2_CLK 0x008 +#define CLKSEL_TIMER3_CLK 0x00C +#define CLKSEL_TIMER4_CLK 0x010 +#define CLKSEL_TIMER5_CLK 0x018 +#define CLKSEL_TIMER6_CLK 0x01C +#define CLKSEL_PRUSS_OCP_CLK 0x030 + #define AM335X_PRCM_CM_MPU 0x0600 #define AM335X_PRCM_CM_DEVICE 0x0700 #define AM335X_PRCM_CM_RTC 0x0800