Adding the ns32k arch to gcc2.
This commit is contained in:
phil
parent
fa491c1bc9
commit
30f778234a
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# $Id: Makefile,v 1.1 1994/03/10 21:11:39 phil Exp $
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.include <bsd.prog.mk>
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/* Subroutines for assembler code output on the NS32000.
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Copyright (C) 1988 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Some output-actions in ns32k.md need these. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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#ifdef OSF_OS
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int ns32k_num_files = 0;
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#endif
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void
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trace (s, s1, s2)
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char *s, *s1, *s2;
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{
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fprintf (stderr, s, s1, s2);
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}
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
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int
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hard_regno_mode_ok (regno, mode)
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int regno;
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enum machine_mode mode;
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{
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switch (mode)
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{
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case QImode:
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case HImode:
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case PSImode:
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case SImode:
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case PDImode:
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case VOIDmode:
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case BLKmode:
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if (regno < 8 || regno == 16 || regno == 17)
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return 1;
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else
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return 0;
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case DImode:
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if (regno < 8 && (regno & 1) == 0)
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return 1;
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else
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return 0;
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case SFmode:
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case SCmode:
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if (TARGET_32081)
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{
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if (regno < 16)
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return 1;
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else
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return 0;
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}
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else
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{
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if (regno < 8)
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return 1;
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else
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return 0;
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}
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case DFmode:
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case DCmode:
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if ((regno & 1) == 0)
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{
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if (TARGET_32081)
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{
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if (regno < 16)
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return 1;
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else
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return 0;
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}
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else
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{
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if (regno < 8)
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return 1;
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else
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return 0;
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}
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}
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else
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return 0;
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}
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/* Used to abort here, but simply saying "no" handles TImode
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much better. */
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return 0;
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}
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/* ADDRESS_COST calls this. This function is not optimal
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for the 32032 & 32332, but it probably is better than
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the default. */
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int
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calc_address_cost (operand)
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rtx operand;
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{
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int i;
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int cost = 0;
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if (GET_CODE (operand) == MEM)
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cost += 3;
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if (GET_CODE (operand) == MULT)
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cost += 2;
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#if 0
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if (GET_CODE (operand) == REG)
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cost += 1; /* not really, but the documentation
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says different amount of registers
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shouldn't return the same costs */
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#endif
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switch (GET_CODE (operand))
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{
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case REG:
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case CONST:
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case CONST_INT:
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case CONST_DOUBLE:
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case SYMBOL_REF:
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case LABEL_REF:
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case POST_DEC:
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case PRE_DEC:
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break;
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case MULT:
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case MEM:
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case PLUS:
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for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
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{
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cost += calc_address_cost (XEXP (operand, i));
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}
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default:
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break;
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}
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return cost;
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}
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/* Return the register class of a scratch register needed to copy IN into
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or out of a register in CLASS in MODE. If it can be done directly,
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NO_REGS is returned. */
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enum reg_class
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secondary_reload_class (class, mode, in)
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enum reg_class class;
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enum machine_mode mode;
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rtx in;
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{
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int regno = true_regnum (in);
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if (regno >= FIRST_PSEUDO_REGISTER)
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regno = -1;
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/* We can place anything into GENERAL_REGS and can put GENERAL_REGS
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into anything. */
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if (class == GENERAL_REGS || (regno >= 0 && regno < 8))
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return NO_REGS;
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/* Constants, memory, and FP registers can go into FP registers. */
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if ((regno == -1 || (regno >= 8 && regno < 16)) && (class == FLOAT_REGS))
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return NO_REGS;
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#if 0 /* This isn't strictly true (can't move fp to sp or vice versa),
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so it's cleaner to use PREFERRED_RELOAD_CLASS
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to make the right things happen. */
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if (regno >= 16 && class == GEN_AND_MEM_REGS)
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return NO_REGS;
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#endif
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/* Otherwise, we need GENERAL_REGS. */
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return GENERAL_REGS;
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}
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/* Generate the rtx that comes from an address expression in the md file */
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/* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
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scale must be converted from an exponent (from ASHIFT) to a
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multiplier (for MULT). */
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rtx
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gen_indexed_expr (base, index, scale)
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rtx base, index, scale;
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{
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rtx addr;
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/* This generates an illegal addressing mode, if BASE is
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fp or sp. This is handled by PRINT_OPERAND_ADDRESS. */
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if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT)
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base = gen_rtx (MEM, SImode, base);
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addr = gen_rtx (MULT, SImode, index,
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gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (scale)));
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addr = gen_rtx (PLUS, SImode, base, addr);
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return addr;
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}
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/* Return 1 if OP is a valid operand of mode MODE. This
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predicate rejects operands which do not have a mode
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(such as CONST_INT which are VOIDmode). */
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int
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reg_or_mem_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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return (GET_MODE (op) == mode
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&& (GET_CODE (op) == REG
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|| GET_CODE (op) == SUBREG
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|| GET_CODE (op) == MEM));
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}
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/* Return the best assembler insn template
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for moving operands[1] into operands[0] as a fullword. */
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static char *
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singlemove_string (operands)
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rtx *operands;
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{
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if (GET_CODE (operands[1]) == CONST_INT
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&& INTVAL (operands[1]) <= 7
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&& INTVAL (operands[1]) >= -8)
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return "movqd %1,%0";
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return "movd %1,%0";
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}
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char *
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output_move_double (operands)
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rtx *operands;
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{
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enum anon1 { REGOP, OFFSOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
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rtx latehalf[2];
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/* First classify both operands. */
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if (REG_P (operands[0]))
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optype0 = REGOP;
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else if (offsettable_memref_p (operands[0]))
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optype0 = OFFSOP;
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else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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optype0 = POPOP;
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else
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optype0 = RNDOP;
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if (REG_P (operands[1]))
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optype1 = REGOP;
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else if (CONSTANT_ADDRESS_P (operands[1])
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|| GET_CODE (operands[1]) == CONST_DOUBLE)
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optype1 = CNSTOP;
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else if (offsettable_memref_p (operands[1]))
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optype1 = OFFSOP;
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else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
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optype1 = POPOP;
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else
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optype1 = RNDOP;
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/* Check for the cases that the operand constraints are not
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supposed to allow to happen. Abort if we get one,
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because generating code for these cases is painful. */
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if (optype0 == RNDOP || optype1 == RNDOP)
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abort ();
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/* Ok, we can do one word at a time.
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Normally we do the low-numbered word first,
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but if either operand is autodecrementing then we
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do the high-numbered word first.
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In either case, set up in LATEHALF the operands to use
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for the high-numbered word and in some cases alter the
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operands in OPERANDS to be suitable for the low-numbered word. */
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if (optype0 == REGOP)
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latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else if (optype0 == OFFSOP)
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latehalf[0] = adj_offsettable_operand (operands[0], 4);
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else
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latehalf[0] = operands[0];
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if (optype1 == REGOP)
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latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else if (optype1 == OFFSOP)
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latehalf[1] = adj_offsettable_operand (operands[1], 4);
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else if (optype1 == CNSTOP)
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{
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if (CONSTANT_ADDRESS_P (operands[1]))
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latehalf[1] = const0_rtx;
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else if (GET_CODE (operands[1]) == CONST_DOUBLE)
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split_double (operands[1], &operands[1], &latehalf[1]);
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}
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else
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latehalf[1] = operands[1];
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/* If one or both operands autodecrementing,
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do the two words, high-numbered first. */
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if (optype0 == POPOP || optype1 == POPOP)
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{
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output_asm_insn (singlemove_string (latehalf), latehalf);
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return singlemove_string (operands);
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}
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/* Not autodecrementing. Do the two words, low-numbered first. */
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output_asm_insn (singlemove_string (operands), operands);
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operands[0] = latehalf[0];
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operands[1] = latehalf[1];
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return singlemove_string (operands);
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}
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int
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check_reg (oper, reg)
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rtx oper;
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int reg;
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{
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register int i;
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if (oper == 0)
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return 0;
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switch (GET_CODE(oper))
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{
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case REG:
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return (REGNO(oper) == reg) ? 1 : 0;
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case MEM:
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return check_reg(XEXP(oper, 0), reg);
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case PLUS:
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case MULT:
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return check_reg(XEXP(oper, 0), reg) || check_reg(XEXP(oper, 1), reg);
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}
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return 0;
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}
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/* PRINT_OPERAND is defined to call this function,
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which is easier to debug than putting all the code in
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a macro definition in ns32k.h. */
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void
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print_operand (file, x, code)
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FILE *file;
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rtx x;
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char code;
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{
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if (code == '$')
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PUT_IMMEDIATE_PREFIX (file);
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else if (code == '?')
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PUT_EXTERNAL_PREFIX (file);
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else if (GET_CODE (x) == REG)
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fprintf (file, "%s", reg_names[REGNO (x)]);
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else if (GET_CODE (x) == MEM)
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{
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rtx tmp = XEXP (x, 0);
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#if ! (defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC))
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if (GET_CODE (tmp) != CONST_INT)
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{
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char *out = XSTR (tmp, 0);
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if (out[0] == '*')
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{
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PUT_ABSOLUTE_PREFIX (file);
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fprintf (file, "%s", &out[1]);
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}
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else
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ASM_OUTPUT_LABELREF (file, out);
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}
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else
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#endif
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output_address (XEXP (x, 0));
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}
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else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode)
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{
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if (GET_MODE (x) == DFmode)
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{
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union { double d; int i[2]; } u;
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u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
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PUT_IMMEDIATE_PREFIX(file);
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#ifdef SEQUENT_ASM
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/* Sequent likes it's floating point constants as integers */
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fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
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#else
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#ifdef ENCORE_ASM
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fprintf (file, "0f%.20e", u.d);
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#else
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fprintf (file, "0d%.20e", u.d);
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#endif
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#endif
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}
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else
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{
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union { double d; int i[2]; } u;
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u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
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PUT_IMMEDIATE_PREFIX (file);
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#ifdef SEQUENT_ASM
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/* We have no way of winning if we can't get the bits
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for a sequent floating point number. */
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#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
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abort ();
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#endif
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{
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union { float f; long l; } uu;
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uu.f = u.d;
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fprintf (file, "0Fx%08x", uu.l);
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}
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#else
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fprintf (file, "0f%.20e", u.d);
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#endif
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}
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}
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else
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{
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#ifdef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
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if (GET_CODE (x) == CONST_INT)
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#endif
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PUT_IMMEDIATE_PREFIX (file);
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output_addr_const (file, x);
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}
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}
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|
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/* PRINT_OPERAND_ADDRESS is defined to call this function,
|
||||
which is easier to debug than putting all the code in
|
||||
a macro definition in ns32k.h . */
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||||
/* Completely rewritten to get this to work with Gas for PC532 Mach.
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||||
This function didn't work and I just wasn't able (nor very willing) to
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figure out how it worked.
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||||
90-11-25 Tatu Yl|nen <ylo@cs.hut.fi> */
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print_operand_address (file, addr)
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register FILE *file;
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register rtx addr;
|
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{
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||||
static char scales[] = { 'b', 'w', 'd', 0, 'q', };
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rtx offset, base, indexexp, tmp;
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int scale;
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if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC)
|
||||
{
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fprintf (file, "tos");
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return;
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}
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||||
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||||
offset = NULL;
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||||
base = NULL;
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||||
indexexp = NULL;
|
||||
while (addr != NULL)
|
||||
{
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if (GET_CODE (addr) == PLUS)
|
||||
{
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||||
if (GET_CODE (XEXP (addr, 0)) == PLUS)
|
||||
{
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||||
tmp = XEXP (addr, 1);
|
||||
addr = XEXP (addr, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = XEXP (addr,0);
|
||||
addr = XEXP (addr,1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = addr;
|
||||
addr = NULL;
|
||||
}
|
||||
switch (GET_CODE (tmp))
|
||||
{
|
||||
case PLUS:
|
||||
abort ();
|
||||
case MEM:
|
||||
if (base)
|
||||
{
|
||||
indexexp = base;
|
||||
base = tmp;
|
||||
}
|
||||
else
|
||||
base = tmp;
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||||
break;
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||||
case REG:
|
||||
if (REGNO (tmp) < 8)
|
||||
if (base)
|
||||
{
|
||||
indexexp = tmp;
|
||||
}
|
||||
else
|
||||
base = tmp;
|
||||
else
|
||||
if (base)
|
||||
{
|
||||
indexexp = base;
|
||||
base = tmp;
|
||||
}
|
||||
else
|
||||
base = tmp;
|
||||
break;
|
||||
case MULT:
|
||||
indexexp = tmp;
|
||||
break;
|
||||
case CONST:
|
||||
case CONST_INT:
|
||||
case SYMBOL_REF:
|
||||
case LABEL_REF:
|
||||
if (offset)
|
||||
offset = gen_rtx (PLUS, SImode, tmp, offset);
|
||||
else
|
||||
offset = tmp;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
if (! offset)
|
||||
offset = const0_rtx;
|
||||
|
||||
#ifdef INDEX_RATHER_THAN_BASE
|
||||
/* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix. */
|
||||
if (base && !indexexp && GET_CODE (base) == REG
|
||||
&& REG_OK_FOR_INDEX_P (base))
|
||||
{
|
||||
indexexp = base;
|
||||
base = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* now, offset, base and indexexp are set */
|
||||
if (! base)
|
||||
{
|
||||
#if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)
|
||||
if (GET_CODE (offset) == CONST_INT)
|
||||
/* if (! (GET_CODE (offset) == LABEL_REF
|
||||
|| GET_CODE (offset) == SYMBOL_REF)) */
|
||||
#endif
|
||||
PUT_ABSOLUTE_PREFIX (file);
|
||||
}
|
||||
|
||||
output_addr_const (file, offset);
|
||||
if (base) /* base can be (REG ...) or (MEM ...) */
|
||||
switch (GET_CODE (base))
|
||||
{
|
||||
/* now we must output base. Possible alternatives are:
|
||||
(rN) (REG ...)
|
||||
(sp) (REG ...)
|
||||
(fp) (REG ...)
|
||||
(pc) (REG ...) used for SYMBOL_REF and LABEL_REF, output
|
||||
(disp(fp)) (MEM ...) just before possible [rX:y]
|
||||
(disp(sp)) (MEM ...)
|
||||
(disp(sb)) (MEM ...)
|
||||
*/
|
||||
case REG:
|
||||
fprintf (file, "(%s)", reg_names[REGNO (base)]);
|
||||
break;
|
||||
case MEM:
|
||||
addr = XEXP(base,0);
|
||||
base = NULL;
|
||||
offset = NULL;
|
||||
while (addr != NULL)
|
||||
{
|
||||
if (GET_CODE (addr) == PLUS)
|
||||
{
|
||||
if (GET_CODE (XEXP (addr, 0)) == PLUS)
|
||||
{
|
||||
tmp = XEXP (addr, 1);
|
||||
addr = XEXP (addr, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = XEXP (addr, 0);
|
||||
addr = XEXP (addr, 1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = addr;
|
||||
addr = NULL;
|
||||
}
|
||||
switch (GET_CODE (tmp))
|
||||
{
|
||||
case REG:
|
||||
base = tmp;
|
||||
break;
|
||||
case CONST:
|
||||
case CONST_INT:
|
||||
case SYMBOL_REF:
|
||||
case LABEL_REF:
|
||||
if (offset)
|
||||
offset = gen_rtx (PLUS, SImode, tmp, offset);
|
||||
else
|
||||
offset = tmp;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
if (! offset)
|
||||
offset = const0_rtx;
|
||||
fprintf (file, "(");
|
||||
output_addr_const (file, offset);
|
||||
if (base)
|
||||
fprintf (file, "(%s)", reg_names[REGNO (base)]);
|
||||
#ifdef BASE_REG_NEEDED
|
||||
else if (TARGET_SB)
|
||||
fprintf (file, "(sb)");
|
||||
else
|
||||
abort ();
|
||||
#endif
|
||||
fprintf (file, ")");
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
#ifdef PC_RELATIVE
|
||||
else /* no base */
|
||||
if (GET_CODE (offset) == LABEL_REF || GET_CODE (offset) == SYMBOL_REF)
|
||||
fprintf (file, "(pc)");
|
||||
#endif
|
||||
#ifdef BASE_REG_NEEDED /* this is defined if the assembler always
|
||||
needs a base register */
|
||||
else if (TARGET_SB)
|
||||
fprintf (file, "(sb)");
|
||||
else
|
||||
abort ();
|
||||
#endif
|
||||
/* now print index if we have one */
|
||||
if (indexexp)
|
||||
{
|
||||
if (GET_CODE (indexexp) == MULT)
|
||||
{
|
||||
scale = INTVAL (XEXP (indexexp, 1)) >> 1;
|
||||
indexexp = XEXP (indexexp, 0);
|
||||
}
|
||||
else
|
||||
scale = 0;
|
||||
if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= 8)
|
||||
abort ();
|
||||
|
||||
#ifdef UTEK_ASM
|
||||
fprintf (file, "[%c`%s]",
|
||||
scales[scale],
|
||||
reg_names[REGNO (indexexp)]);
|
||||
#else
|
||||
fprintf (file, "[%s:%c]",
|
||||
reg_names[REGNO (indexexp)],
|
||||
scales[scale]);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* National 32032 shifting is so bad that we can get
|
||||
better performance in many common cases by using other
|
||||
techniques. */
|
||||
char *
|
||||
output_shift_insn (operands)
|
||||
rtx *operands;
|
||||
{
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& INTVAL (operands[2]) > 0
|
||||
&& INTVAL (operands[2]) <= 3)
|
||||
if (GET_CODE (operands[0]) == REG)
|
||||
{
|
||||
if (GET_CODE (operands[1]) == REG)
|
||||
{
|
||||
if (REGNO (operands[0]) == REGNO (operands[1]))
|
||||
{
|
||||
if (operands[2] == const1_rtx)
|
||||
return "addd %0,%0";
|
||||
else if (INTVAL (operands[2]) == 2)
|
||||
return "addd %0,%0\n\taddd %0,%0";
|
||||
}
|
||||
if (operands[2] == const1_rtx)
|
||||
return "movd %1,%0\n\taddd %0,%0";
|
||||
|
||||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||||
return "addr %a1,%0";
|
||||
}
|
||||
if (operands[2] == const1_rtx)
|
||||
return "movd %1,%0\n\taddd %0,%0";
|
||||
}
|
||||
else if (GET_CODE (operands[1]) == REG)
|
||||
{
|
||||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||||
return "addr %a1,%0";
|
||||
}
|
||||
else if (INTVAL (operands[2]) == 1
|
||||
&& GET_CODE (operands[1]) == MEM
|
||||
&& rtx_equal_p (operands [0], operands[1]))
|
||||
{
|
||||
rtx temp = XEXP (operands[1], 0);
|
||||
|
||||
if (GET_CODE (temp) == REG
|
||||
|| (GET_CODE (temp) == PLUS
|
||||
&& GET_CODE (XEXP (temp, 0)) == REG
|
||||
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
|
||||
return "addd %0,%0";
|
||||
}
|
||||
else return "ashd %2,%0";
|
||||
return "ashd %2,%0";
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/* Configuration for GNU C-compiler for Vax.
|
||||
Copyright (C) 1987 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
||||
GNU CC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GNU CC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GNU CC; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
/* #defines that need visibility everywhere. */
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
|
||||
/* target machine dependencies.
|
||||
tm.h is a symbolic link to the actual target specific file. */
|
||||
#include "tm.h"
|
||||
|
||||
/* This describes the machine the compiler is hosted on. */
|
||||
#define HOST_BITS_PER_CHAR 8
|
||||
#define HOST_BITS_PER_SHORT 16
|
||||
#define HOST_BITS_PER_INT 32
|
||||
#define HOST_BITS_PER_LONG 32
|
||||
#define HOST_BITS_PER_LONGLONG 64
|
||||
|
||||
/* Arguments to use with `exit'. */
|
||||
#define SUCCESS_EXIT_CODE 0
|
||||
#define FATAL_EXIT_CODE 33
|
||||
|
||||
#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
|
||||
#define memset gcc_memset
|
||||
#define memcmp(left,right,len) bcmp ((left),(right),(len))
|
||||
|
||||
/* If compiled with GNU C, use the built-in alloca */
|
||||
#ifdef __GNUC__
|
||||
#define alloca __builtin_alloca
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Generated automatically by the program `genattr'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#ifndef PROTO
|
||||
#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__)
|
||||
#define PROTO(ARGS) ARGS
|
||||
#else
|
||||
#define PROTO(ARGS) ()
|
||||
#endif
|
||||
#endif
|
||||
#define HAVE_ATTR_alternative
|
||||
#define get_attr_alternative(insn) which_alternative
|
||||
|
||||
#define ATTR_FLAG_forward 0x1
|
||||
#define ATTR_FLAG_backward 0x2
|
||||
#define ATTR_FLAG_likely 0x4
|
||||
#define ATTR_FLAG_very_likely 0x8
|
||||
#define ATTR_FLAG_unlikely 0x10
|
||||
#define ATTR_FLAG_very_unlikely 0x20
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* Generated automatically by the program `genattrtab'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#include "config.h"
|
||||
#include "rtl.h"
|
||||
#include "insn-config.h"
|
||||
#include "recog.h"
|
||||
#include "regs.h"
|
||||
#include "real.h"
|
||||
#include "output.h"
|
||||
#include "insn-attr.h"
|
||||
|
||||
#define operands recog_operand
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/* Generated automatically by the program `gencodes'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#ifndef MAX_INSN_CODE
|
||||
|
||||
enum insn_code {
|
||||
CODE_FOR_tstsi = 0,
|
||||
CODE_FOR_tsthi = 1,
|
||||
CODE_FOR_tstqi = 2,
|
||||
CODE_FOR_tstdf = 3,
|
||||
CODE_FOR_tstsf = 4,
|
||||
CODE_FOR_cmpsi = 5,
|
||||
CODE_FOR_cmphi = 6,
|
||||
CODE_FOR_cmpqi = 7,
|
||||
CODE_FOR_cmpdf = 8,
|
||||
CODE_FOR_cmpsf = 9,
|
||||
CODE_FOR_movdf = 10,
|
||||
CODE_FOR_movsf = 11,
|
||||
CODE_FOR_movdi = 13,
|
||||
CODE_FOR_movsi = 15,
|
||||
CODE_FOR_movhi = 16,
|
||||
CODE_FOR_movstricthi = 17,
|
||||
CODE_FOR_movqi = 18,
|
||||
CODE_FOR_movstrictqi = 19,
|
||||
CODE_FOR_movstrsi = 20,
|
||||
CODE_FOR_movstrsi1 = 21,
|
||||
CODE_FOR_truncsiqi2 = 22,
|
||||
CODE_FOR_truncsihi2 = 23,
|
||||
CODE_FOR_trunchiqi2 = 24,
|
||||
CODE_FOR_extendhisi2 = 25,
|
||||
CODE_FOR_extendqihi2 = 26,
|
||||
CODE_FOR_extendqisi2 = 27,
|
||||
CODE_FOR_extendsfdf2 = 28,
|
||||
CODE_FOR_truncdfsf2 = 29,
|
||||
CODE_FOR_zero_extendhisi2 = 30,
|
||||
CODE_FOR_zero_extendqihi2 = 31,
|
||||
CODE_FOR_zero_extendqisi2 = 32,
|
||||
CODE_FOR_floatsisf2 = 33,
|
||||
CODE_FOR_floatsidf2 = 34,
|
||||
CODE_FOR_floathisf2 = 35,
|
||||
CODE_FOR_floathidf2 = 36,
|
||||
CODE_FOR_floatqisf2 = 37,
|
||||
CODE_FOR_fixsfqi2 = 38,
|
||||
CODE_FOR_fixsfhi2 = 39,
|
||||
CODE_FOR_fixsfsi2 = 40,
|
||||
CODE_FOR_fixdfqi2 = 41,
|
||||
CODE_FOR_fixdfhi2 = 42,
|
||||
CODE_FOR_fixdfsi2 = 43,
|
||||
CODE_FOR_fixunssfqi2 = 44,
|
||||
CODE_FOR_fixunssfhi2 = 45,
|
||||
CODE_FOR_fixunssfsi2 = 46,
|
||||
CODE_FOR_fixunsdfqi2 = 47,
|
||||
CODE_FOR_fixunsdfhi2 = 48,
|
||||
CODE_FOR_fixunsdfsi2 = 49,
|
||||
CODE_FOR_fix_truncsfqi2 = 50,
|
||||
CODE_FOR_fix_truncsfhi2 = 51,
|
||||
CODE_FOR_fix_truncsfsi2 = 52,
|
||||
CODE_FOR_fix_truncdfqi2 = 53,
|
||||
CODE_FOR_fix_truncdfhi2 = 54,
|
||||
CODE_FOR_fix_truncdfsi2 = 55,
|
||||
CODE_FOR_adddf3 = 56,
|
||||
CODE_FOR_addsf3 = 57,
|
||||
CODE_FOR_addsi3 = 61,
|
||||
CODE_FOR_addhi3 = 62,
|
||||
CODE_FOR_addqi3 = 64,
|
||||
CODE_FOR_subdf3 = 66,
|
||||
CODE_FOR_subsf3 = 67,
|
||||
CODE_FOR_subsi3 = 69,
|
||||
CODE_FOR_subhi3 = 70,
|
||||
CODE_FOR_subqi3 = 72,
|
||||
CODE_FOR_muldf3 = 74,
|
||||
CODE_FOR_mulsf3 = 75,
|
||||
CODE_FOR_mulsi3 = 76,
|
||||
CODE_FOR_mulhi3 = 77,
|
||||
CODE_FOR_mulqi3 = 78,
|
||||
CODE_FOR_umulsidi3 = 79,
|
||||
CODE_FOR_divdf3 = 80,
|
||||
CODE_FOR_divsf3 = 81,
|
||||
CODE_FOR_divsi3 = 82,
|
||||
CODE_FOR_divhi3 = 83,
|
||||
CODE_FOR_divqi3 = 84,
|
||||
CODE_FOR_udivsi3 = 85,
|
||||
CODE_FOR_udivhi3 = 86,
|
||||
CODE_FOR_udivqi3 = 87,
|
||||
CODE_FOR_modsi3 = 88,
|
||||
CODE_FOR_modhi3 = 89,
|
||||
CODE_FOR_modqi3 = 90,
|
||||
CODE_FOR_umodsi3 = 91,
|
||||
CODE_FOR_umodhi3 = 92,
|
||||
CODE_FOR_umodqi3 = 93,
|
||||
CODE_FOR_andsi3 = 94,
|
||||
CODE_FOR_andhi3 = 95,
|
||||
CODE_FOR_andqi3 = 96,
|
||||
CODE_FOR_iorsi3 = 100,
|
||||
CODE_FOR_iorhi3 = 101,
|
||||
CODE_FOR_iorqi3 = 102,
|
||||
CODE_FOR_xorsi3 = 103,
|
||||
CODE_FOR_xorhi3 = 104,
|
||||
CODE_FOR_xorqi3 = 105,
|
||||
CODE_FOR_negdf2 = 106,
|
||||
CODE_FOR_negsf2 = 107,
|
||||
CODE_FOR_negsi2 = 108,
|
||||
CODE_FOR_neghi2 = 109,
|
||||
CODE_FOR_negqi2 = 110,
|
||||
CODE_FOR_one_cmplsi2 = 111,
|
||||
CODE_FOR_one_cmplhi2 = 112,
|
||||
CODE_FOR_one_cmplqi2 = 113,
|
||||
CODE_FOR_ashlsi3 = 114,
|
||||
CODE_FOR_ashlhi3 = 115,
|
||||
CODE_FOR_ashlqi3 = 116,
|
||||
CODE_FOR_ashrsi3 = 117,
|
||||
CODE_FOR_ashrhi3 = 120,
|
||||
CODE_FOR_ashrqi3 = 123,
|
||||
CODE_FOR_lshlsi3 = 126,
|
||||
CODE_FOR_lshlhi3 = 127,
|
||||
CODE_FOR_lshlqi3 = 128,
|
||||
CODE_FOR_lshrsi3 = 129,
|
||||
CODE_FOR_lshrhi3 = 132,
|
||||
CODE_FOR_lshrqi3 = 135,
|
||||
CODE_FOR_rotlsi3 = 138,
|
||||
CODE_FOR_rotlhi3 = 139,
|
||||
CODE_FOR_rotlqi3 = 140,
|
||||
CODE_FOR_rotrsi3 = 141,
|
||||
CODE_FOR_rotrhi3 = 144,
|
||||
CODE_FOR_rotrqi3 = 147,
|
||||
CODE_FOR_extzv = 158,
|
||||
CODE_FOR_insv = 161,
|
||||
CODE_FOR_jump = 162,
|
||||
CODE_FOR_beq = 163,
|
||||
CODE_FOR_bne = 164,
|
||||
CODE_FOR_bgt = 165,
|
||||
CODE_FOR_bgtu = 166,
|
||||
CODE_FOR_blt = 167,
|
||||
CODE_FOR_bltu = 168,
|
||||
CODE_FOR_bge = 169,
|
||||
CODE_FOR_bgeu = 170,
|
||||
CODE_FOR_ble = 171,
|
||||
CODE_FOR_bleu = 172,
|
||||
CODE_FOR_call = 185,
|
||||
CODE_FOR_call_value = 186,
|
||||
CODE_FOR_untyped_call = 187,
|
||||
CODE_FOR_blockage = 188,
|
||||
CODE_FOR_return = 189,
|
||||
CODE_FOR_abssf2 = 190,
|
||||
CODE_FOR_absdf2 = 191,
|
||||
CODE_FOR_abssi2 = 192,
|
||||
CODE_FOR_abshi2 = 193,
|
||||
CODE_FOR_absqi2 = 194,
|
||||
CODE_FOR_nop = 195,
|
||||
CODE_FOR_indirect_jump = 196,
|
||||
CODE_FOR_tablejump = 197,
|
||||
CODE_FOR_seq = 198,
|
||||
CODE_FOR_sne = 201,
|
||||
CODE_FOR_sgt = 204,
|
||||
CODE_FOR_sgtu = 207,
|
||||
CODE_FOR_slt = 210,
|
||||
CODE_FOR_sltu = 213,
|
||||
CODE_FOR_sge = 216,
|
||||
CODE_FOR_sgeu = 219,
|
||||
CODE_FOR_sle = 222,
|
||||
CODE_FOR_sleu = 225,
|
||||
CODE_FOR_nothing };
|
||||
|
||||
#define MAX_INSN_CODE ((int) CODE_FOR_nothing)
|
||||
#endif /* MAX_INSN_CODE */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* Generated automatically by the program `genconfig'
|
||||
from the machine description file `md'. */
|
||||
|
||||
|
||||
#define MAX_RECOG_OPERANDS 10
|
||||
|
||||
#define MAX_DUP_OPERANDS 3
|
||||
#ifndef MAX_INSNS_PER_SPLIT
|
||||
#define MAX_INSNS_PER_SPLIT 1
|
||||
#endif
|
||||
#define REGISTER_CONSTRAINTS
|
||||
#define HAVE_cc0
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,381 @@
|
|||
/* Generated automatically by the program `genextract'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#include "config.h"
|
||||
#include "rtl.h"
|
||||
|
||||
static rtx junk;
|
||||
extern rtx recog_operand[];
|
||||
extern rtx *recog_operand_loc[];
|
||||
extern rtx *recog_dup_loc[];
|
||||
extern char recog_dup_num[];
|
||||
extern
|
||||
#ifdef __GNUC__
|
||||
__volatile__
|
||||
#endif
|
||||
void fatal_insn_not_found ();
|
||||
|
||||
void
|
||||
insn_extract (insn)
|
||||
rtx insn;
|
||||
{
|
||||
register rtx *ro = recog_operand;
|
||||
register rtx **ro_loc = recog_operand_loc;
|
||||
rtx pat = PATTERN (insn);
|
||||
switch (INSN_CODE (insn))
|
||||
{
|
||||
case -1:
|
||||
fatal_insn_not_found (insn);
|
||||
|
||||
case 227:
|
||||
case 226:
|
||||
case 225:
|
||||
case 224:
|
||||
case 223:
|
||||
case 222:
|
||||
case 221:
|
||||
case 220:
|
||||
case 219:
|
||||
case 218:
|
||||
case 217:
|
||||
case 216:
|
||||
case 215:
|
||||
case 214:
|
||||
case 213:
|
||||
case 212:
|
||||
case 211:
|
||||
case 210:
|
||||
case 209:
|
||||
case 208:
|
||||
case 207:
|
||||
case 206:
|
||||
case 205:
|
||||
case 204:
|
||||
case 203:
|
||||
case 202:
|
||||
case 201:
|
||||
case 200:
|
||||
case 199:
|
||||
case 198:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
break;
|
||||
|
||||
case 197:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0));
|
||||
break;
|
||||
|
||||
case 195:
|
||||
case 189:
|
||||
case 188:
|
||||
break;
|
||||
|
||||
case 184:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 1));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0));
|
||||
ro[3] = *(ro_loc[3] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1));
|
||||
recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0);
|
||||
recog_dup_num[0] = 0;
|
||||
recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0);
|
||||
recog_dup_num[1] = 0;
|
||||
break;
|
||||
|
||||
case 183:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 1));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0));
|
||||
recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0);
|
||||
recog_dup_num[0] = 0;
|
||||
recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0);
|
||||
recog_dup_num[1] = 0;
|
||||
recog_dup_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1);
|
||||
recog_dup_num[2] = 1;
|
||||
break;
|
||||
|
||||
case 182:
|
||||
case 181:
|
||||
case 180:
|
||||
case 179:
|
||||
case 178:
|
||||
case 177:
|
||||
case 176:
|
||||
case 175:
|
||||
case 174:
|
||||
case 173:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 2), 0));
|
||||
break;
|
||||
|
||||
case 172:
|
||||
case 171:
|
||||
case 170:
|
||||
case 169:
|
||||
case 168:
|
||||
case 167:
|
||||
case 166:
|
||||
case 165:
|
||||
case 164:
|
||||
case 163:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 1), 0));
|
||||
break;
|
||||
|
||||
case 162:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0));
|
||||
break;
|
||||
|
||||
case 161:
|
||||
case 160:
|
||||
case 159:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 1));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2));
|
||||
ro[3] = *(ro_loc[3] = &XEXP (pat, 1));
|
||||
break;
|
||||
|
||||
case 158:
|
||||
case 157:
|
||||
case 156:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1));
|
||||
ro[3] = *(ro_loc[3] = &XEXP (XEXP (pat, 1), 2));
|
||||
break;
|
||||
|
||||
case 155:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 2));
|
||||
break;
|
||||
|
||||
case 154:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XEXP (pat, 1), 0), 0), 1));
|
||||
recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 1);
|
||||
recog_dup_num[0] = 0;
|
||||
break;
|
||||
|
||||
case 153:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 1));
|
||||
recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 1);
|
||||
recog_dup_num[0] = 0;
|
||||
break;
|
||||
|
||||
case 152:
|
||||
case 151:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 2));
|
||||
break;
|
||||
|
||||
case 149:
|
||||
case 146:
|
||||
case 143:
|
||||
case 137:
|
||||
case 134:
|
||||
case 131:
|
||||
case 125:
|
||||
case 122:
|
||||
case 119:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0));
|
||||
break;
|
||||
|
||||
case 99:
|
||||
case 98:
|
||||
case 97:
|
||||
case 93:
|
||||
case 92:
|
||||
case 91:
|
||||
case 87:
|
||||
case 86:
|
||||
case 85:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1));
|
||||
break;
|
||||
|
||||
case 79:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0));
|
||||
break;
|
||||
|
||||
case 73:
|
||||
case 71:
|
||||
case 65:
|
||||
case 63:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1));
|
||||
break;
|
||||
|
||||
case 60:
|
||||
case 59:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1));
|
||||
break;
|
||||
|
||||
case 68:
|
||||
case 58:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 1));
|
||||
break;
|
||||
|
||||
case 186:
|
||||
case 148:
|
||||
case 145:
|
||||
case 142:
|
||||
case 140:
|
||||
case 139:
|
||||
case 138:
|
||||
case 136:
|
||||
case 133:
|
||||
case 130:
|
||||
case 128:
|
||||
case 127:
|
||||
case 126:
|
||||
case 124:
|
||||
case 121:
|
||||
case 118:
|
||||
case 116:
|
||||
case 115:
|
||||
case 114:
|
||||
case 105:
|
||||
case 104:
|
||||
case 103:
|
||||
case 102:
|
||||
case 101:
|
||||
case 100:
|
||||
case 96:
|
||||
case 95:
|
||||
case 94:
|
||||
case 90:
|
||||
case 89:
|
||||
case 88:
|
||||
case 84:
|
||||
case 83:
|
||||
case 82:
|
||||
case 81:
|
||||
case 80:
|
||||
case 78:
|
||||
case 77:
|
||||
case 76:
|
||||
case 75:
|
||||
case 74:
|
||||
case 72:
|
||||
case 70:
|
||||
case 69:
|
||||
case 67:
|
||||
case 66:
|
||||
case 64:
|
||||
case 62:
|
||||
case 61:
|
||||
case 57:
|
||||
case 56:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1));
|
||||
break;
|
||||
|
||||
case 49:
|
||||
case 48:
|
||||
case 47:
|
||||
case 46:
|
||||
case 45:
|
||||
case 44:
|
||||
case 43:
|
||||
case 42:
|
||||
case 41:
|
||||
case 40:
|
||||
case 39:
|
||||
case 38:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0));
|
||||
break;
|
||||
|
||||
case 194:
|
||||
case 193:
|
||||
case 192:
|
||||
case 191:
|
||||
case 190:
|
||||
case 113:
|
||||
case 112:
|
||||
case 111:
|
||||
case 110:
|
||||
case 109:
|
||||
case 108:
|
||||
case 107:
|
||||
case 106:
|
||||
case 55:
|
||||
case 54:
|
||||
case 53:
|
||||
case 52:
|
||||
case 51:
|
||||
case 50:
|
||||
case 37:
|
||||
case 36:
|
||||
case 35:
|
||||
case 34:
|
||||
case 33:
|
||||
case 32:
|
||||
case 31:
|
||||
case 30:
|
||||
case 29:
|
||||
case 28:
|
||||
case 27:
|
||||
case 26:
|
||||
case 25:
|
||||
case 24:
|
||||
case 23:
|
||||
case 22:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0));
|
||||
break;
|
||||
|
||||
case 21:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1));
|
||||
ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0));
|
||||
break;
|
||||
|
||||
case 19:
|
||||
case 17:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (pat, 1));
|
||||
break;
|
||||
|
||||
case 185:
|
||||
case 150:
|
||||
case 18:
|
||||
case 16:
|
||||
case 15:
|
||||
case 13:
|
||||
case 12:
|
||||
case 11:
|
||||
case 10:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (pat, 1));
|
||||
break;
|
||||
|
||||
case 9:
|
||||
case 8:
|
||||
case 7:
|
||||
case 6:
|
||||
case 5:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0));
|
||||
ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1));
|
||||
break;
|
||||
|
||||
case 196:
|
||||
case 14:
|
||||
case 4:
|
||||
case 3:
|
||||
case 2:
|
||||
case 1:
|
||||
case 0:
|
||||
ro[0] = *(ro_loc[0] = &XEXP (pat, 1));
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,480 @@
|
|||
/* Generated automatically by the program `genflags'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#define HAVE_tstsi 1
|
||||
#define HAVE_tsthi 1
|
||||
#define HAVE_tstqi 1
|
||||
#define HAVE_tstdf (TARGET_32081)
|
||||
#define HAVE_tstsf (TARGET_32081)
|
||||
#define HAVE_cmpsi 1
|
||||
#define HAVE_cmphi 1
|
||||
#define HAVE_cmpqi 1
|
||||
#define HAVE_cmpdf (TARGET_32081)
|
||||
#define HAVE_cmpsf (TARGET_32081)
|
||||
#define HAVE_movdf 1
|
||||
#define HAVE_movsf 1
|
||||
#define HAVE_movdi 1
|
||||
#define HAVE_movsi 1
|
||||
#define HAVE_movhi 1
|
||||
#define HAVE_movstricthi 1
|
||||
#define HAVE_movqi 1
|
||||
#define HAVE_movstrictqi 1
|
||||
#define HAVE_movstrsi 1
|
||||
#define HAVE_movstrsi1 1
|
||||
#define HAVE_truncsiqi2 1
|
||||
#define HAVE_truncsihi2 1
|
||||
#define HAVE_trunchiqi2 1
|
||||
#define HAVE_extendhisi2 1
|
||||
#define HAVE_extendqihi2 1
|
||||
#define HAVE_extendqisi2 1
|
||||
#define HAVE_extendsfdf2 (TARGET_32081)
|
||||
#define HAVE_truncdfsf2 (TARGET_32081)
|
||||
#define HAVE_zero_extendhisi2 1
|
||||
#define HAVE_zero_extendqihi2 1
|
||||
#define HAVE_zero_extendqisi2 1
|
||||
#define HAVE_floatsisf2 (TARGET_32081)
|
||||
#define HAVE_floatsidf2 (TARGET_32081)
|
||||
#define HAVE_floathisf2 (TARGET_32081)
|
||||
#define HAVE_floathidf2 (TARGET_32081)
|
||||
#define HAVE_floatqisf2 (TARGET_32081)
|
||||
#define HAVE_fixsfqi2 (TARGET_32081)
|
||||
#define HAVE_fixsfhi2 (TARGET_32081)
|
||||
#define HAVE_fixsfsi2 (TARGET_32081)
|
||||
#define HAVE_fixdfqi2 (TARGET_32081)
|
||||
#define HAVE_fixdfhi2 (TARGET_32081)
|
||||
#define HAVE_fixdfsi2 (TARGET_32081)
|
||||
#define HAVE_fixunssfqi2 (TARGET_32081)
|
||||
#define HAVE_fixunssfhi2 (TARGET_32081)
|
||||
#define HAVE_fixunssfsi2 (TARGET_32081)
|
||||
#define HAVE_fixunsdfqi2 (TARGET_32081)
|
||||
#define HAVE_fixunsdfhi2 (TARGET_32081)
|
||||
#define HAVE_fixunsdfsi2 (TARGET_32081)
|
||||
#define HAVE_fix_truncsfqi2 (TARGET_32081)
|
||||
#define HAVE_fix_truncsfhi2 (TARGET_32081)
|
||||
#define HAVE_fix_truncsfsi2 (TARGET_32081)
|
||||
#define HAVE_fix_truncdfqi2 (TARGET_32081)
|
||||
#define HAVE_fix_truncdfhi2 (TARGET_32081)
|
||||
#define HAVE_fix_truncdfsi2 (TARGET_32081)
|
||||
#define HAVE_adddf3 (TARGET_32081)
|
||||
#define HAVE_addsf3 (TARGET_32081)
|
||||
#define HAVE_addsi3 1
|
||||
#define HAVE_addhi3 1
|
||||
#define HAVE_addqi3 1
|
||||
#define HAVE_subdf3 (TARGET_32081)
|
||||
#define HAVE_subsf3 (TARGET_32081)
|
||||
#define HAVE_subsi3 1
|
||||
#define HAVE_subhi3 1
|
||||
#define HAVE_subqi3 1
|
||||
#define HAVE_muldf3 (TARGET_32081)
|
||||
#define HAVE_mulsf3 (TARGET_32081)
|
||||
#define HAVE_mulsi3 1
|
||||
#define HAVE_mulhi3 1
|
||||
#define HAVE_mulqi3 1
|
||||
#define HAVE_umulsidi3 1
|
||||
#define HAVE_divdf3 (TARGET_32081)
|
||||
#define HAVE_divsf3 (TARGET_32081)
|
||||
#define HAVE_divsi3 1
|
||||
#define HAVE_divhi3 1
|
||||
#define HAVE_divqi3 1
|
||||
#define HAVE_udivsi3 1
|
||||
#define HAVE_udivhi3 1
|
||||
#define HAVE_udivqi3 1
|
||||
#define HAVE_modsi3 1
|
||||
#define HAVE_modhi3 1
|
||||
#define HAVE_modqi3 1
|
||||
#define HAVE_umodsi3 1
|
||||
#define HAVE_umodhi3 1
|
||||
#define HAVE_umodqi3 1
|
||||
#define HAVE_andsi3 1
|
||||
#define HAVE_andhi3 1
|
||||
#define HAVE_andqi3 1
|
||||
#define HAVE_iorsi3 1
|
||||
#define HAVE_iorhi3 1
|
||||
#define HAVE_iorqi3 1
|
||||
#define HAVE_xorsi3 1
|
||||
#define HAVE_xorhi3 1
|
||||
#define HAVE_xorqi3 1
|
||||
#define HAVE_negdf2 (TARGET_32081)
|
||||
#define HAVE_negsf2 (TARGET_32081)
|
||||
#define HAVE_negsi2 1
|
||||
#define HAVE_neghi2 1
|
||||
#define HAVE_negqi2 1
|
||||
#define HAVE_one_cmplsi2 1
|
||||
#define HAVE_one_cmplhi2 1
|
||||
#define HAVE_one_cmplqi2 1
|
||||
#define HAVE_ashlsi3 1
|
||||
#define HAVE_ashlhi3 1
|
||||
#define HAVE_ashlqi3 1
|
||||
#define HAVE_ashrsi3 1
|
||||
#define HAVE_ashrhi3 1
|
||||
#define HAVE_ashrqi3 1
|
||||
#define HAVE_lshlsi3 1
|
||||
#define HAVE_lshlhi3 1
|
||||
#define HAVE_lshlqi3 1
|
||||
#define HAVE_lshrsi3 1
|
||||
#define HAVE_lshrhi3 1
|
||||
#define HAVE_lshrqi3 1
|
||||
#define HAVE_rotlsi3 1
|
||||
#define HAVE_rotlhi3 1
|
||||
#define HAVE_rotlqi3 1
|
||||
#define HAVE_rotrsi3 1
|
||||
#define HAVE_rotrhi3 1
|
||||
#define HAVE_rotrqi3 1
|
||||
#define HAVE_extzv 1
|
||||
#define HAVE_insv 1
|
||||
#define HAVE_jump 1
|
||||
#define HAVE_beq 1
|
||||
#define HAVE_bne 1
|
||||
#define HAVE_bgt 1
|
||||
#define HAVE_bgtu 1
|
||||
#define HAVE_blt 1
|
||||
#define HAVE_bltu 1
|
||||
#define HAVE_bge 1
|
||||
#define HAVE_bgeu 1
|
||||
#define HAVE_ble 1
|
||||
#define HAVE_bleu 1
|
||||
#define HAVE_call 1
|
||||
#define HAVE_call_value 1
|
||||
#define HAVE_untyped_call 1
|
||||
#define HAVE_blockage 1
|
||||
#define HAVE_return (0)
|
||||
#define HAVE_abssf2 (TARGET_32081)
|
||||
#define HAVE_absdf2 (TARGET_32081)
|
||||
#define HAVE_abssi2 1
|
||||
#define HAVE_abshi2 1
|
||||
#define HAVE_absqi2 1
|
||||
#define HAVE_nop 1
|
||||
#define HAVE_indirect_jump 1
|
||||
#define HAVE_tablejump 1
|
||||
#define HAVE_seq 1
|
||||
#define HAVE_sne 1
|
||||
#define HAVE_sgt 1
|
||||
#define HAVE_sgtu 1
|
||||
#define HAVE_slt 1
|
||||
#define HAVE_sltu 1
|
||||
#define HAVE_sge 1
|
||||
#define HAVE_sgeu 1
|
||||
#define HAVE_sle 1
|
||||
#define HAVE_sleu 1
|
||||
|
||||
#ifndef NO_MD_PROTOTYPES
|
||||
extern rtx gen_tstsi PROTO((rtx));
|
||||
extern rtx gen_tsthi PROTO((rtx));
|
||||
extern rtx gen_tstqi PROTO((rtx));
|
||||
extern rtx gen_tstdf PROTO((rtx));
|
||||
extern rtx gen_tstsf PROTO((rtx));
|
||||
extern rtx gen_cmpsi PROTO((rtx, rtx));
|
||||
extern rtx gen_cmphi PROTO((rtx, rtx));
|
||||
extern rtx gen_cmpqi PROTO((rtx, rtx));
|
||||
extern rtx gen_cmpdf PROTO((rtx, rtx));
|
||||
extern rtx gen_cmpsf PROTO((rtx, rtx));
|
||||
extern rtx gen_movdf PROTO((rtx, rtx));
|
||||
extern rtx gen_movsf PROTO((rtx, rtx));
|
||||
extern rtx gen_movdi PROTO((rtx, rtx));
|
||||
extern rtx gen_movsi PROTO((rtx, rtx));
|
||||
extern rtx gen_movhi PROTO((rtx, rtx));
|
||||
extern rtx gen_movstricthi PROTO((rtx, rtx));
|
||||
extern rtx gen_movqi PROTO((rtx, rtx));
|
||||
extern rtx gen_movstrictqi PROTO((rtx, rtx));
|
||||
extern rtx gen_movstrsi PROTO((rtx, rtx, rtx, rtx));
|
||||
extern rtx gen_movstrsi1 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_truncsiqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_truncsihi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_trunchiqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_extendhisi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_extendqihi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_extendqisi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_extendsfdf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_truncdfsf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_zero_extendhisi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_zero_extendqihi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_zero_extendqisi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_floatsisf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_floatsidf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_floathisf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_floathidf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_floatqisf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixsfqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixsfhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixsfsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixdfqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixdfhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixdfsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixunssfqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixunssfhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixunssfsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixunsdfqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixunsdfhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fixunsdfsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fix_truncsfqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fix_truncsfhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fix_truncsfsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fix_truncdfqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fix_truncdfhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_fix_truncdfsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_adddf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_addsf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_addsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_addhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_addqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_subdf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_subsf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_subsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_subhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_subqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_muldf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_mulsf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_mulsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_mulhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_mulqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_umulsidi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_divdf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_divsf3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_divsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_divhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_divqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_udivsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_udivhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_udivqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_modsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_modhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_modqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_umodsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_umodhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_umodqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_andsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_andhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_andqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_iorsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_iorhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_iorqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_xorsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_xorhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_xorqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_negdf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_negsf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_negsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_neghi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_negqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_one_cmplsi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_one_cmplhi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_one_cmplqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_ashlsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_ashlhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_ashlqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_ashrsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_ashrhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_ashrqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_lshlsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_lshlhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_lshlqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_lshrsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_lshrhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_lshrqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_rotlsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_rotlhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_rotlqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_rotrsi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_rotrhi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_rotrqi3 PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_extzv PROTO((rtx, rtx, rtx, rtx));
|
||||
extern rtx gen_insv PROTO((rtx, rtx, rtx, rtx));
|
||||
extern rtx gen_jump PROTO((rtx));
|
||||
extern rtx gen_beq PROTO((rtx));
|
||||
extern rtx gen_bne PROTO((rtx));
|
||||
extern rtx gen_bgt PROTO((rtx));
|
||||
extern rtx gen_bgtu PROTO((rtx));
|
||||
extern rtx gen_blt PROTO((rtx));
|
||||
extern rtx gen_bltu PROTO((rtx));
|
||||
extern rtx gen_bge PROTO((rtx));
|
||||
extern rtx gen_bgeu PROTO((rtx));
|
||||
extern rtx gen_ble PROTO((rtx));
|
||||
extern rtx gen_bleu PROTO((rtx));
|
||||
extern rtx gen_untyped_call PROTO((rtx, rtx, rtx));
|
||||
extern rtx gen_blockage PROTO((void));
|
||||
extern rtx gen_return PROTO((void));
|
||||
extern rtx gen_abssf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_absdf2 PROTO((rtx, rtx));
|
||||
extern rtx gen_abssi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_abshi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_absqi2 PROTO((rtx, rtx));
|
||||
extern rtx gen_nop PROTO((void));
|
||||
extern rtx gen_indirect_jump PROTO((rtx));
|
||||
extern rtx gen_tablejump PROTO((rtx, rtx));
|
||||
extern rtx gen_seq PROTO((rtx));
|
||||
extern rtx gen_sne PROTO((rtx));
|
||||
extern rtx gen_sgt PROTO((rtx));
|
||||
extern rtx gen_sgtu PROTO((rtx));
|
||||
extern rtx gen_slt PROTO((rtx));
|
||||
extern rtx gen_sltu PROTO((rtx));
|
||||
extern rtx gen_sge PROTO((rtx));
|
||||
extern rtx gen_sgeu PROTO((rtx));
|
||||
extern rtx gen_sle PROTO((rtx));
|
||||
extern rtx gen_sleu PROTO((rtx));
|
||||
|
||||
#ifdef MD_CALL_PROTOTYPES
|
||||
extern rtx gen_call PROTO((rtx, rtx));
|
||||
extern rtx gen_call_value PROTO((rtx, rtx, rtx));
|
||||
|
||||
#else /* !MD_CALL_PROTOTYPES */
|
||||
extern rtx gen_call ();
|
||||
extern rtx gen_call_value ();
|
||||
#endif /* !MD_CALL_PROTOTYPES */
|
||||
|
||||
#else /* NO_MD_PROTOTYPES */
|
||||
extern rtx gen_tstsi ();
|
||||
extern rtx gen_tsthi ();
|
||||
extern rtx gen_tstqi ();
|
||||
extern rtx gen_tstdf ();
|
||||
extern rtx gen_tstsf ();
|
||||
extern rtx gen_cmpsi ();
|
||||
extern rtx gen_cmphi ();
|
||||
extern rtx gen_cmpqi ();
|
||||
extern rtx gen_cmpdf ();
|
||||
extern rtx gen_cmpsf ();
|
||||
extern rtx gen_movdf ();
|
||||
extern rtx gen_movsf ();
|
||||
extern rtx gen_movdi ();
|
||||
extern rtx gen_movsi ();
|
||||
extern rtx gen_movhi ();
|
||||
extern rtx gen_movstricthi ();
|
||||
extern rtx gen_movqi ();
|
||||
extern rtx gen_movstrictqi ();
|
||||
extern rtx gen_movstrsi ();
|
||||
extern rtx gen_movstrsi1 ();
|
||||
extern rtx gen_truncsiqi2 ();
|
||||
extern rtx gen_truncsihi2 ();
|
||||
extern rtx gen_trunchiqi2 ();
|
||||
extern rtx gen_extendhisi2 ();
|
||||
extern rtx gen_extendqihi2 ();
|
||||
extern rtx gen_extendqisi2 ();
|
||||
extern rtx gen_extendsfdf2 ();
|
||||
extern rtx gen_truncdfsf2 ();
|
||||
extern rtx gen_zero_extendhisi2 ();
|
||||
extern rtx gen_zero_extendqihi2 ();
|
||||
extern rtx gen_zero_extendqisi2 ();
|
||||
extern rtx gen_floatsisf2 ();
|
||||
extern rtx gen_floatsidf2 ();
|
||||
extern rtx gen_floathisf2 ();
|
||||
extern rtx gen_floathidf2 ();
|
||||
extern rtx gen_floatqisf2 ();
|
||||
extern rtx gen_fixsfqi2 ();
|
||||
extern rtx gen_fixsfhi2 ();
|
||||
extern rtx gen_fixsfsi2 ();
|
||||
extern rtx gen_fixdfqi2 ();
|
||||
extern rtx gen_fixdfhi2 ();
|
||||
extern rtx gen_fixdfsi2 ();
|
||||
extern rtx gen_fixunssfqi2 ();
|
||||
extern rtx gen_fixunssfhi2 ();
|
||||
extern rtx gen_fixunssfsi2 ();
|
||||
extern rtx gen_fixunsdfqi2 ();
|
||||
extern rtx gen_fixunsdfhi2 ();
|
||||
extern rtx gen_fixunsdfsi2 ();
|
||||
extern rtx gen_fix_truncsfqi2 ();
|
||||
extern rtx gen_fix_truncsfhi2 ();
|
||||
extern rtx gen_fix_truncsfsi2 ();
|
||||
extern rtx gen_fix_truncdfqi2 ();
|
||||
extern rtx gen_fix_truncdfhi2 ();
|
||||
extern rtx gen_fix_truncdfsi2 ();
|
||||
extern rtx gen_adddf3 ();
|
||||
extern rtx gen_addsf3 ();
|
||||
extern rtx gen_addsi3 ();
|
||||
extern rtx gen_addhi3 ();
|
||||
extern rtx gen_addqi3 ();
|
||||
extern rtx gen_subdf3 ();
|
||||
extern rtx gen_subsf3 ();
|
||||
extern rtx gen_subsi3 ();
|
||||
extern rtx gen_subhi3 ();
|
||||
extern rtx gen_subqi3 ();
|
||||
extern rtx gen_muldf3 ();
|
||||
extern rtx gen_mulsf3 ();
|
||||
extern rtx gen_mulsi3 ();
|
||||
extern rtx gen_mulhi3 ();
|
||||
extern rtx gen_mulqi3 ();
|
||||
extern rtx gen_umulsidi3 ();
|
||||
extern rtx gen_divdf3 ();
|
||||
extern rtx gen_divsf3 ();
|
||||
extern rtx gen_divsi3 ();
|
||||
extern rtx gen_divhi3 ();
|
||||
extern rtx gen_divqi3 ();
|
||||
extern rtx gen_udivsi3 ();
|
||||
extern rtx gen_udivhi3 ();
|
||||
extern rtx gen_udivqi3 ();
|
||||
extern rtx gen_modsi3 ();
|
||||
extern rtx gen_modhi3 ();
|
||||
extern rtx gen_modqi3 ();
|
||||
extern rtx gen_umodsi3 ();
|
||||
extern rtx gen_umodhi3 ();
|
||||
extern rtx gen_umodqi3 ();
|
||||
extern rtx gen_andsi3 ();
|
||||
extern rtx gen_andhi3 ();
|
||||
extern rtx gen_andqi3 ();
|
||||
extern rtx gen_iorsi3 ();
|
||||
extern rtx gen_iorhi3 ();
|
||||
extern rtx gen_iorqi3 ();
|
||||
extern rtx gen_xorsi3 ();
|
||||
extern rtx gen_xorhi3 ();
|
||||
extern rtx gen_xorqi3 ();
|
||||
extern rtx gen_negdf2 ();
|
||||
extern rtx gen_negsf2 ();
|
||||
extern rtx gen_negsi2 ();
|
||||
extern rtx gen_neghi2 ();
|
||||
extern rtx gen_negqi2 ();
|
||||
extern rtx gen_one_cmplsi2 ();
|
||||
extern rtx gen_one_cmplhi2 ();
|
||||
extern rtx gen_one_cmplqi2 ();
|
||||
extern rtx gen_ashlsi3 ();
|
||||
extern rtx gen_ashlhi3 ();
|
||||
extern rtx gen_ashlqi3 ();
|
||||
extern rtx gen_ashrsi3 ();
|
||||
extern rtx gen_ashrhi3 ();
|
||||
extern rtx gen_ashrqi3 ();
|
||||
extern rtx gen_lshlsi3 ();
|
||||
extern rtx gen_lshlhi3 ();
|
||||
extern rtx gen_lshlqi3 ();
|
||||
extern rtx gen_lshrsi3 ();
|
||||
extern rtx gen_lshrhi3 ();
|
||||
extern rtx gen_lshrqi3 ();
|
||||
extern rtx gen_rotlsi3 ();
|
||||
extern rtx gen_rotlhi3 ();
|
||||
extern rtx gen_rotlqi3 ();
|
||||
extern rtx gen_rotrsi3 ();
|
||||
extern rtx gen_rotrhi3 ();
|
||||
extern rtx gen_rotrqi3 ();
|
||||
extern rtx gen_extzv ();
|
||||
extern rtx gen_insv ();
|
||||
extern rtx gen_jump ();
|
||||
extern rtx gen_beq ();
|
||||
extern rtx gen_bne ();
|
||||
extern rtx gen_bgt ();
|
||||
extern rtx gen_bgtu ();
|
||||
extern rtx gen_blt ();
|
||||
extern rtx gen_bltu ();
|
||||
extern rtx gen_bge ();
|
||||
extern rtx gen_bgeu ();
|
||||
extern rtx gen_ble ();
|
||||
extern rtx gen_bleu ();
|
||||
extern rtx gen_untyped_call ();
|
||||
extern rtx gen_blockage ();
|
||||
extern rtx gen_return ();
|
||||
extern rtx gen_abssf2 ();
|
||||
extern rtx gen_absdf2 ();
|
||||
extern rtx gen_abssi2 ();
|
||||
extern rtx gen_abshi2 ();
|
||||
extern rtx gen_absqi2 ();
|
||||
extern rtx gen_nop ();
|
||||
extern rtx gen_indirect_jump ();
|
||||
extern rtx gen_tablejump ();
|
||||
extern rtx gen_seq ();
|
||||
extern rtx gen_sne ();
|
||||
extern rtx gen_sgt ();
|
||||
extern rtx gen_sgtu ();
|
||||
extern rtx gen_slt ();
|
||||
extern rtx gen_sltu ();
|
||||
extern rtx gen_sge ();
|
||||
extern rtx gen_sgeu ();
|
||||
extern rtx gen_sle ();
|
||||
extern rtx gen_sleu ();
|
||||
extern rtx gen_call ();
|
||||
extern rtx gen_call_value ();
|
||||
#endif /* NO_MD_PROTOTYPES */
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
/* Generated automatically by the program `genopinit'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#include "config.h"
|
||||
#include "rtl.h"
|
||||
#include "flags.h"
|
||||
#include "insn-flags.h"
|
||||
#include "insn-codes.h"
|
||||
#include "insn-config.h"
|
||||
#include "recog.h"
|
||||
#include "expr.h"
|
||||
#include "reload.h"
|
||||
|
||||
void
|
||||
init_all_optabs ()
|
||||
{
|
||||
tst_optab->handlers[(int) SImode].insn_code = CODE_FOR_tstsi;
|
||||
tst_optab->handlers[(int) HImode].insn_code = CODE_FOR_tsthi;
|
||||
tst_optab->handlers[(int) QImode].insn_code = CODE_FOR_tstqi;
|
||||
if (HAVE_tstdf)
|
||||
tst_optab->handlers[(int) DFmode].insn_code = CODE_FOR_tstdf;
|
||||
if (HAVE_tstsf)
|
||||
tst_optab->handlers[(int) SFmode].insn_code = CODE_FOR_tstsf;
|
||||
cmp_optab->handlers[(int) SImode].insn_code = CODE_FOR_cmpsi;
|
||||
cmp_optab->handlers[(int) HImode].insn_code = CODE_FOR_cmphi;
|
||||
cmp_optab->handlers[(int) QImode].insn_code = CODE_FOR_cmpqi;
|
||||
if (HAVE_cmpdf)
|
||||
cmp_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cmpdf;
|
||||
if (HAVE_cmpsf)
|
||||
cmp_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cmpsf;
|
||||
mov_optab->handlers[(int) DFmode].insn_code = CODE_FOR_movdf;
|
||||
mov_optab->handlers[(int) SFmode].insn_code = CODE_FOR_movsf;
|
||||
mov_optab->handlers[(int) DImode].insn_code = CODE_FOR_movdi;
|
||||
mov_optab->handlers[(int) SImode].insn_code = CODE_FOR_movsi;
|
||||
mov_optab->handlers[(int) HImode].insn_code = CODE_FOR_movhi;
|
||||
movstrict_optab->handlers[(int) HImode].insn_code = CODE_FOR_movstricthi;
|
||||
mov_optab->handlers[(int) QImode].insn_code = CODE_FOR_movqi;
|
||||
movstrict_optab->handlers[(int) QImode].insn_code = CODE_FOR_movstrictqi;
|
||||
movstr_optab[(int) SImode] = CODE_FOR_movstrsi;
|
||||
extendtab[(int) SImode][(int) HImode][0] = CODE_FOR_extendhisi2;
|
||||
extendtab[(int) HImode][(int) QImode][0] = CODE_FOR_extendqihi2;
|
||||
extendtab[(int) SImode][(int) QImode][0] = CODE_FOR_extendqisi2;
|
||||
if (HAVE_extendsfdf2)
|
||||
extendtab[(int) DFmode][(int) SFmode][0] = CODE_FOR_extendsfdf2;
|
||||
extendtab[(int) SImode][(int) HImode][1] = CODE_FOR_zero_extendhisi2;
|
||||
extendtab[(int) HImode][(int) QImode][1] = CODE_FOR_zero_extendqihi2;
|
||||
extendtab[(int) SImode][(int) QImode][1] = CODE_FOR_zero_extendqisi2;
|
||||
if (HAVE_floatsisf2)
|
||||
floattab[(int) SFmode][(int) SImode][0] = CODE_FOR_floatsisf2;
|
||||
if (HAVE_floatsidf2)
|
||||
floattab[(int) DFmode][(int) SImode][0] = CODE_FOR_floatsidf2;
|
||||
if (HAVE_floathisf2)
|
||||
floattab[(int) SFmode][(int) HImode][0] = CODE_FOR_floathisf2;
|
||||
if (HAVE_floathidf2)
|
||||
floattab[(int) DFmode][(int) HImode][0] = CODE_FOR_floathidf2;
|
||||
if (HAVE_floatqisf2)
|
||||
floattab[(int) SFmode][(int) QImode][0] = CODE_FOR_floatqisf2;
|
||||
if (HAVE_fixsfqi2)
|
||||
fixtab[(int) SFmode][(int) QImode][0] = CODE_FOR_fixsfqi2;
|
||||
if (HAVE_fixsfhi2)
|
||||
fixtab[(int) SFmode][(int) HImode][0] = CODE_FOR_fixsfhi2;
|
||||
if (HAVE_fixsfsi2)
|
||||
fixtab[(int) SFmode][(int) SImode][0] = CODE_FOR_fixsfsi2;
|
||||
if (HAVE_fixdfqi2)
|
||||
fixtab[(int) DFmode][(int) QImode][0] = CODE_FOR_fixdfqi2;
|
||||
if (HAVE_fixdfhi2)
|
||||
fixtab[(int) DFmode][(int) HImode][0] = CODE_FOR_fixdfhi2;
|
||||
if (HAVE_fixdfsi2)
|
||||
fixtab[(int) DFmode][(int) SImode][0] = CODE_FOR_fixdfsi2;
|
||||
if (HAVE_fixunssfqi2)
|
||||
fixtab[(int) SFmode][(int) QImode][1] = CODE_FOR_fixunssfqi2;
|
||||
if (HAVE_fixunssfhi2)
|
||||
fixtab[(int) SFmode][(int) HImode][1] = CODE_FOR_fixunssfhi2;
|
||||
if (HAVE_fixunssfsi2)
|
||||
fixtab[(int) SFmode][(int) SImode][1] = CODE_FOR_fixunssfsi2;
|
||||
if (HAVE_fixunsdfqi2)
|
||||
fixtab[(int) DFmode][(int) QImode][1] = CODE_FOR_fixunsdfqi2;
|
||||
if (HAVE_fixunsdfhi2)
|
||||
fixtab[(int) DFmode][(int) HImode][1] = CODE_FOR_fixunsdfhi2;
|
||||
if (HAVE_fixunsdfsi2)
|
||||
fixtab[(int) DFmode][(int) SImode][1] = CODE_FOR_fixunsdfsi2;
|
||||
if (HAVE_fix_truncsfqi2)
|
||||
fixtrunctab[(int) SFmode][(int) QImode][0] = CODE_FOR_fix_truncsfqi2;
|
||||
if (HAVE_fix_truncsfhi2)
|
||||
fixtrunctab[(int) SFmode][(int) HImode][0] = CODE_FOR_fix_truncsfhi2;
|
||||
if (HAVE_fix_truncsfsi2)
|
||||
fixtrunctab[(int) SFmode][(int) SImode][0] = CODE_FOR_fix_truncsfsi2;
|
||||
if (HAVE_fix_truncdfqi2)
|
||||
fixtrunctab[(int) DFmode][(int) QImode][0] = CODE_FOR_fix_truncdfqi2;
|
||||
if (HAVE_fix_truncdfhi2)
|
||||
fixtrunctab[(int) DFmode][(int) HImode][0] = CODE_FOR_fix_truncdfhi2;
|
||||
if (HAVE_fix_truncdfsi2)
|
||||
fixtrunctab[(int) DFmode][(int) SImode][0] = CODE_FOR_fix_truncdfsi2;
|
||||
if (HAVE_adddf3)
|
||||
add_optab->handlers[(int) DFmode].insn_code = CODE_FOR_adddf3;
|
||||
if (HAVE_addsf3)
|
||||
add_optab->handlers[(int) SFmode].insn_code = CODE_FOR_addsf3;
|
||||
add_optab->handlers[(int) SImode].insn_code = CODE_FOR_addsi3;
|
||||
add_optab->handlers[(int) HImode].insn_code = CODE_FOR_addhi3;
|
||||
add_optab->handlers[(int) QImode].insn_code = CODE_FOR_addqi3;
|
||||
if (HAVE_subdf3)
|
||||
sub_optab->handlers[(int) DFmode].insn_code = CODE_FOR_subdf3;
|
||||
if (HAVE_subsf3)
|
||||
sub_optab->handlers[(int) SFmode].insn_code = CODE_FOR_subsf3;
|
||||
sub_optab->handlers[(int) SImode].insn_code = CODE_FOR_subsi3;
|
||||
sub_optab->handlers[(int) HImode].insn_code = CODE_FOR_subhi3;
|
||||
sub_optab->handlers[(int) QImode].insn_code = CODE_FOR_subqi3;
|
||||
if (HAVE_muldf3)
|
||||
smul_optab->handlers[(int) DFmode].insn_code = CODE_FOR_muldf3;
|
||||
if (HAVE_mulsf3)
|
||||
smul_optab->handlers[(int) SFmode].insn_code = CODE_FOR_mulsf3;
|
||||
smul_optab->handlers[(int) SImode].insn_code = CODE_FOR_mulsi3;
|
||||
smul_optab->handlers[(int) HImode].insn_code = CODE_FOR_mulhi3;
|
||||
smul_optab->handlers[(int) QImode].insn_code = CODE_FOR_mulqi3;
|
||||
umul_widen_optab->handlers[(int) DImode].insn_code = CODE_FOR_umulsidi3;
|
||||
if (HAVE_divdf3)
|
||||
flodiv_optab->handlers[(int) DFmode].insn_code = CODE_FOR_divdf3;
|
||||
if (HAVE_divsf3)
|
||||
flodiv_optab->handlers[(int) SFmode].insn_code = CODE_FOR_divsf3;
|
||||
sdiv_optab->handlers[(int) SImode].insn_code = CODE_FOR_divsi3;
|
||||
sdiv_optab->handlers[(int) HImode].insn_code = CODE_FOR_divhi3;
|
||||
sdiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_divqi3;
|
||||
udiv_optab->handlers[(int) SImode].insn_code = CODE_FOR_udivsi3;
|
||||
udiv_optab->handlers[(int) HImode].insn_code = CODE_FOR_udivhi3;
|
||||
udiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_udivqi3;
|
||||
smod_optab->handlers[(int) SImode].insn_code = CODE_FOR_modsi3;
|
||||
smod_optab->handlers[(int) HImode].insn_code = CODE_FOR_modhi3;
|
||||
smod_optab->handlers[(int) QImode].insn_code = CODE_FOR_modqi3;
|
||||
umod_optab->handlers[(int) SImode].insn_code = CODE_FOR_umodsi3;
|
||||
umod_optab->handlers[(int) HImode].insn_code = CODE_FOR_umodhi3;
|
||||
umod_optab->handlers[(int) QImode].insn_code = CODE_FOR_umodqi3;
|
||||
and_optab->handlers[(int) SImode].insn_code = CODE_FOR_andsi3;
|
||||
and_optab->handlers[(int) HImode].insn_code = CODE_FOR_andhi3;
|
||||
and_optab->handlers[(int) QImode].insn_code = CODE_FOR_andqi3;
|
||||
ior_optab->handlers[(int) SImode].insn_code = CODE_FOR_iorsi3;
|
||||
ior_optab->handlers[(int) HImode].insn_code = CODE_FOR_iorhi3;
|
||||
ior_optab->handlers[(int) QImode].insn_code = CODE_FOR_iorqi3;
|
||||
xor_optab->handlers[(int) SImode].insn_code = CODE_FOR_xorsi3;
|
||||
xor_optab->handlers[(int) HImode].insn_code = CODE_FOR_xorhi3;
|
||||
xor_optab->handlers[(int) QImode].insn_code = CODE_FOR_xorqi3;
|
||||
if (HAVE_negdf2)
|
||||
neg_optab->handlers[(int) DFmode].insn_code = CODE_FOR_negdf2;
|
||||
if (HAVE_negsf2)
|
||||
neg_optab->handlers[(int) SFmode].insn_code = CODE_FOR_negsf2;
|
||||
neg_optab->handlers[(int) SImode].insn_code = CODE_FOR_negsi2;
|
||||
neg_optab->handlers[(int) HImode].insn_code = CODE_FOR_neghi2;
|
||||
neg_optab->handlers[(int) QImode].insn_code = CODE_FOR_negqi2;
|
||||
one_cmpl_optab->handlers[(int) SImode].insn_code = CODE_FOR_one_cmplsi2;
|
||||
one_cmpl_optab->handlers[(int) HImode].insn_code = CODE_FOR_one_cmplhi2;
|
||||
one_cmpl_optab->handlers[(int) QImode].insn_code = CODE_FOR_one_cmplqi2;
|
||||
ashl_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashlsi3;
|
||||
ashl_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashlhi3;
|
||||
ashl_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashlqi3;
|
||||
ashr_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashrsi3;
|
||||
ashr_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashrhi3;
|
||||
ashr_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashrqi3;
|
||||
lshl_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshlsi3;
|
||||
lshl_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshlhi3;
|
||||
lshl_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshlqi3;
|
||||
lshr_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshrsi3;
|
||||
lshr_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshrhi3;
|
||||
lshr_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshrqi3;
|
||||
rotl_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotlsi3;
|
||||
rotl_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotlhi3;
|
||||
rotl_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotlqi3;
|
||||
rotr_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotrsi3;
|
||||
rotr_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotrhi3;
|
||||
rotr_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotrqi3;
|
||||
bcc_gen_fctn[(int) EQ] = gen_beq;
|
||||
bcc_gen_fctn[(int) NE] = gen_bne;
|
||||
bcc_gen_fctn[(int) GT] = gen_bgt;
|
||||
bcc_gen_fctn[(int) GTU] = gen_bgtu;
|
||||
bcc_gen_fctn[(int) LT] = gen_blt;
|
||||
bcc_gen_fctn[(int) LTU] = gen_bltu;
|
||||
bcc_gen_fctn[(int) GE] = gen_bge;
|
||||
bcc_gen_fctn[(int) GEU] = gen_bgeu;
|
||||
bcc_gen_fctn[(int) LE] = gen_ble;
|
||||
bcc_gen_fctn[(int) LEU] = gen_bleu;
|
||||
if (HAVE_abssf2)
|
||||
abs_optab->handlers[(int) SFmode].insn_code = CODE_FOR_abssf2;
|
||||
if (HAVE_absdf2)
|
||||
abs_optab->handlers[(int) DFmode].insn_code = CODE_FOR_absdf2;
|
||||
abs_optab->handlers[(int) SImode].insn_code = CODE_FOR_abssi2;
|
||||
abs_optab->handlers[(int) HImode].insn_code = CODE_FOR_abshi2;
|
||||
abs_optab->handlers[(int) QImode].insn_code = CODE_FOR_absqi2;
|
||||
setcc_gen_code[(int) EQ] = CODE_FOR_seq;
|
||||
setcc_gen_code[(int) NE] = CODE_FOR_sne;
|
||||
setcc_gen_code[(int) GT] = CODE_FOR_sgt;
|
||||
setcc_gen_code[(int) GTU] = CODE_FOR_sgtu;
|
||||
setcc_gen_code[(int) LT] = CODE_FOR_slt;
|
||||
setcc_gen_code[(int) LTU] = CODE_FOR_sltu;
|
||||
setcc_gen_code[(int) GE] = CODE_FOR_sge;
|
||||
setcc_gen_code[(int) GEU] = CODE_FOR_sgeu;
|
||||
setcc_gen_code[(int) LE] = CODE_FOR_sle;
|
||||
setcc_gen_code[(int) LEU] = CODE_FOR_sleu;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,28 @@
|
|||
/* Generated automatically by the program `genpeep'
|
||||
from the machine description file `md'. */
|
||||
|
||||
#include "config.h"
|
||||
#include "rtl.h"
|
||||
#include "regs.h"
|
||||
#include "output.h"
|
||||
#include "real.h"
|
||||
|
||||
extern rtx peep_operand[];
|
||||
|
||||
#define operands peep_operand
|
||||
|
||||
rtx
|
||||
peephole (ins1)
|
||||
rtx ins1;
|
||||
{
|
||||
rtx insn, x, pat;
|
||||
int i;
|
||||
|
||||
if (NEXT_INSN (ins1)
|
||||
&& GET_CODE (NEXT_INSN (ins1)) == BARRIER)
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rtx peep_operand[2];
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,46 @@
|
|||
/* Configuration for GNU C-compiler for Vax.
|
||||
Copyright (C) 1987 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
||||
GNU CC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GNU CC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GNU CC; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
/* #defines that need visibility everywhere. */
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
|
||||
/* target machine dependencies.
|
||||
tm.h is a symbolic link to the actual target specific file. */
|
||||
#include "tm.h"
|
||||
|
||||
/* This describes the machine the compiler is hosted on. */
|
||||
#define HOST_BITS_PER_CHAR 8
|
||||
#define HOST_BITS_PER_SHORT 16
|
||||
#define HOST_BITS_PER_INT 32
|
||||
#define HOST_BITS_PER_LONG 32
|
||||
#define HOST_BITS_PER_LONGLONG 64
|
||||
|
||||
/* Arguments to use with `exit'. */
|
||||
#define SUCCESS_EXIT_CODE 0
|
||||
#define FATAL_EXIT_CODE 33
|
||||
|
||||
#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
|
||||
#define memset gcc_memset
|
||||
#define memcmp(left,right,len) bcmp ((left),(right),(len))
|
||||
|
||||
/* If compiled with GNU C, use the built-in alloca */
|
||||
#ifdef __GNUC__
|
||||
#define alloca __builtin_alloca
|
||||
#endif
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/* Definitions of target machine for GNU compiler.
|
||||
PC532 with National 32532, running NetBSD 0.9 or later.
|
||||
Copyright (C) 1992 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
||||
GNU CC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
GNU CC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GNU CC; see the file COPYING. If not, write to
|
||||
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
|
||||
#include "ns32k/ns32k.h"
|
||||
|
||||
/* The NetBSD predefines ... */
|
||||
|
||||
#undef CPP_PREDEFINES
|
||||
#define CPP_PREDEFINES "-Dns32532 -Dpc532 -Dunix -D__NetBSD__ -Dns32k"
|
||||
|
||||
/* Compile for the floating point unit & 32532 by default;
|
||||
also presume SB is zero */
|
||||
|
||||
#define TARGET_DEFAULT 25
|
||||
|
||||
/* Write DBX debugging info for gdb to read */
|
||||
|
||||
#define DBX_DEBUGGING_INFO
|
||||
|
||||
/* Use the re-entrant and potentially faster method */
|
||||
|
||||
#undef PCC_STATIC_STRUCT_RETURN
|
||||
|
||||
/* 32-bit alignment for efficiency */
|
||||
#undef POINTER_BOUNDARY
|
||||
#define POINTER_BOUNDARY 32
|
||||
|
||||
/* 32-bit alignment for efficiency */
|
||||
#undef FUNCTION_BOUNDARY
|
||||
#define FUNCTION_BOUNDARY 32
|
||||
|
||||
/* 32532 spec says it can handle any alignment. Rumor from tm-ns32k.h
|
||||
tells this might not be actually true (but it's for 32032, perhaps
|
||||
National has fixed the bug for 32532). You might have to change this
|
||||
if the bug still exists. */
|
||||
|
||||
#undef STRICT_ALIGNMENT
|
||||
#define STRICT_ALIGNMENT 0
|
||||
|
||||
/* Use pc relative addressing whenever possible,
|
||||
it's more efficient than absolute (ns32k.c)
|
||||
You have to fix a bug in gas 1.38.1 to make this work with gas,
|
||||
patch available from jkp@cs.hut.fi. */
|
||||
|
||||
#define PC_RELATIVE
|
||||
|
||||
/* Operand of bsr or jsr should be just the address. */
|
||||
|
||||
#define CALL_MEMREF_IMPLICIT
|
||||
|
||||
/* movd insns may have floating point constant operands. */
|
||||
|
||||
#define MOVD_FLOAT_OK
|
||||
|
||||
/* Every address needs to use a base reg. */
|
||||
|
||||
#define BASE_REG_NEEDED
|
||||
|
||||
/* Don't default to pcc-struct-return, because gcc is the only compiler, and
|
||||
we want to retain compatibility with older gcc versions. */
|
||||
|
||||
#define DEFAULT_PCC_STRUCT_RETURN 0
|
||||
|
||||
/* Change the built-in type ideas ... */
|
||||
|
||||
#undef SIZE_TYPE
|
||||
#define SIZE_TYPE "unsigned int"
|
||||
|
||||
#undef PTRDIFF_TYPE
|
||||
#define PTRDIFF_TYPE "int"
|
||||
|
||||
#undef WCHAR_TYPE
|
||||
#define WCHAR_TYPE "short unsigned int"
|
||||
|
||||
#define WCHAR_UNSIGNED 1
|
||||
|
||||
#undef WCHAR_TYPE_SIZE
|
||||
#define WCHAR_TYPE_SIZE 16
|
||||
|
||||
/* NetBSD does have atexit. */
|
||||
|
||||
#define HAVE_ATEXIT
|
||||
|
||||
Loading…
Reference in New Issue