diff --git a/gnu/usr.bin/gcc2/arch/ns32k/Makefile b/gnu/usr.bin/gcc2/arch/ns32k/Makefile new file mode 100644 index 000000000000..f6243c75e6ca --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/Makefile @@ -0,0 +1,3 @@ +# $Id: Makefile,v 1.1 1994/03/10 21:11:39 phil Exp $ + +.include diff --git a/gnu/usr.bin/gcc2/arch/ns32k/aux-output.c b/gnu/usr.bin/gcc2/arch/ns32k/aux-output.c new file mode 100644 index 000000000000..eb47d9c9344f --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/aux-output.c @@ -0,0 +1,712 @@ +/* Subroutines for assembler code output on the NS32000. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Some output-actions in ns32k.md need these. */ +#include +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" + +#ifdef OSF_OS +int ns32k_num_files = 0; +#endif + +void +trace (s, s1, s2) + char *s, *s1, *s2; +{ + fprintf (stderr, s, s1, s2); +} + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ + +int +hard_regno_mode_ok (regno, mode) + int regno; + enum machine_mode mode; +{ + switch (mode) + { + case QImode: + case HImode: + case PSImode: + case SImode: + case PDImode: + case VOIDmode: + case BLKmode: + if (regno < 8 || regno == 16 || regno == 17) + return 1; + else + return 0; + + case DImode: + if (regno < 8 && (regno & 1) == 0) + return 1; + else + return 0; + + case SFmode: + case SCmode: + if (TARGET_32081) + { + if (regno < 16) + return 1; + else + return 0; + } + else + { + if (regno < 8) + return 1; + else + return 0; + } + + case DFmode: + case DCmode: + if ((regno & 1) == 0) + { + if (TARGET_32081) + { + if (regno < 16) + return 1; + else + return 0; + } + else + { + if (regno < 8) + return 1; + else + return 0; + } + } + else + return 0; + } + + /* Used to abort here, but simply saying "no" handles TImode + much better. */ + return 0; +} + +/* ADDRESS_COST calls this. This function is not optimal + for the 32032 & 32332, but it probably is better than + the default. */ + +int +calc_address_cost (operand) + rtx operand; +{ + int i; + int cost = 0; + + if (GET_CODE (operand) == MEM) + cost += 3; + if (GET_CODE (operand) == MULT) + cost += 2; +#if 0 + if (GET_CODE (operand) == REG) + cost += 1; /* not really, but the documentation + says different amount of registers + shouldn't return the same costs */ +#endif + switch (GET_CODE (operand)) + { + case REG: + case CONST: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case POST_DEC: + case PRE_DEC: + break; + case MULT: + case MEM: + case PLUS: + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++) + { + cost += calc_address_cost (XEXP (operand, i)); + } + default: + break; + } + return cost; +} + +/* Return the register class of a scratch register needed to copy IN into + or out of a register in CLASS in MODE. If it can be done directly, + NO_REGS is returned. */ + +enum reg_class +secondary_reload_class (class, mode, in) + enum reg_class class; + enum machine_mode mode; + rtx in; +{ + int regno = true_regnum (in); + + if (regno >= FIRST_PSEUDO_REGISTER) + regno = -1; + + /* We can place anything into GENERAL_REGS and can put GENERAL_REGS + into anything. */ + if (class == GENERAL_REGS || (regno >= 0 && regno < 8)) + return NO_REGS; + + /* Constants, memory, and FP registers can go into FP registers. */ + if ((regno == -1 || (regno >= 8 && regno < 16)) && (class == FLOAT_REGS)) + return NO_REGS; + +#if 0 /* This isn't strictly true (can't move fp to sp or vice versa), + so it's cleaner to use PREFERRED_RELOAD_CLASS + to make the right things happen. */ + if (regno >= 16 && class == GEN_AND_MEM_REGS) + return NO_REGS; +#endif + + /* Otherwise, we need GENERAL_REGS. */ + return GENERAL_REGS; +} +/* Generate the rtx that comes from an address expression in the md file */ +/* The expression to be build is BASE[INDEX:SCALE]. To recognize this, + scale must be converted from an exponent (from ASHIFT) to a + multiplier (for MULT). */ +rtx +gen_indexed_expr (base, index, scale) + rtx base, index, scale; +{ + rtx addr; + + /* This generates an illegal addressing mode, if BASE is + fp or sp. This is handled by PRINT_OPERAND_ADDRESS. */ + if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT) + base = gen_rtx (MEM, SImode, base); + addr = gen_rtx (MULT, SImode, index, + gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (scale))); + addr = gen_rtx (PLUS, SImode, base, addr); + return addr; +} + +/* Return 1 if OP is a valid operand of mode MODE. This + predicate rejects operands which do not have a mode + (such as CONST_INT which are VOIDmode). */ +int +reg_or_mem_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + return (GET_MODE (op) == mode + && (GET_CODE (op) == REG + || GET_CODE (op) == SUBREG + || GET_CODE (op) == MEM)); +} + +/* Return the best assembler insn template + for moving operands[1] into operands[0] as a fullword. */ + +static char * +singlemove_string (operands) + rtx *operands; +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) <= 7 + && INTVAL (operands[1]) >= -8) + return "movqd %1,%0"; + return "movd %1,%0"; +} + +char * +output_move_double (operands) + rtx *operands; +{ + enum anon1 { REGOP, OFFSOP, POPOP, CNSTOP, RNDOP } optype0, optype1; + rtx latehalf[2]; + + /* First classify both operands. */ + + if (REG_P (operands[0])) + optype0 = REGOP; + else if (offsettable_memref_p (operands[0])) + optype0 = OFFSOP; + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + optype0 = POPOP; + else + optype0 = RNDOP; + + if (REG_P (operands[1])) + optype1 = REGOP; + else if (CONSTANT_ADDRESS_P (operands[1]) + || GET_CODE (operands[1]) == CONST_DOUBLE) + optype1 = CNSTOP; + else if (offsettable_memref_p (operands[1])) + optype1 = OFFSOP; + else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) + optype1 = POPOP; + else + optype1 = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Abort if we get one, + because generating code for these cases is painful. */ + + if (optype0 == RNDOP || optype1 == RNDOP) + abort (); + + /* Ok, we can do one word at a time. + Normally we do the low-numbered word first, + but if either operand is autodecrementing then we + do the high-numbered word first. + + In either case, set up in LATEHALF the operands to use + for the high-numbered word and in some cases alter the + operands in OPERANDS to be suitable for the low-numbered word. */ + + if (optype0 == REGOP) + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + else if (optype0 == OFFSOP) + latehalf[0] = adj_offsettable_operand (operands[0], 4); + else + latehalf[0] = operands[0]; + + if (optype1 == REGOP) + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + else if (optype1 == OFFSOP) + latehalf[1] = adj_offsettable_operand (operands[1], 4); + else if (optype1 == CNSTOP) + { + if (CONSTANT_ADDRESS_P (operands[1])) + latehalf[1] = const0_rtx; + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + split_double (operands[1], &operands[1], &latehalf[1]); + } + else + latehalf[1] = operands[1]; + + /* If one or both operands autodecrementing, + do the two words, high-numbered first. */ + + if (optype0 == POPOP || optype1 == POPOP) + { + output_asm_insn (singlemove_string (latehalf), latehalf); + return singlemove_string (operands); + } + + /* Not autodecrementing. Do the two words, low-numbered first. */ + + output_asm_insn (singlemove_string (operands), operands); + + operands[0] = latehalf[0]; + operands[1] = latehalf[1]; + return singlemove_string (operands); +} + +int +check_reg (oper, reg) + rtx oper; + int reg; +{ + register int i; + + if (oper == 0) + return 0; + switch (GET_CODE(oper)) + { + case REG: + return (REGNO(oper) == reg) ? 1 : 0; + case MEM: + return check_reg(XEXP(oper, 0), reg); + case PLUS: + case MULT: + return check_reg(XEXP(oper, 0), reg) || check_reg(XEXP(oper, 1), reg); + } + return 0; +} + +/* PRINT_OPERAND is defined to call this function, + which is easier to debug than putting all the code in + a macro definition in ns32k.h. */ + +void +print_operand (file, x, code) + FILE *file; + rtx x; + char code; +{ + if (code == '$') + PUT_IMMEDIATE_PREFIX (file); + else if (code == '?') + PUT_EXTERNAL_PREFIX (file); + else if (GET_CODE (x) == REG) + fprintf (file, "%s", reg_names[REGNO (x)]); + else if (GET_CODE (x) == MEM) + { + rtx tmp = XEXP (x, 0); +#if ! (defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)) + if (GET_CODE (tmp) != CONST_INT) + { + char *out = XSTR (tmp, 0); + if (out[0] == '*') + { + PUT_ABSOLUTE_PREFIX (file); + fprintf (file, "%s", &out[1]); + } + else + ASM_OUTPUT_LABELREF (file, out); + } + else +#endif + output_address (XEXP (x, 0)); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != DImode) + { + if (GET_MODE (x) == DFmode) + { + union { double d; int i[2]; } u; + u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x); + PUT_IMMEDIATE_PREFIX(file); +#ifdef SEQUENT_ASM + /* Sequent likes it's floating point constants as integers */ + fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]); +#else +#ifdef ENCORE_ASM + fprintf (file, "0f%.20e", u.d); +#else + fprintf (file, "0d%.20e", u.d); +#endif +#endif + } + else + { + union { double d; int i[2]; } u; + u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x); + PUT_IMMEDIATE_PREFIX (file); +#ifdef SEQUENT_ASM + /* We have no way of winning if we can't get the bits + for a sequent floating point number. */ +#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT + abort (); +#endif + { + union { float f; long l; } uu; + uu.f = u.d; + fprintf (file, "0Fx%08x", uu.l); + } +#else + fprintf (file, "0f%.20e", u.d); +#endif + } + } + else + { +#ifdef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC + if (GET_CODE (x) == CONST_INT) +#endif + PUT_IMMEDIATE_PREFIX (file); + output_addr_const (file, x); + } +} + +/* PRINT_OPERAND_ADDRESS is defined to call this function, + which is easier to debug than putting all the code in + a macro definition in ns32k.h . */ + +/* Completely rewritten to get this to work with Gas for PC532 Mach. + This function didn't work and I just wasn't able (nor very willing) to + figure out how it worked. + 90-11-25 Tatu Yl|nen */ + +print_operand_address (file, addr) + register FILE *file; + register rtx addr; +{ + static char scales[] = { 'b', 'w', 'd', 0, 'q', }; + rtx offset, base, indexexp, tmp; + int scale; + + if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC) + { + fprintf (file, "tos"); + return; + } + + offset = NULL; + base = NULL; + indexexp = NULL; + while (addr != NULL) + { + if (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == PLUS) + { + tmp = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else + { + tmp = XEXP (addr,0); + addr = XEXP (addr,1); + } + } + else + { + tmp = addr; + addr = NULL; + } + switch (GET_CODE (tmp)) + { + case PLUS: + abort (); + case MEM: + if (base) + { + indexexp = base; + base = tmp; + } + else + base = tmp; + break; + case REG: + if (REGNO (tmp) < 8) + if (base) + { + indexexp = tmp; + } + else + base = tmp; + else + if (base) + { + indexexp = base; + base = tmp; + } + else + base = tmp; + break; + case MULT: + indexexp = tmp; + break; + case CONST: + case CONST_INT: + case SYMBOL_REF: + case LABEL_REF: + if (offset) + offset = gen_rtx (PLUS, SImode, tmp, offset); + else + offset = tmp; + break; + default: + abort (); + } + } + if (! offset) + offset = const0_rtx; + +#ifdef INDEX_RATHER_THAN_BASE + /* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix. */ + if (base && !indexexp && GET_CODE (base) == REG + && REG_OK_FOR_INDEX_P (base)) + { + indexexp = base; + base = 0; + } +#endif + + /* now, offset, base and indexexp are set */ + if (! base) + { +#if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC) + if (GET_CODE (offset) == CONST_INT) +/* if (! (GET_CODE (offset) == LABEL_REF + || GET_CODE (offset) == SYMBOL_REF)) */ +#endif + PUT_ABSOLUTE_PREFIX (file); + } + + output_addr_const (file, offset); + if (base) /* base can be (REG ...) or (MEM ...) */ + switch (GET_CODE (base)) + { + /* now we must output base. Possible alternatives are: + (rN) (REG ...) + (sp) (REG ...) + (fp) (REG ...) + (pc) (REG ...) used for SYMBOL_REF and LABEL_REF, output + (disp(fp)) (MEM ...) just before possible [rX:y] + (disp(sp)) (MEM ...) + (disp(sb)) (MEM ...) + */ + case REG: + fprintf (file, "(%s)", reg_names[REGNO (base)]); + break; + case MEM: + addr = XEXP(base,0); + base = NULL; + offset = NULL; + while (addr != NULL) + { + if (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == PLUS) + { + tmp = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else + { + tmp = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + } + else + { + tmp = addr; + addr = NULL; + } + switch (GET_CODE (tmp)) + { + case REG: + base = tmp; + break; + case CONST: + case CONST_INT: + case SYMBOL_REF: + case LABEL_REF: + if (offset) + offset = gen_rtx (PLUS, SImode, tmp, offset); + else + offset = tmp; + break; + default: + abort (); + } + } + if (! offset) + offset = const0_rtx; + fprintf (file, "("); + output_addr_const (file, offset); + if (base) + fprintf (file, "(%s)", reg_names[REGNO (base)]); +#ifdef BASE_REG_NEEDED + else if (TARGET_SB) + fprintf (file, "(sb)"); + else + abort (); +#endif + fprintf (file, ")"); + break; + + default: + abort (); + } +#ifdef PC_RELATIVE + else /* no base */ + if (GET_CODE (offset) == LABEL_REF || GET_CODE (offset) == SYMBOL_REF) + fprintf (file, "(pc)"); +#endif +#ifdef BASE_REG_NEEDED /* this is defined if the assembler always + needs a base register */ + else if (TARGET_SB) + fprintf (file, "(sb)"); + else + abort (); +#endif + /* now print index if we have one */ + if (indexexp) + { + if (GET_CODE (indexexp) == MULT) + { + scale = INTVAL (XEXP (indexexp, 1)) >> 1; + indexexp = XEXP (indexexp, 0); + } + else + scale = 0; + if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= 8) + abort (); + +#ifdef UTEK_ASM + fprintf (file, "[%c`%s]", + scales[scale], + reg_names[REGNO (indexexp)]); +#else + fprintf (file, "[%s:%c]", + reg_names[REGNO (indexexp)], + scales[scale]); +#endif + } +} + +/* National 32032 shifting is so bad that we can get + better performance in many common cases by using other + techniques. */ +char * +output_shift_insn (operands) + rtx *operands; +{ + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 3) + if (GET_CODE (operands[0]) == REG) + { + if (GET_CODE (operands[1]) == REG) + { + if (REGNO (operands[0]) == REGNO (operands[1])) + { + if (operands[2] == const1_rtx) + return "addd %0,%0"; + else if (INTVAL (operands[2]) == 2) + return "addd %0,%0\n\taddd %0,%0"; + } + if (operands[2] == const1_rtx) + return "movd %1,%0\n\taddd %0,%0"; + + operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]); + return "addr %a1,%0"; + } + if (operands[2] == const1_rtx) + return "movd %1,%0\n\taddd %0,%0"; + } + else if (GET_CODE (operands[1]) == REG) + { + operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]); + return "addr %a1,%0"; + } + else if (INTVAL (operands[2]) == 1 + && GET_CODE (operands[1]) == MEM + && rtx_equal_p (operands [0], operands[1])) + { + rtx temp = XEXP (operands[1], 0); + + if (GET_CODE (temp) == REG + || (GET_CODE (temp) == PLUS + && GET_CODE (XEXP (temp, 0)) == REG + && GET_CODE (XEXP (temp, 1)) == CONST_INT)) + return "addd %0,%0"; + } + else return "ashd %2,%0"; + return "ashd %2,%0"; +} diff --git a/gnu/usr.bin/gcc2/arch/ns32k/config.h b/gnu/usr.bin/gcc2/arch/ns32k/config.h new file mode 100644 index 000000000000..0342169ebb6b --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/config.h @@ -0,0 +1,46 @@ +/* Configuration for GNU C-compiler for Vax. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +#define memcpy(src,dst,len) bcopy ((dst),(src),(len)) +#define memset gcc_memset +#define memcmp(left,right,len) bcmp ((left),(right),(len)) + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +#define alloca __builtin_alloca +#endif diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-attr.h b/gnu/usr.bin/gcc2/arch/ns32k/insn-attr.h new file mode 100644 index 000000000000..5fe9a2f80012 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-attr.h @@ -0,0 +1,19 @@ +/* Generated automatically by the program `genattr' +from the machine description file `md'. */ + +#ifndef PROTO +#if defined (USE_PROTOTYPES) ? USE_PROTOTYPES : defined (__STDC__) +#define PROTO(ARGS) ARGS +#else +#define PROTO(ARGS) () +#endif +#endif +#define HAVE_ATTR_alternative +#define get_attr_alternative(insn) which_alternative + +#define ATTR_FLAG_forward 0x1 +#define ATTR_FLAG_backward 0x2 +#define ATTR_FLAG_likely 0x4 +#define ATTR_FLAG_very_likely 0x8 +#define ATTR_FLAG_unlikely 0x10 +#define ATTR_FLAG_very_unlikely 0x20 diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-attrtab.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-attrtab.c new file mode 100644 index 000000000000..0e86d1f4c35a --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-attrtab.c @@ -0,0 +1,14 @@ +/* Generated automatically by the program `genattrtab' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "regs.h" +#include "real.h" +#include "output.h" +#include "insn-attr.h" + +#define operands recog_operand + diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-codes.h b/gnu/usr.bin/gcc2/arch/ns32k/insn-codes.h new file mode 100644 index 000000000000..8099416cc3d8 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-codes.h @@ -0,0 +1,165 @@ +/* Generated automatically by the program `gencodes' +from the machine description file `md'. */ + +#ifndef MAX_INSN_CODE + +enum insn_code { + CODE_FOR_tstsi = 0, + CODE_FOR_tsthi = 1, + CODE_FOR_tstqi = 2, + CODE_FOR_tstdf = 3, + CODE_FOR_tstsf = 4, + CODE_FOR_cmpsi = 5, + CODE_FOR_cmphi = 6, + CODE_FOR_cmpqi = 7, + CODE_FOR_cmpdf = 8, + CODE_FOR_cmpsf = 9, + CODE_FOR_movdf = 10, + CODE_FOR_movsf = 11, + CODE_FOR_movdi = 13, + CODE_FOR_movsi = 15, + CODE_FOR_movhi = 16, + CODE_FOR_movstricthi = 17, + CODE_FOR_movqi = 18, + CODE_FOR_movstrictqi = 19, + CODE_FOR_movstrsi = 20, + CODE_FOR_movstrsi1 = 21, + CODE_FOR_truncsiqi2 = 22, + CODE_FOR_truncsihi2 = 23, + CODE_FOR_trunchiqi2 = 24, + CODE_FOR_extendhisi2 = 25, + CODE_FOR_extendqihi2 = 26, + CODE_FOR_extendqisi2 = 27, + CODE_FOR_extendsfdf2 = 28, + CODE_FOR_truncdfsf2 = 29, + CODE_FOR_zero_extendhisi2 = 30, + CODE_FOR_zero_extendqihi2 = 31, + CODE_FOR_zero_extendqisi2 = 32, + CODE_FOR_floatsisf2 = 33, + CODE_FOR_floatsidf2 = 34, + CODE_FOR_floathisf2 = 35, + CODE_FOR_floathidf2 = 36, + CODE_FOR_floatqisf2 = 37, + CODE_FOR_fixsfqi2 = 38, + CODE_FOR_fixsfhi2 = 39, + CODE_FOR_fixsfsi2 = 40, + CODE_FOR_fixdfqi2 = 41, + CODE_FOR_fixdfhi2 = 42, + CODE_FOR_fixdfsi2 = 43, + CODE_FOR_fixunssfqi2 = 44, + CODE_FOR_fixunssfhi2 = 45, + CODE_FOR_fixunssfsi2 = 46, + CODE_FOR_fixunsdfqi2 = 47, + CODE_FOR_fixunsdfhi2 = 48, + CODE_FOR_fixunsdfsi2 = 49, + CODE_FOR_fix_truncsfqi2 = 50, + CODE_FOR_fix_truncsfhi2 = 51, + CODE_FOR_fix_truncsfsi2 = 52, + CODE_FOR_fix_truncdfqi2 = 53, + CODE_FOR_fix_truncdfhi2 = 54, + CODE_FOR_fix_truncdfsi2 = 55, + CODE_FOR_adddf3 = 56, + CODE_FOR_addsf3 = 57, + CODE_FOR_addsi3 = 61, + CODE_FOR_addhi3 = 62, + CODE_FOR_addqi3 = 64, + CODE_FOR_subdf3 = 66, + CODE_FOR_subsf3 = 67, + CODE_FOR_subsi3 = 69, + CODE_FOR_subhi3 = 70, + CODE_FOR_subqi3 = 72, + CODE_FOR_muldf3 = 74, + CODE_FOR_mulsf3 = 75, + CODE_FOR_mulsi3 = 76, + CODE_FOR_mulhi3 = 77, + CODE_FOR_mulqi3 = 78, + CODE_FOR_umulsidi3 = 79, + CODE_FOR_divdf3 = 80, + CODE_FOR_divsf3 = 81, + CODE_FOR_divsi3 = 82, + CODE_FOR_divhi3 = 83, + CODE_FOR_divqi3 = 84, + CODE_FOR_udivsi3 = 85, + CODE_FOR_udivhi3 = 86, + CODE_FOR_udivqi3 = 87, + CODE_FOR_modsi3 = 88, + CODE_FOR_modhi3 = 89, + CODE_FOR_modqi3 = 90, + CODE_FOR_umodsi3 = 91, + CODE_FOR_umodhi3 = 92, + CODE_FOR_umodqi3 = 93, + CODE_FOR_andsi3 = 94, + CODE_FOR_andhi3 = 95, + CODE_FOR_andqi3 = 96, + CODE_FOR_iorsi3 = 100, + CODE_FOR_iorhi3 = 101, + CODE_FOR_iorqi3 = 102, + CODE_FOR_xorsi3 = 103, + CODE_FOR_xorhi3 = 104, + CODE_FOR_xorqi3 = 105, + CODE_FOR_negdf2 = 106, + CODE_FOR_negsf2 = 107, + CODE_FOR_negsi2 = 108, + CODE_FOR_neghi2 = 109, + CODE_FOR_negqi2 = 110, + CODE_FOR_one_cmplsi2 = 111, + CODE_FOR_one_cmplhi2 = 112, + CODE_FOR_one_cmplqi2 = 113, + CODE_FOR_ashlsi3 = 114, + CODE_FOR_ashlhi3 = 115, + CODE_FOR_ashlqi3 = 116, + CODE_FOR_ashrsi3 = 117, + CODE_FOR_ashrhi3 = 120, + CODE_FOR_ashrqi3 = 123, + CODE_FOR_lshlsi3 = 126, + CODE_FOR_lshlhi3 = 127, + CODE_FOR_lshlqi3 = 128, + CODE_FOR_lshrsi3 = 129, + CODE_FOR_lshrhi3 = 132, + CODE_FOR_lshrqi3 = 135, + CODE_FOR_rotlsi3 = 138, + CODE_FOR_rotlhi3 = 139, + CODE_FOR_rotlqi3 = 140, + CODE_FOR_rotrsi3 = 141, + CODE_FOR_rotrhi3 = 144, + CODE_FOR_rotrqi3 = 147, + CODE_FOR_extzv = 158, + CODE_FOR_insv = 161, + CODE_FOR_jump = 162, + CODE_FOR_beq = 163, + CODE_FOR_bne = 164, + CODE_FOR_bgt = 165, + CODE_FOR_bgtu = 166, + CODE_FOR_blt = 167, + CODE_FOR_bltu = 168, + CODE_FOR_bge = 169, + CODE_FOR_bgeu = 170, + CODE_FOR_ble = 171, + CODE_FOR_bleu = 172, + CODE_FOR_call = 185, + CODE_FOR_call_value = 186, + CODE_FOR_untyped_call = 187, + CODE_FOR_blockage = 188, + CODE_FOR_return = 189, + CODE_FOR_abssf2 = 190, + CODE_FOR_absdf2 = 191, + CODE_FOR_abssi2 = 192, + CODE_FOR_abshi2 = 193, + CODE_FOR_absqi2 = 194, + CODE_FOR_nop = 195, + CODE_FOR_indirect_jump = 196, + CODE_FOR_tablejump = 197, + CODE_FOR_seq = 198, + CODE_FOR_sne = 201, + CODE_FOR_sgt = 204, + CODE_FOR_sgtu = 207, + CODE_FOR_slt = 210, + CODE_FOR_sltu = 213, + CODE_FOR_sge = 216, + CODE_FOR_sgeu = 219, + CODE_FOR_sle = 222, + CODE_FOR_sleu = 225, + CODE_FOR_nothing }; + +#define MAX_INSN_CODE ((int) CODE_FOR_nothing) +#endif /* MAX_INSN_CODE */ diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-config.h b/gnu/usr.bin/gcc2/arch/ns32k/insn-config.h new file mode 100644 index 000000000000..7dba8866f62f --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-config.h @@ -0,0 +1,12 @@ +/* Generated automatically by the program `genconfig' +from the machine description file `md'. */ + + +#define MAX_RECOG_OPERANDS 10 + +#define MAX_DUP_OPERANDS 3 +#ifndef MAX_INSNS_PER_SPLIT +#define MAX_INSNS_PER_SPLIT 1 +#endif +#define REGISTER_CONSTRAINTS +#define HAVE_cc0 diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-emit.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-emit.c new file mode 100644 index 000000000000..5a780385174f --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-emit.c @@ -0,0 +1,1555 @@ +/* Generated automatically by the program `genemit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "expr.h" +#include "real.h" +#include "output.h" +#include "insn-config.h" + +#include "insn-flags.h" + +#include "insn-codes.h" + +extern char *insn_operand_constraint[][MAX_RECOG_OPERANDS]; + +extern rtx recog_operand[]; +#define operands emit_operand + +#define FAIL goto _fail + +#define DONE goto _done + +rtx +gen_tstsi (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tsthi (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstqi (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstdf (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_tstsf (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, operand0); +} + +rtx +gen_cmpsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmphi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_cmpsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, cc0_rtx, gen_rtx (COMPARE, VOIDmode, operand0, operand1)); +} + +rtx +gen_movdf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movsf (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movdi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movsi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movhi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstricthi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, operand1); +} + +rtx +gen_movstrictqi (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (STRICT_LOW_PART, VOIDmode, operand0), operand1); +} + +rtx +gen_movstrsi (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + rtx operands[4]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + operands[3] = operand3; + + emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2])); + DONE; + + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + operand3 = operands[3]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); + emit_insn (gen_rtx (USE, VOIDmode, operand2)); + emit (operand3); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_movstrsi1 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5, + gen_rtx (SET, VOIDmode, operand0, operand1), + gen_rtx (USE, VOIDmode, operand2), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 0)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 1)), + gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 2)))); +} + +rtx +gen_truncsiqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, QImode, operand1)); +} + +rtx +gen_truncsihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, HImode, operand1)); +} + +rtx +gen_trunchiqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (TRUNCATE, QImode, operand1)); +} + +rtx +gen_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, HImode, operand1)); +} + +rtx +gen_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (SIGN_EXTEND, SImode, operand1)); +} + +rtx +gen_extendsfdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_EXTEND, DFmode, operand1)); +} + +rtx +gen_truncdfsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT_TRUNCATE, SFmode, operand1)); +} + +rtx +gen_zero_extendhisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, SImode, operand1)); +} + +rtx +gen_zero_extendqihi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, HImode, operand1)); +} + +rtx +gen_zero_extendqisi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTEND, SImode, operand1)); +} + +rtx +gen_floatsisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floatsidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_floathisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_floathidf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, DFmode, operand1)); +} + +rtx +gen_floatqisf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FLOAT, SFmode, operand1)); +} + +rtx +gen_fixsfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, gen_rtx (FIX, SFmode, operand1))); +} + +rtx +gen_fixsfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, gen_rtx (FIX, SFmode, operand1))); +} + +rtx +gen_fixsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, SFmode, operand1))); +} + +rtx +gen_fixdfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, gen_rtx (FIX, DFmode, operand1))); +} + +rtx +gen_fixdfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, gen_rtx (FIX, DFmode, operand1))); +} + +rtx +gen_fixdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, gen_rtx (FIX, DFmode, operand1))); +} + +rtx +gen_fixunssfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSIGNED_FIX, QImode, gen_rtx (FIX, SFmode, operand1))); +} + +rtx +gen_fixunssfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSIGNED_FIX, HImode, gen_rtx (FIX, SFmode, operand1))); +} + +rtx +gen_fixunssfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSIGNED_FIX, SImode, gen_rtx (FIX, SFmode, operand1))); +} + +rtx +gen_fixunsdfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSIGNED_FIX, QImode, gen_rtx (FIX, DFmode, operand1))); +} + +rtx +gen_fixunsdfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSIGNED_FIX, HImode, gen_rtx (FIX, DFmode, operand1))); +} + +rtx +gen_fixunsdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UNSIGNED_FIX, SImode, gen_rtx (FIX, DFmode, operand1))); +} + +rtx +gen_fix_truncsfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, operand1)); +} + +rtx +gen_fix_truncsfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, operand1)); +} + +rtx +gen_fix_truncsfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, operand1)); +} + +rtx +gen_fix_truncdfqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, QImode, operand1)); +} + +rtx +gen_fix_truncdfhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, HImode, operand1)); +} + +rtx +gen_fix_truncdfsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (FIX, SImode, operand1)); +} + +rtx +gen_adddf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, DFmode, operand1, operand2)); +} + +rtx +gen_addsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SFmode, operand1, operand2)); +} + +rtx +gen_addsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, SImode, operand1, operand2)); +} + +rtx +gen_addhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, HImode, operand1, operand2)); +} + +rtx +gen_addqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (PLUS, QImode, operand1, operand2)); +} + +rtx +gen_subdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, DFmode, operand1, operand2)); +} + +rtx +gen_subsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SFmode, operand1, operand2)); +} + +rtx +gen_subsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, SImode, operand1, operand2)); +} + +rtx +gen_subhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, HImode, operand1, operand2)); +} + +rtx +gen_subqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MINUS, QImode, operand1, operand2)); +} + +rtx +gen_muldf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, DFmode, operand1, operand2)); +} + +rtx +gen_mulsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SFmode, operand1, operand2)); +} + +rtx +gen_mulsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, SImode, operand1, operand2)); +} + +rtx +gen_mulhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, HImode, operand1, operand2)); +} + +rtx +gen_mulqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, QImode, operand1, operand2)); +} + +rtx +gen_umulsidi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MULT, DImode, gen_rtx (ZERO_EXTEND, DImode, operand1), gen_rtx (ZERO_EXTEND, DImode, operand2))); +} + +rtx +gen_divdf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, DFmode, operand1, operand2)); +} + +rtx +gen_divsf3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SFmode, operand1, operand2)); +} + +rtx +gen_divsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, SImode, operand1, operand2)); +} + +rtx +gen_divhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, HImode, operand1, operand2)); +} + +rtx +gen_divqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (DIV, QImode, operand1, operand2)); +} + +rtx +gen_udivsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, SImode, gen_rtx (SUBREG, SImode, operand1, 0), operand2)); +} + +rtx +gen_udivhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, HImode, gen_rtx (SUBREG, HImode, operand1, 0), operand2)); +} + +rtx +gen_udivqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UDIV, QImode, gen_rtx (SUBREG, QImode, operand1, 0), operand2)); +} + +rtx +gen_modsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MOD, SImode, operand1, operand2)); +} + +rtx +gen_modhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MOD, HImode, operand1, operand2)); +} + +rtx +gen_modqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (MOD, QImode, operand1, operand2)); +} + +rtx +gen_umodsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UMOD, SImode, gen_rtx (SUBREG, SImode, operand1, 0), operand2)); +} + +rtx +gen_umodhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UMOD, HImode, gen_rtx (SUBREG, HImode, operand1, 0), operand2)); +} + +rtx +gen_umodqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (UMOD, QImode, gen_rtx (SUBREG, QImode, operand1, 0), operand2)); +} + +rtx +gen_andsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, SImode, operand1, operand2)); +} + +rtx +gen_andhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, HImode, operand1, operand2)); +} + +rtx +gen_andqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (AND, QImode, operand1, operand2)); +} + +rtx +gen_iorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, SImode, operand1, operand2)); +} + +rtx +gen_iorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, HImode, operand1, operand2)); +} + +rtx +gen_iorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (IOR, QImode, operand1, operand2)); +} + +rtx +gen_xorsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, SImode, operand1, operand2)); +} + +rtx +gen_xorhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, HImode, operand1, operand2)); +} + +rtx +gen_xorqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (XOR, QImode, operand1, operand2)); +} + +rtx +gen_negdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, DFmode, operand1)); +} + +rtx +gen_negsf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SFmode, operand1)); +} + +rtx +gen_negsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, SImode, operand1)); +} + +rtx +gen_neghi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, HImode, operand1)); +} + +rtx +gen_negqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NEG, QImode, operand1)); +} + +rtx +gen_one_cmplsi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, SImode, operand1)); +} + +rtx +gen_one_cmplhi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, HImode, operand1)); +} + +rtx +gen_one_cmplqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NOT, QImode, operand1)); +} + +rtx +gen_ashlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, SImode, operand1, operand2)); +} + +rtx +gen_ashlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, HImode, operand1, operand2)); +} + +rtx +gen_ashlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFT, QImode, operand1, operand2)); +} + +rtx +gen_ashrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, SImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ashrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, HImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_ashrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ASHIFTRT, QImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_lshlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFT, SImode, operand1, operand2)); +} + +rtx +gen_lshlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFT, HImode, operand1, operand2)); +} + +rtx +gen_lshlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFT, QImode, operand1, operand2)); +} + +rtx +gen_lshrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, SImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_lshrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, HImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_lshrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (LSHIFTRT, QImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_rotlsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, SImode, operand1, operand2)); +} + +rtx +gen_rotlhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, HImode, operand1, operand2)); +} + +rtx +gen_rotlqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATE, QImode, operand1, operand2)); +} + +rtx +gen_rotrsi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, SImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_rotrhi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, HImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_rotrqi3 (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_insn (gen_rtx (SET, VOIDmode, operand0, gen_rtx (ROTATERT, QImode, operand1, operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_extzv (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ZERO_EXTRACT, SImode, operand1, operand2, operand3)); +} + +rtx +gen_insv (operand0, operand1, operand2, operand3) + rtx operand0; + rtx operand1; + rtx operand2; + rtx operand3; +{ + return gen_rtx (SET, VOIDmode, gen_rtx (ZERO_EXTRACT, SImode, operand0, operand1, operand2), operand3); +} + +rtx +gen_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, operand0)); +} + +rtx +gen_beq (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (EQ, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bne (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (NE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bgt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bgtu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_blt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LT, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bltu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LTU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bge (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bgeu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (GEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_ble (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LE, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_bleu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (IF_THEN_ELSE, VOIDmode, gen_rtx (LEU, VOIDmode, cc0_rtx, const0_rtx), gen_rtx (LABEL_REF, VOIDmode, operand0), pc_rtx)); +} + +rtx +gen_call (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (CALL, VOIDmode, operand0, operand1); +} + +rtx +gen_call_value (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (CALL, VOIDmode, operand1, operand2)); +} + +rtx +gen_untyped_call (operand0, operand1, operand2) + rtx operand0; + rtx operand1; + rtx operand2; +{ + rtx operands[3]; + rtx _val = 0; + start_sequence (); + operands[0] = operand0; + operands[1] = operand1; + operands[2] = operand2; + +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +} + operand0 = operands[0]; + operand1 = operands[1]; + operand2 = operands[2]; + emit_call_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (3, + gen_rtx (CALL, VOIDmode, operand0, const0_rtx), + operand1, + operand2))); + _done: + _val = gen_sequence (); + _fail: + end_sequence (); + return _val; +} + +rtx +gen_blockage () +{ + return gen_rtx (UNSPEC_VOLATILE, VOIDmode, gen_rtvec (1, + const0_rtx), 0); +} + +rtx +gen_return () +{ + return gen_rtx (RETURN, VOIDmode); +} + +rtx +gen_abssf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, SFmode, operand1)); +} + +rtx +gen_absdf2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, DFmode, operand1)); +} + +rtx +gen_abssi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, SImode, operand1)); +} + +rtx +gen_abshi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, HImode, operand1)); +} + +rtx +gen_absqi2 (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (ABS, QImode, operand1)); +} + +rtx +gen_nop () +{ + return const0_rtx; +} + +rtx +gen_indirect_jump (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, pc_rtx, operand0); +} + +rtx +gen_tablejump (operand0, operand1) + rtx operand0; + rtx operand1; +{ + return gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2, + gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (PLUS, SImode, pc_rtx, operand0)), + gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, operand1)))); +} + +rtx +gen_seq (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (EQ, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sne (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (NE, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sgt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GT, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sgtu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GTU, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_slt (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LT, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sltu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LTU, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sge (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GE, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sgeu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (GEU, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sle (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LE, SImode, cc0_rtx, const0_rtx)); +} + +rtx +gen_sleu (operand0) + rtx operand0; +{ + return gen_rtx (SET, VOIDmode, operand0, gen_rtx (LEU, SImode, cc0_rtx, const0_rtx)); +} + + + +void +add_clobbers (pattern, insn_code_number) + rtx pattern; + int insn_code_number; +{ + int i; + + switch (insn_code_number) + { + case 21: + XVECEXP (pattern, 0, 2) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 0)); + XVECEXP (pattern, 0, 3) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 1)); + XVECEXP (pattern, 0, 4) = gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 2)); + break; + + default: + abort (); + } +} diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-extract.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-extract.c new file mode 100644 index 000000000000..31e40fd77474 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-extract.c @@ -0,0 +1,381 @@ +/* Generated automatically by the program `genextract' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" + +static rtx junk; +extern rtx recog_operand[]; +extern rtx *recog_operand_loc[]; +extern rtx *recog_dup_loc[]; +extern char recog_dup_num[]; +extern +#ifdef __GNUC__ +__volatile__ +#endif +void fatal_insn_not_found (); + +void +insn_extract (insn) + rtx insn; +{ + register rtx *ro = recog_operand; + register rtx **ro_loc = recog_operand_loc; + rtx pat = PATTERN (insn); + switch (INSN_CODE (insn)) + { + case -1: + fatal_insn_not_found (insn); + + case 227: + case 226: + case 225: + case 224: + case 223: + case 222: + case 221: + case 220: + case 219: + case 218: + case 217: + case 216: + case 215: + case 214: + case 213: + case 212: + case 211: + case 210: + case 209: + case 208: + case 207: + case 206: + case 205: + case 204: + case 203: + case 202: + case 201: + case 200: + case 199: + case 198: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + break; + + case 197: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0)); + break; + + case 195: + case 189: + case 188: + break; + + case 184: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + ro[3] = *(ro_loc[3] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 0; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[1] = 0; + break; + + case 183: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 1), 0)); + recog_dup_loc[0] = &XEXP (XVECEXP (pat, 0, 1), 0); + recog_dup_num[0] = 0; + recog_dup_loc[1] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 0); + recog_dup_num[1] = 0; + recog_dup_loc[2] = &XEXP (XEXP (XVECEXP (pat, 0, 1), 1), 1); + recog_dup_num[2] = 1; + break; + + case 182: + case 181: + case 180: + case 179: + case 178: + case 177: + case 176: + case 175: + case 174: + case 173: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 2), 0)); + break; + + case 172: + case 171: + case 170: + case 169: + case 168: + case 167: + case 166: + case 165: + case 164: + case 163: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 162: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 161: + case 160: + case 159: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 0), 2)); + ro[3] = *(ro_loc[3] = &XEXP (pat, 1)); + break; + + case 158: + case 157: + case 156: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + ro[3] = *(ro_loc[3] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 155: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 2)); + break; + + case 154: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (XEXP (pat, 1), 0), 0), 1)); + recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 1); + recog_dup_num[0] = 0; + break; + + case 153: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 1)); + recog_dup_loc[0] = &XEXP (XEXP (pat, 1), 1); + recog_dup_num[0] = 0; + break; + + case 152: + case 151: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 0), 2)); + break; + + case 149: + case 146: + case 143: + case 137: + case 134: + case 131: + case 125: + case 122: + case 119: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 99: + case 98: + case 97: + case 93: + case 92: + case 91: + case 87: + case 86: + case 85: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 79: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (XEXP (pat, 1), 1), 0)); + break; + + case 73: + case 71: + case 65: + case 63: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 60: + case 59: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 68: + case 58: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 186: + case 148: + case 145: + case 142: + case 140: + case 139: + case 138: + case 136: + case 133: + case 130: + case 128: + case 127: + case 126: + case 124: + case 121: + case 118: + case 116: + case 115: + case 114: + case 105: + case 104: + case 103: + case 102: + case 101: + case 100: + case 96: + case 95: + case 94: + case 90: + case 89: + case 88: + case 84: + case 83: + case 82: + case 81: + case 80: + case 78: + case 77: + case 76: + case 75: + case 74: + case 72: + case 70: + case 69: + case 67: + case 66: + case 64: + case 62: + case 61: + case 57: + case 56: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + ro[2] = *(ro_loc[2] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 49: + case 48: + case 47: + case 46: + case 45: + case 44: + case 43: + case 42: + case 41: + case 40: + case 39: + case 38: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (XEXP (pat, 1), 0), 0)); + break; + + case 194: + case 193: + case 192: + case 191: + case 190: + case 113: + case 112: + case 111: + case 110: + case 109: + case 108: + case 107: + case 106: + case 55: + case 54: + case 53: + case 52: + case 51: + case 50: + case 37: + case 36: + case 35: + case 34: + case 33: + case 32: + case 31: + case 30: + case 29: + case 28: + case 27: + case 26: + case 25: + case 24: + case 23: + case 22: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 0)); + break; + + case 21: + ro[0] = *(ro_loc[0] = &XEXP (XVECEXP (pat, 0, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XVECEXP (pat, 0, 0), 1)); + ro[2] = *(ro_loc[2] = &XEXP (XVECEXP (pat, 0, 1), 0)); + break; + + case 19: + case 17: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 0), 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 185: + case 150: + case 18: + case 16: + case 15: + case 13: + case 12: + case 11: + case 10: + ro[0] = *(ro_loc[0] = &XEXP (pat, 0)); + ro[1] = *(ro_loc[1] = &XEXP (pat, 1)); + break; + + case 9: + case 8: + case 7: + case 6: + case 5: + ro[0] = *(ro_loc[0] = &XEXP (XEXP (pat, 1), 0)); + ro[1] = *(ro_loc[1] = &XEXP (XEXP (pat, 1), 1)); + break; + + case 196: + case 14: + case 4: + case 3: + case 2: + case 1: + case 0: + ro[0] = *(ro_loc[0] = &XEXP (pat, 1)); + break; + + default: + abort (); + } +} diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-flags.h b/gnu/usr.bin/gcc2/arch/ns32k/insn-flags.h new file mode 100644 index 000000000000..dba124f93f65 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-flags.h @@ -0,0 +1,480 @@ +/* Generated automatically by the program `genflags' +from the machine description file `md'. */ + +#define HAVE_tstsi 1 +#define HAVE_tsthi 1 +#define HAVE_tstqi 1 +#define HAVE_tstdf (TARGET_32081) +#define HAVE_tstsf (TARGET_32081) +#define HAVE_cmpsi 1 +#define HAVE_cmphi 1 +#define HAVE_cmpqi 1 +#define HAVE_cmpdf (TARGET_32081) +#define HAVE_cmpsf (TARGET_32081) +#define HAVE_movdf 1 +#define HAVE_movsf 1 +#define HAVE_movdi 1 +#define HAVE_movsi 1 +#define HAVE_movhi 1 +#define HAVE_movstricthi 1 +#define HAVE_movqi 1 +#define HAVE_movstrictqi 1 +#define HAVE_movstrsi 1 +#define HAVE_movstrsi1 1 +#define HAVE_truncsiqi2 1 +#define HAVE_truncsihi2 1 +#define HAVE_trunchiqi2 1 +#define HAVE_extendhisi2 1 +#define HAVE_extendqihi2 1 +#define HAVE_extendqisi2 1 +#define HAVE_extendsfdf2 (TARGET_32081) +#define HAVE_truncdfsf2 (TARGET_32081) +#define HAVE_zero_extendhisi2 1 +#define HAVE_zero_extendqihi2 1 +#define HAVE_zero_extendqisi2 1 +#define HAVE_floatsisf2 (TARGET_32081) +#define HAVE_floatsidf2 (TARGET_32081) +#define HAVE_floathisf2 (TARGET_32081) +#define HAVE_floathidf2 (TARGET_32081) +#define HAVE_floatqisf2 (TARGET_32081) +#define HAVE_fixsfqi2 (TARGET_32081) +#define HAVE_fixsfhi2 (TARGET_32081) +#define HAVE_fixsfsi2 (TARGET_32081) +#define HAVE_fixdfqi2 (TARGET_32081) +#define HAVE_fixdfhi2 (TARGET_32081) +#define HAVE_fixdfsi2 (TARGET_32081) +#define HAVE_fixunssfqi2 (TARGET_32081) +#define HAVE_fixunssfhi2 (TARGET_32081) +#define HAVE_fixunssfsi2 (TARGET_32081) +#define HAVE_fixunsdfqi2 (TARGET_32081) +#define HAVE_fixunsdfhi2 (TARGET_32081) +#define HAVE_fixunsdfsi2 (TARGET_32081) +#define HAVE_fix_truncsfqi2 (TARGET_32081) +#define HAVE_fix_truncsfhi2 (TARGET_32081) +#define HAVE_fix_truncsfsi2 (TARGET_32081) +#define HAVE_fix_truncdfqi2 (TARGET_32081) +#define HAVE_fix_truncdfhi2 (TARGET_32081) +#define HAVE_fix_truncdfsi2 (TARGET_32081) +#define HAVE_adddf3 (TARGET_32081) +#define HAVE_addsf3 (TARGET_32081) +#define HAVE_addsi3 1 +#define HAVE_addhi3 1 +#define HAVE_addqi3 1 +#define HAVE_subdf3 (TARGET_32081) +#define HAVE_subsf3 (TARGET_32081) +#define HAVE_subsi3 1 +#define HAVE_subhi3 1 +#define HAVE_subqi3 1 +#define HAVE_muldf3 (TARGET_32081) +#define HAVE_mulsf3 (TARGET_32081) +#define HAVE_mulsi3 1 +#define HAVE_mulhi3 1 +#define HAVE_mulqi3 1 +#define HAVE_umulsidi3 1 +#define HAVE_divdf3 (TARGET_32081) +#define HAVE_divsf3 (TARGET_32081) +#define HAVE_divsi3 1 +#define HAVE_divhi3 1 +#define HAVE_divqi3 1 +#define HAVE_udivsi3 1 +#define HAVE_udivhi3 1 +#define HAVE_udivqi3 1 +#define HAVE_modsi3 1 +#define HAVE_modhi3 1 +#define HAVE_modqi3 1 +#define HAVE_umodsi3 1 +#define HAVE_umodhi3 1 +#define HAVE_umodqi3 1 +#define HAVE_andsi3 1 +#define HAVE_andhi3 1 +#define HAVE_andqi3 1 +#define HAVE_iorsi3 1 +#define HAVE_iorhi3 1 +#define HAVE_iorqi3 1 +#define HAVE_xorsi3 1 +#define HAVE_xorhi3 1 +#define HAVE_xorqi3 1 +#define HAVE_negdf2 (TARGET_32081) +#define HAVE_negsf2 (TARGET_32081) +#define HAVE_negsi2 1 +#define HAVE_neghi2 1 +#define HAVE_negqi2 1 +#define HAVE_one_cmplsi2 1 +#define HAVE_one_cmplhi2 1 +#define HAVE_one_cmplqi2 1 +#define HAVE_ashlsi3 1 +#define HAVE_ashlhi3 1 +#define HAVE_ashlqi3 1 +#define HAVE_ashrsi3 1 +#define HAVE_ashrhi3 1 +#define HAVE_ashrqi3 1 +#define HAVE_lshlsi3 1 +#define HAVE_lshlhi3 1 +#define HAVE_lshlqi3 1 +#define HAVE_lshrsi3 1 +#define HAVE_lshrhi3 1 +#define HAVE_lshrqi3 1 +#define HAVE_rotlsi3 1 +#define HAVE_rotlhi3 1 +#define HAVE_rotlqi3 1 +#define HAVE_rotrsi3 1 +#define HAVE_rotrhi3 1 +#define HAVE_rotrqi3 1 +#define HAVE_extzv 1 +#define HAVE_insv 1 +#define HAVE_jump 1 +#define HAVE_beq 1 +#define HAVE_bne 1 +#define HAVE_bgt 1 +#define HAVE_bgtu 1 +#define HAVE_blt 1 +#define HAVE_bltu 1 +#define HAVE_bge 1 +#define HAVE_bgeu 1 +#define HAVE_ble 1 +#define HAVE_bleu 1 +#define HAVE_call 1 +#define HAVE_call_value 1 +#define HAVE_untyped_call 1 +#define HAVE_blockage 1 +#define HAVE_return (0) +#define HAVE_abssf2 (TARGET_32081) +#define HAVE_absdf2 (TARGET_32081) +#define HAVE_abssi2 1 +#define HAVE_abshi2 1 +#define HAVE_absqi2 1 +#define HAVE_nop 1 +#define HAVE_indirect_jump 1 +#define HAVE_tablejump 1 +#define HAVE_seq 1 +#define HAVE_sne 1 +#define HAVE_sgt 1 +#define HAVE_sgtu 1 +#define HAVE_slt 1 +#define HAVE_sltu 1 +#define HAVE_sge 1 +#define HAVE_sgeu 1 +#define HAVE_sle 1 +#define HAVE_sleu 1 + +#ifndef NO_MD_PROTOTYPES +extern rtx gen_tstsi PROTO((rtx)); +extern rtx gen_tsthi PROTO((rtx)); +extern rtx gen_tstqi PROTO((rtx)); +extern rtx gen_tstdf PROTO((rtx)); +extern rtx gen_tstsf PROTO((rtx)); +extern rtx gen_cmpsi PROTO((rtx, rtx)); +extern rtx gen_cmphi PROTO((rtx, rtx)); +extern rtx gen_cmpqi PROTO((rtx, rtx)); +extern rtx gen_cmpdf PROTO((rtx, rtx)); +extern rtx gen_cmpsf PROTO((rtx, rtx)); +extern rtx gen_movdf PROTO((rtx, rtx)); +extern rtx gen_movsf PROTO((rtx, rtx)); +extern rtx gen_movdi PROTO((rtx, rtx)); +extern rtx gen_movsi PROTO((rtx, rtx)); +extern rtx gen_movhi PROTO((rtx, rtx)); +extern rtx gen_movstricthi PROTO((rtx, rtx)); +extern rtx gen_movqi PROTO((rtx, rtx)); +extern rtx gen_movstrictqi PROTO((rtx, rtx)); +extern rtx gen_movstrsi PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_movstrsi1 PROTO((rtx, rtx, rtx)); +extern rtx gen_truncsiqi2 PROTO((rtx, rtx)); +extern rtx gen_truncsihi2 PROTO((rtx, rtx)); +extern rtx gen_trunchiqi2 PROTO((rtx, rtx)); +extern rtx gen_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_extendsfdf2 PROTO((rtx, rtx)); +extern rtx gen_truncdfsf2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendhisi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqihi2 PROTO((rtx, rtx)); +extern rtx gen_zero_extendqisi2 PROTO((rtx, rtx)); +extern rtx gen_floatsisf2 PROTO((rtx, rtx)); +extern rtx gen_floatsidf2 PROTO((rtx, rtx)); +extern rtx gen_floathisf2 PROTO((rtx, rtx)); +extern rtx gen_floathidf2 PROTO((rtx, rtx)); +extern rtx gen_floatqisf2 PROTO((rtx, rtx)); +extern rtx gen_fixsfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixsfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixsfsi2 PROTO((rtx, rtx)); +extern rtx gen_fixdfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixdfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fixunssfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixunssfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixunssfsi2 PROTO((rtx, rtx)); +extern rtx gen_fixunsdfqi2 PROTO((rtx, rtx)); +extern rtx gen_fixunsdfhi2 PROTO((rtx, rtx)); +extern rtx gen_fixunsdfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfqi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfhi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncsfsi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfqi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfhi2 PROTO((rtx, rtx)); +extern rtx gen_fix_truncdfsi2 PROTO((rtx, rtx)); +extern rtx gen_adddf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_addqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_subqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_muldf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_mulqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umulsidi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divdf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divsf3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_divqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_udivqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_modsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_modhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_modqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umodsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umodhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_umodqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_andqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_iorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_xorqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_negdf2 PROTO((rtx, rtx)); +extern rtx gen_negsf2 PROTO((rtx, rtx)); +extern rtx gen_negsi2 PROTO((rtx, rtx)); +extern rtx gen_neghi2 PROTO((rtx, rtx)); +extern rtx gen_negqi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplsi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplhi2 PROTO((rtx, rtx)); +extern rtx gen_one_cmplqi2 PROTO((rtx, rtx)); +extern rtx gen_ashlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_ashrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_lshrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotlqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrsi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrhi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_rotrqi3 PROTO((rtx, rtx, rtx)); +extern rtx gen_extzv PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_insv PROTO((rtx, rtx, rtx, rtx)); +extern rtx gen_jump PROTO((rtx)); +extern rtx gen_beq PROTO((rtx)); +extern rtx gen_bne PROTO((rtx)); +extern rtx gen_bgt PROTO((rtx)); +extern rtx gen_bgtu PROTO((rtx)); +extern rtx gen_blt PROTO((rtx)); +extern rtx gen_bltu PROTO((rtx)); +extern rtx gen_bge PROTO((rtx)); +extern rtx gen_bgeu PROTO((rtx)); +extern rtx gen_ble PROTO((rtx)); +extern rtx gen_bleu PROTO((rtx)); +extern rtx gen_untyped_call PROTO((rtx, rtx, rtx)); +extern rtx gen_blockage PROTO((void)); +extern rtx gen_return PROTO((void)); +extern rtx gen_abssf2 PROTO((rtx, rtx)); +extern rtx gen_absdf2 PROTO((rtx, rtx)); +extern rtx gen_abssi2 PROTO((rtx, rtx)); +extern rtx gen_abshi2 PROTO((rtx, rtx)); +extern rtx gen_absqi2 PROTO((rtx, rtx)); +extern rtx gen_nop PROTO((void)); +extern rtx gen_indirect_jump PROTO((rtx)); +extern rtx gen_tablejump PROTO((rtx, rtx)); +extern rtx gen_seq PROTO((rtx)); +extern rtx gen_sne PROTO((rtx)); +extern rtx gen_sgt PROTO((rtx)); +extern rtx gen_sgtu PROTO((rtx)); +extern rtx gen_slt PROTO((rtx)); +extern rtx gen_sltu PROTO((rtx)); +extern rtx gen_sge PROTO((rtx)); +extern rtx gen_sgeu PROTO((rtx)); +extern rtx gen_sle PROTO((rtx)); +extern rtx gen_sleu PROTO((rtx)); + +#ifdef MD_CALL_PROTOTYPES +extern rtx gen_call PROTO((rtx, rtx)); +extern rtx gen_call_value PROTO((rtx, rtx, rtx)); + +#else /* !MD_CALL_PROTOTYPES */ +extern rtx gen_call (); +extern rtx gen_call_value (); +#endif /* !MD_CALL_PROTOTYPES */ + +#else /* NO_MD_PROTOTYPES */ +extern rtx gen_tstsi (); +extern rtx gen_tsthi (); +extern rtx gen_tstqi (); +extern rtx gen_tstdf (); +extern rtx gen_tstsf (); +extern rtx gen_cmpsi (); +extern rtx gen_cmphi (); +extern rtx gen_cmpqi (); +extern rtx gen_cmpdf (); +extern rtx gen_cmpsf (); +extern rtx gen_movdf (); +extern rtx gen_movsf (); +extern rtx gen_movdi (); +extern rtx gen_movsi (); +extern rtx gen_movhi (); +extern rtx gen_movstricthi (); +extern rtx gen_movqi (); +extern rtx gen_movstrictqi (); +extern rtx gen_movstrsi (); +extern rtx gen_movstrsi1 (); +extern rtx gen_truncsiqi2 (); +extern rtx gen_truncsihi2 (); +extern rtx gen_trunchiqi2 (); +extern rtx gen_extendhisi2 (); +extern rtx gen_extendqihi2 (); +extern rtx gen_extendqisi2 (); +extern rtx gen_extendsfdf2 (); +extern rtx gen_truncdfsf2 (); +extern rtx gen_zero_extendhisi2 (); +extern rtx gen_zero_extendqihi2 (); +extern rtx gen_zero_extendqisi2 (); +extern rtx gen_floatsisf2 (); +extern rtx gen_floatsidf2 (); +extern rtx gen_floathisf2 (); +extern rtx gen_floathidf2 (); +extern rtx gen_floatqisf2 (); +extern rtx gen_fixsfqi2 (); +extern rtx gen_fixsfhi2 (); +extern rtx gen_fixsfsi2 (); +extern rtx gen_fixdfqi2 (); +extern rtx gen_fixdfhi2 (); +extern rtx gen_fixdfsi2 (); +extern rtx gen_fixunssfqi2 (); +extern rtx gen_fixunssfhi2 (); +extern rtx gen_fixunssfsi2 (); +extern rtx gen_fixunsdfqi2 (); +extern rtx gen_fixunsdfhi2 (); +extern rtx gen_fixunsdfsi2 (); +extern rtx gen_fix_truncsfqi2 (); +extern rtx gen_fix_truncsfhi2 (); +extern rtx gen_fix_truncsfsi2 (); +extern rtx gen_fix_truncdfqi2 (); +extern rtx gen_fix_truncdfhi2 (); +extern rtx gen_fix_truncdfsi2 (); +extern rtx gen_adddf3 (); +extern rtx gen_addsf3 (); +extern rtx gen_addsi3 (); +extern rtx gen_addhi3 (); +extern rtx gen_addqi3 (); +extern rtx gen_subdf3 (); +extern rtx gen_subsf3 (); +extern rtx gen_subsi3 (); +extern rtx gen_subhi3 (); +extern rtx gen_subqi3 (); +extern rtx gen_muldf3 (); +extern rtx gen_mulsf3 (); +extern rtx gen_mulsi3 (); +extern rtx gen_mulhi3 (); +extern rtx gen_mulqi3 (); +extern rtx gen_umulsidi3 (); +extern rtx gen_divdf3 (); +extern rtx gen_divsf3 (); +extern rtx gen_divsi3 (); +extern rtx gen_divhi3 (); +extern rtx gen_divqi3 (); +extern rtx gen_udivsi3 (); +extern rtx gen_udivhi3 (); +extern rtx gen_udivqi3 (); +extern rtx gen_modsi3 (); +extern rtx gen_modhi3 (); +extern rtx gen_modqi3 (); +extern rtx gen_umodsi3 (); +extern rtx gen_umodhi3 (); +extern rtx gen_umodqi3 (); +extern rtx gen_andsi3 (); +extern rtx gen_andhi3 (); +extern rtx gen_andqi3 (); +extern rtx gen_iorsi3 (); +extern rtx gen_iorhi3 (); +extern rtx gen_iorqi3 (); +extern rtx gen_xorsi3 (); +extern rtx gen_xorhi3 (); +extern rtx gen_xorqi3 (); +extern rtx gen_negdf2 (); +extern rtx gen_negsf2 (); +extern rtx gen_negsi2 (); +extern rtx gen_neghi2 (); +extern rtx gen_negqi2 (); +extern rtx gen_one_cmplsi2 (); +extern rtx gen_one_cmplhi2 (); +extern rtx gen_one_cmplqi2 (); +extern rtx gen_ashlsi3 (); +extern rtx gen_ashlhi3 (); +extern rtx gen_ashlqi3 (); +extern rtx gen_ashrsi3 (); +extern rtx gen_ashrhi3 (); +extern rtx gen_ashrqi3 (); +extern rtx gen_lshlsi3 (); +extern rtx gen_lshlhi3 (); +extern rtx gen_lshlqi3 (); +extern rtx gen_lshrsi3 (); +extern rtx gen_lshrhi3 (); +extern rtx gen_lshrqi3 (); +extern rtx gen_rotlsi3 (); +extern rtx gen_rotlhi3 (); +extern rtx gen_rotlqi3 (); +extern rtx gen_rotrsi3 (); +extern rtx gen_rotrhi3 (); +extern rtx gen_rotrqi3 (); +extern rtx gen_extzv (); +extern rtx gen_insv (); +extern rtx gen_jump (); +extern rtx gen_beq (); +extern rtx gen_bne (); +extern rtx gen_bgt (); +extern rtx gen_bgtu (); +extern rtx gen_blt (); +extern rtx gen_bltu (); +extern rtx gen_bge (); +extern rtx gen_bgeu (); +extern rtx gen_ble (); +extern rtx gen_bleu (); +extern rtx gen_untyped_call (); +extern rtx gen_blockage (); +extern rtx gen_return (); +extern rtx gen_abssf2 (); +extern rtx gen_absdf2 (); +extern rtx gen_abssi2 (); +extern rtx gen_abshi2 (); +extern rtx gen_absqi2 (); +extern rtx gen_nop (); +extern rtx gen_indirect_jump (); +extern rtx gen_tablejump (); +extern rtx gen_seq (); +extern rtx gen_sne (); +extern rtx gen_sgt (); +extern rtx gen_sgtu (); +extern rtx gen_slt (); +extern rtx gen_sltu (); +extern rtx gen_sge (); +extern rtx gen_sgeu (); +extern rtx gen_sle (); +extern rtx gen_sleu (); +extern rtx gen_call (); +extern rtx gen_call_value (); +#endif /* NO_MD_PROTOTYPES */ diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-opinit.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-opinit.c new file mode 100644 index 000000000000..5c0e0d97c8b8 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-opinit.c @@ -0,0 +1,196 @@ +/* Generated automatically by the program `genopinit' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "flags.h" +#include "insn-flags.h" +#include "insn-codes.h" +#include "insn-config.h" +#include "recog.h" +#include "expr.h" +#include "reload.h" + +void +init_all_optabs () +{ + tst_optab->handlers[(int) SImode].insn_code = CODE_FOR_tstsi; + tst_optab->handlers[(int) HImode].insn_code = CODE_FOR_tsthi; + tst_optab->handlers[(int) QImode].insn_code = CODE_FOR_tstqi; + if (HAVE_tstdf) + tst_optab->handlers[(int) DFmode].insn_code = CODE_FOR_tstdf; + if (HAVE_tstsf) + tst_optab->handlers[(int) SFmode].insn_code = CODE_FOR_tstsf; + cmp_optab->handlers[(int) SImode].insn_code = CODE_FOR_cmpsi; + cmp_optab->handlers[(int) HImode].insn_code = CODE_FOR_cmphi; + cmp_optab->handlers[(int) QImode].insn_code = CODE_FOR_cmpqi; + if (HAVE_cmpdf) + cmp_optab->handlers[(int) DFmode].insn_code = CODE_FOR_cmpdf; + if (HAVE_cmpsf) + cmp_optab->handlers[(int) SFmode].insn_code = CODE_FOR_cmpsf; + mov_optab->handlers[(int) DFmode].insn_code = CODE_FOR_movdf; + mov_optab->handlers[(int) SFmode].insn_code = CODE_FOR_movsf; + mov_optab->handlers[(int) DImode].insn_code = CODE_FOR_movdi; + mov_optab->handlers[(int) SImode].insn_code = CODE_FOR_movsi; + mov_optab->handlers[(int) HImode].insn_code = CODE_FOR_movhi; + movstrict_optab->handlers[(int) HImode].insn_code = CODE_FOR_movstricthi; + mov_optab->handlers[(int) QImode].insn_code = CODE_FOR_movqi; + movstrict_optab->handlers[(int) QImode].insn_code = CODE_FOR_movstrictqi; + movstr_optab[(int) SImode] = CODE_FOR_movstrsi; + extendtab[(int) SImode][(int) HImode][0] = CODE_FOR_extendhisi2; + extendtab[(int) HImode][(int) QImode][0] = CODE_FOR_extendqihi2; + extendtab[(int) SImode][(int) QImode][0] = CODE_FOR_extendqisi2; + if (HAVE_extendsfdf2) + extendtab[(int) DFmode][(int) SFmode][0] = CODE_FOR_extendsfdf2; + extendtab[(int) SImode][(int) HImode][1] = CODE_FOR_zero_extendhisi2; + extendtab[(int) HImode][(int) QImode][1] = CODE_FOR_zero_extendqihi2; + extendtab[(int) SImode][(int) QImode][1] = CODE_FOR_zero_extendqisi2; + if (HAVE_floatsisf2) + floattab[(int) SFmode][(int) SImode][0] = CODE_FOR_floatsisf2; + if (HAVE_floatsidf2) + floattab[(int) DFmode][(int) SImode][0] = CODE_FOR_floatsidf2; + if (HAVE_floathisf2) + floattab[(int) SFmode][(int) HImode][0] = CODE_FOR_floathisf2; + if (HAVE_floathidf2) + floattab[(int) DFmode][(int) HImode][0] = CODE_FOR_floathidf2; + if (HAVE_floatqisf2) + floattab[(int) SFmode][(int) QImode][0] = CODE_FOR_floatqisf2; + if (HAVE_fixsfqi2) + fixtab[(int) SFmode][(int) QImode][0] = CODE_FOR_fixsfqi2; + if (HAVE_fixsfhi2) + fixtab[(int) SFmode][(int) HImode][0] = CODE_FOR_fixsfhi2; + if (HAVE_fixsfsi2) + fixtab[(int) SFmode][(int) SImode][0] = CODE_FOR_fixsfsi2; + if (HAVE_fixdfqi2) + fixtab[(int) DFmode][(int) QImode][0] = CODE_FOR_fixdfqi2; + if (HAVE_fixdfhi2) + fixtab[(int) DFmode][(int) HImode][0] = CODE_FOR_fixdfhi2; + if (HAVE_fixdfsi2) + fixtab[(int) DFmode][(int) SImode][0] = CODE_FOR_fixdfsi2; + if (HAVE_fixunssfqi2) + fixtab[(int) SFmode][(int) QImode][1] = CODE_FOR_fixunssfqi2; + if (HAVE_fixunssfhi2) + fixtab[(int) SFmode][(int) HImode][1] = CODE_FOR_fixunssfhi2; + if (HAVE_fixunssfsi2) + fixtab[(int) SFmode][(int) SImode][1] = CODE_FOR_fixunssfsi2; + if (HAVE_fixunsdfqi2) + fixtab[(int) DFmode][(int) QImode][1] = CODE_FOR_fixunsdfqi2; + if (HAVE_fixunsdfhi2) + fixtab[(int) DFmode][(int) HImode][1] = CODE_FOR_fixunsdfhi2; + if (HAVE_fixunsdfsi2) + fixtab[(int) DFmode][(int) SImode][1] = CODE_FOR_fixunsdfsi2; + if (HAVE_fix_truncsfqi2) + fixtrunctab[(int) SFmode][(int) QImode][0] = CODE_FOR_fix_truncsfqi2; + if (HAVE_fix_truncsfhi2) + fixtrunctab[(int) SFmode][(int) HImode][0] = CODE_FOR_fix_truncsfhi2; + if (HAVE_fix_truncsfsi2) + fixtrunctab[(int) SFmode][(int) SImode][0] = CODE_FOR_fix_truncsfsi2; + if (HAVE_fix_truncdfqi2) + fixtrunctab[(int) DFmode][(int) QImode][0] = CODE_FOR_fix_truncdfqi2; + if (HAVE_fix_truncdfhi2) + fixtrunctab[(int) DFmode][(int) HImode][0] = CODE_FOR_fix_truncdfhi2; + if (HAVE_fix_truncdfsi2) + fixtrunctab[(int) DFmode][(int) SImode][0] = CODE_FOR_fix_truncdfsi2; + if (HAVE_adddf3) + add_optab->handlers[(int) DFmode].insn_code = CODE_FOR_adddf3; + if (HAVE_addsf3) + add_optab->handlers[(int) SFmode].insn_code = CODE_FOR_addsf3; + add_optab->handlers[(int) SImode].insn_code = CODE_FOR_addsi3; + add_optab->handlers[(int) HImode].insn_code = CODE_FOR_addhi3; + add_optab->handlers[(int) QImode].insn_code = CODE_FOR_addqi3; + if (HAVE_subdf3) + sub_optab->handlers[(int) DFmode].insn_code = CODE_FOR_subdf3; + if (HAVE_subsf3) + sub_optab->handlers[(int) SFmode].insn_code = CODE_FOR_subsf3; + sub_optab->handlers[(int) SImode].insn_code = CODE_FOR_subsi3; + sub_optab->handlers[(int) HImode].insn_code = CODE_FOR_subhi3; + sub_optab->handlers[(int) QImode].insn_code = CODE_FOR_subqi3; + if (HAVE_muldf3) + smul_optab->handlers[(int) DFmode].insn_code = CODE_FOR_muldf3; + if (HAVE_mulsf3) + smul_optab->handlers[(int) SFmode].insn_code = CODE_FOR_mulsf3; + smul_optab->handlers[(int) SImode].insn_code = CODE_FOR_mulsi3; + smul_optab->handlers[(int) HImode].insn_code = CODE_FOR_mulhi3; + smul_optab->handlers[(int) QImode].insn_code = CODE_FOR_mulqi3; + umul_widen_optab->handlers[(int) DImode].insn_code = CODE_FOR_umulsidi3; + if (HAVE_divdf3) + flodiv_optab->handlers[(int) DFmode].insn_code = CODE_FOR_divdf3; + if (HAVE_divsf3) + flodiv_optab->handlers[(int) SFmode].insn_code = CODE_FOR_divsf3; + sdiv_optab->handlers[(int) SImode].insn_code = CODE_FOR_divsi3; + sdiv_optab->handlers[(int) HImode].insn_code = CODE_FOR_divhi3; + sdiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_divqi3; + udiv_optab->handlers[(int) SImode].insn_code = CODE_FOR_udivsi3; + udiv_optab->handlers[(int) HImode].insn_code = CODE_FOR_udivhi3; + udiv_optab->handlers[(int) QImode].insn_code = CODE_FOR_udivqi3; + smod_optab->handlers[(int) SImode].insn_code = CODE_FOR_modsi3; + smod_optab->handlers[(int) HImode].insn_code = CODE_FOR_modhi3; + smod_optab->handlers[(int) QImode].insn_code = CODE_FOR_modqi3; + umod_optab->handlers[(int) SImode].insn_code = CODE_FOR_umodsi3; + umod_optab->handlers[(int) HImode].insn_code = CODE_FOR_umodhi3; + umod_optab->handlers[(int) QImode].insn_code = CODE_FOR_umodqi3; + and_optab->handlers[(int) SImode].insn_code = CODE_FOR_andsi3; + and_optab->handlers[(int) HImode].insn_code = CODE_FOR_andhi3; + and_optab->handlers[(int) QImode].insn_code = CODE_FOR_andqi3; + ior_optab->handlers[(int) SImode].insn_code = CODE_FOR_iorsi3; + ior_optab->handlers[(int) HImode].insn_code = CODE_FOR_iorhi3; + ior_optab->handlers[(int) QImode].insn_code = CODE_FOR_iorqi3; + xor_optab->handlers[(int) SImode].insn_code = CODE_FOR_xorsi3; + xor_optab->handlers[(int) HImode].insn_code = CODE_FOR_xorhi3; + xor_optab->handlers[(int) QImode].insn_code = CODE_FOR_xorqi3; + if (HAVE_negdf2) + neg_optab->handlers[(int) DFmode].insn_code = CODE_FOR_negdf2; + if (HAVE_negsf2) + neg_optab->handlers[(int) SFmode].insn_code = CODE_FOR_negsf2; + neg_optab->handlers[(int) SImode].insn_code = CODE_FOR_negsi2; + neg_optab->handlers[(int) HImode].insn_code = CODE_FOR_neghi2; + neg_optab->handlers[(int) QImode].insn_code = CODE_FOR_negqi2; + one_cmpl_optab->handlers[(int) SImode].insn_code = CODE_FOR_one_cmplsi2; + one_cmpl_optab->handlers[(int) HImode].insn_code = CODE_FOR_one_cmplhi2; + one_cmpl_optab->handlers[(int) QImode].insn_code = CODE_FOR_one_cmplqi2; + ashl_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashlsi3; + ashl_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashlhi3; + ashl_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashlqi3; + ashr_optab->handlers[(int) SImode].insn_code = CODE_FOR_ashrsi3; + ashr_optab->handlers[(int) HImode].insn_code = CODE_FOR_ashrhi3; + ashr_optab->handlers[(int) QImode].insn_code = CODE_FOR_ashrqi3; + lshl_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshlsi3; + lshl_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshlhi3; + lshl_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshlqi3; + lshr_optab->handlers[(int) SImode].insn_code = CODE_FOR_lshrsi3; + lshr_optab->handlers[(int) HImode].insn_code = CODE_FOR_lshrhi3; + lshr_optab->handlers[(int) QImode].insn_code = CODE_FOR_lshrqi3; + rotl_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotlsi3; + rotl_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotlhi3; + rotl_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotlqi3; + rotr_optab->handlers[(int) SImode].insn_code = CODE_FOR_rotrsi3; + rotr_optab->handlers[(int) HImode].insn_code = CODE_FOR_rotrhi3; + rotr_optab->handlers[(int) QImode].insn_code = CODE_FOR_rotrqi3; + bcc_gen_fctn[(int) EQ] = gen_beq; + bcc_gen_fctn[(int) NE] = gen_bne; + bcc_gen_fctn[(int) GT] = gen_bgt; + bcc_gen_fctn[(int) GTU] = gen_bgtu; + bcc_gen_fctn[(int) LT] = gen_blt; + bcc_gen_fctn[(int) LTU] = gen_bltu; + bcc_gen_fctn[(int) GE] = gen_bge; + bcc_gen_fctn[(int) GEU] = gen_bgeu; + bcc_gen_fctn[(int) LE] = gen_ble; + bcc_gen_fctn[(int) LEU] = gen_bleu; + if (HAVE_abssf2) + abs_optab->handlers[(int) SFmode].insn_code = CODE_FOR_abssf2; + if (HAVE_absdf2) + abs_optab->handlers[(int) DFmode].insn_code = CODE_FOR_absdf2; + abs_optab->handlers[(int) SImode].insn_code = CODE_FOR_abssi2; + abs_optab->handlers[(int) HImode].insn_code = CODE_FOR_abshi2; + abs_optab->handlers[(int) QImode].insn_code = CODE_FOR_absqi2; + setcc_gen_code[(int) EQ] = CODE_FOR_seq; + setcc_gen_code[(int) NE] = CODE_FOR_sne; + setcc_gen_code[(int) GT] = CODE_FOR_sgt; + setcc_gen_code[(int) GTU] = CODE_FOR_sgtu; + setcc_gen_code[(int) LT] = CODE_FOR_slt; + setcc_gen_code[(int) LTU] = CODE_FOR_sltu; + setcc_gen_code[(int) GE] = CODE_FOR_sge; + setcc_gen_code[(int) GEU] = CODE_FOR_sgeu; + setcc_gen_code[(int) LE] = CODE_FOR_sle; + setcc_gen_code[(int) LEU] = CODE_FOR_sleu; +} diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-output.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-output.c new file mode 100644 index 000000000000..9a38ab070859 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-output.c @@ -0,0 +1,3871 @@ +/* Generated automatically by the program `genoutput' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" + +#include "conditions.h" +#include "insn-flags.h" +#include "insn-attr.h" + +#include "insn-codes.h" + +#include "recog.h" + +#include +#include "output.h" + +static char * +output_0 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ cc_status.flags |= CC_REVERSED; + operands[1] = const0_rtx; + return "cmpqd %1,%0"; } +} + +static char * +output_1 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ cc_status.flags |= CC_REVERSED; + operands[1] = const0_rtx; + return "cmpqw %1,%0"; } +} + +static char * +output_2 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ cc_status.flags |= CC_REVERSED; + operands[1] = const0_rtx; + return "cmpqb %1,%0"; } +} + +static char * +output_3 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ cc_status.flags |= CC_REVERSED; + operands[1] = CONST0_RTX (DFmode); + return "cmpl %1,%0"; } +} + +static char * +output_4 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ cc_status.flags |= CC_REVERSED; + operands[1] = CONST0_RTX (SFmode); + return "cmpf %1,%0"; } +} + +static char * +output_5 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + int i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + cc_status.flags |= CC_REVERSED; + return "cmpqd %1,%0"; + } + } + cc_status.flags &= ~CC_REVERSED; + if (GET_CODE (operands[0]) == CONST_INT) + { + int i = INTVAL (operands[0]); + if (i <= 7 && i >= -8) + return "cmpqd %0,%1"; + } + return "cmpd %0,%1"; +} +} + +static char * +output_6 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + short i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + cc_status.flags |= CC_REVERSED; + if (INTVAL (operands[1]) > 7) + operands[1] = gen_rtx(CONST_INT, VOIDmode, i); + return "cmpqw %1,%0"; + } + } + cc_status.flags &= ~CC_REVERSED; + if (GET_CODE (operands[0]) == CONST_INT) + { + short i = INTVAL (operands[0]); + if (i <= 7 && i >= -8) + { + if (INTVAL (operands[0]) > 7) + operands[0] = gen_rtx(CONST_INT, VOIDmode, i); + return "cmpqw %0,%1"; + } + } + return "cmpw %0,%1"; +} +} + +static char * +output_7 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + char i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + cc_status.flags |= CC_REVERSED; + if (INTVAL (operands[1]) > 7) + operands[1] = gen_rtx(CONST_INT, VOIDmode, i); + return "cmpqb %1,%0"; + } + } + cc_status.flags &= ~CC_REVERSED; + if (GET_CODE (operands[0]) == CONST_INT) + { + char i = INTVAL (operands[0]); + if (i <= 7 && i >= -8) + { + if (INTVAL (operands[0]) > 7) + operands[0] = gen_rtx(CONST_INT, VOIDmode, i); + return "cmpqb %0,%1"; + } + } + return "cmpb %0,%1"; +} +} + +static char * +output_10 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) + return "movl %1,%0"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("movd %1,tos", xoperands); + output_asm_insn ("movd %1,tos", operands); + return "movl tos,%0"; + } + return "movl %1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn ("movl %1,tos\n\tmovd tos,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "movd tos,%0"; + } + else + return "movl %1,%0"; + } + return output_move_double (operands); +} +} + +static char * +output_11 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return "movd %1,tos\n\tmovf tos,%0"; + else + return "movf %1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return "movf %1,tos\n\tmovd tos,%0"; + return "movf %1,%0"; + } +#if 0 /* Someone suggested this for the Sequent. Is it needed? */ + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return "movf %1,%0"; +#endif +/* There was a #if 0 around this, but that was erroneous + for many machines -- rms. */ +#ifndef MOVD_FLOAT_OK + /* GAS understands floating constants in ordinary movd instructions + but other assemblers might object. */ + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + union {int i[2]; float f; double d;} convrt; + convrt.i[0] = CONST_DOUBLE_LOW (operands[1]); + convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]); + convrt.f = convrt.d; + + /* Is there a better machine-independent way to to this? */ + operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]); + return "movd %1,%0"; + } +#endif + else return "movd %1,%0"; +} +} + +static char * +output_13 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) + return "movl %1,%0"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn ("movd %1,tos", xoperands); + output_asm_insn ("movd %1,tos", operands); + return "movl tos,%0"; + } + return "movl %1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn ("movl %1,tos\n\tmovd tos,%0", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "movd tos,%0"; + } + else + return "movl %1,%0"; + } + return output_move_double (operands); +} +} + +static char * +output_15 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return "movd %1,tos\n\tmovf tos,%0"; + else + return "movf %1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return "movf %1,tos\n\tmovd tos,%0"; + return "movf %1,%0"; + } + if (GET_CODE (operands[1]) == CONST_INT) + { + int i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + return "movqd %1,%0"; + if (i < 0x4000 && i >= -0x4000 && ! TARGET_32532) +#if defined (GNX_V3) || defined (UTEK_ASM) + return "addr %c1,%0"; +#else + return "addr @%c1,%0"; +#endif + return "movd %1,%0"; + } + else if (GET_CODE (operands[1]) == REG) + { + if (REGNO (operands[1]) < 16) + return "movd %1,%0"; + else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM) + { + if (GET_CODE(operands[0]) == REG) + return "sprd fp,%0"; + else + return "addr 0(fp),%0" ; + } + else if (REGNO (operands[1]) == STACK_POINTER_REGNUM) + { + if (GET_CODE(operands[0]) == REG) + return "sprd sp,%0"; + else + return "addr 0(sp),%0" ; + } + else abort (); + } + else if (GET_CODE (operands[1]) == MEM) + return "movd %1,%0"; + /* Check if this effective address can be + calculated faster by pulling it apart. */ + if (REG_P (operands[0]) + && GET_CODE (operands[1]) == MULT + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && (INTVAL (XEXP (operands[1], 1)) == 2 + || INTVAL (XEXP (operands[1], 1)) == 4)) + { + rtx xoperands[3]; + xoperands[0] = operands[0]; + xoperands[1] = XEXP (operands[1], 0); + xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); + return output_shift_insn (xoperands); + } + return "addr %a1,%0"; +} +} + +static char * +output_16 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + short i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + if (INTVAL (operands[1]) > 7) + operands[1] = + gen_rtx (CONST_INT, VOIDmode, i); + return "movqw %1,%0"; + } + return "movw %1,%0"; + } + else if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return "movwf %1,tos\n\tmovf tos,%0"; + else + return "movwf %1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return "movf %1,tos\n\tmovd tos,%0"; + return "movf %1,%0"; + } + else + return "movw %1,%0"; +} +} + +static char * +output_17 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8) + return "movqw %1,%0"; + return "movw %1,%0"; +} +} + +static char * +output_18 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[1]) == CONST_INT) + { + char char_val = (char)INTVAL (operands[1]); + if (char_val <= 7 && char_val >= -8) + { + if (INTVAL (operands[1]) > 7) + operands[1] = + gen_rtx (CONST_INT, VOIDmode, char_val); + return "movqb %1,%0"; + } + return "movb %1,%0"; + } + else if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return "movbf %1,tos\n\tmovf tos,%0"; + else + return "movbf %1,%0"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return "movf %1,tos\n\tmovd tos,%0"; + return "movf %1,%0"; + } + else + return "movb %1,%0"; +} +} + +static char * +output_19 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9) + return "movqb %1,%0"; + return "movb %1,%0"; +} +} + +static char * +output_21 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + abort (); + operands[0] = XEXP (operands[0], 0); + operands[1] = XEXP (operands[1], 0); + if (GET_CODE (operands[0]) == MEM) + if (GET_CODE (operands[1]) == MEM) + output_asm_insn ("movd %0,r2\n\tmovd %1,r1", operands); + else + output_asm_insn ("movd %0,r2\n\taddr %a1,r1", operands); + else if (GET_CODE (operands[1]) == MEM) + output_asm_insn ("addr %a0,r2\n\tmovd %1,r1", operands); + else + output_asm_insn ("addr %a0,r2\n\taddr %a1,r1", operands); + +#ifdef UTEK_ASM + if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); + if ((unsigned) INTVAL (operands[2]) <= 7) + return "movqd %2,r0\n\tmovsd $0"; + else + return "movd %2,r0\n\tmovsd $0"; + } + else + { + return "movd %2,r0\n\tmovsb $0"; + } +#else + if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); + if ((unsigned) INTVAL (operands[2]) <= 7) + return "movqd %2,r0\n\tmovsd"; + else + return "movd %2,r0\n\tmovsd"; + } + else + { + return "movd %2,r0\n\tmovsb"; + } +#endif +} +} + +static char * +output_58 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef SEQUENT_ADJUST_STACK + if (TARGET_32532) + if (INTVAL (operands[0]) == 8) + return "cmpd tos,tos"; + if (TARGET_32532 || TARGET_32332) + if (INTVAL (operands[0]) == 4) + return "cmpqd %$0,tos"; +#endif + if (! TARGET_32532) + { + if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64) + return "adjspb %$%n0"; + else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192) + return "adjspw %$%n0"; + } + return "adjspd %$%n0"; +} +} + +static char * +output_61 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (which_alternative == 1) + { + int i = INTVAL (operands[2]); + if (NS32K_DISPLACEMENT_P (i)) + return "addr %c2(%1),%0"; + else + return "movd %1,%0\n\taddd %2,%0"; + } + if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 7 && i >= -8) + return "addqd %2,%0"; + else if (GET_CODE (operands[0]) == REG + && i < 0x4000 && i >= -0x4000 && ! TARGET_32532) + return "addr %c2(%0),%0"; + } + return "addd %2,%0"; +} +} + +static char * +output_62 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + if (i <= 7 && i >= -8) + return "addqw %2,%0"; + } + return "addw %2,%0"; +} +} + +static char * +output_63 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) + return "addqw %1,%0"; + return "addw %1,%0"; +} +} + +static char * +output_64 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + if (i <= 7 && i >= -8) + return "addqb %2,%0"; + } + return "addb %2,%0"; +} +} + +static char * +output_65 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) + return "addqb %1,%0"; + return "addb %1,%0"; +} +} + +static char * +output_68 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64 + && INTVAL(operands[0]) > -64 && ! TARGET_32532) + return "adjspb %0"; + return "adjspd %0"; +} +} + +static char * +output_69 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 8 && i >= -7) + return "addqd %$%n2,%0"; + } + return "subd %2,%0"; +} +} + +static char * +output_70 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 8 && i >= -7) + return "addqw %$%n2,%0"; + } + return "subw %2,%0"; +} +} + +static char * +output_71 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) + return "addqw %$%n1,%0"; + return "subw %1,%0"; +} +} + +static char * +output_72 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 8 && i >= -7) + return "addqb %$%n2,%0"; + } + return "subb %2,%0"; +} +} + +static char * +output_73 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) + return "addqb %$%n1,%0"; + return "subb %1,%0"; +} +} + +static char * +output_85 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return "deid %2,%0\n\tmovd %1,%0"; +} +} + +static char * +output_86 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1); + return "deiw %2,%0\n\tmovw %1,%0"; +} +} + +static char * +output_87 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1); + return "deib %2,%0\n\tmovb %1,%0"; +} +} + +static char * +output_94 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT) + { + if ((INTVAL (operands[2]) | 0xff) == 0xffffffff) + { + if (INTVAL (operands[2]) == 0xffffff00) + return "movqb %$0,%0"; + else + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xff); + return "andb %2,%0"; + } + } + if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff) + { + if (INTVAL (operands[2]) == 0xffff0000) + return "movqw %$0,%0"; + else + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xffff); + return "andw %2,%0"; + } + } + } + return "andd %2,%0"; +} +} + +static char * +output_95 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) | 0xff) == 0xffffffff) + { + if (INTVAL (operands[2]) == 0xffffff00) + return "movqb %$0,%0"; + else + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xff); + return "andb %2,%0"; + } + } + return "andw %2,%0"; +} +} + +static char * +output_100 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT) { + if ((INTVAL (operands[2]) & 0xffffff00) == 0) + return "orb %2,%0"; + if ((INTVAL (operands[2]) & 0xffff0000) == 0) + return "orw %2,%0"; + } + return "ord %2,%0"; +} +} + +static char * +output_101 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE(operands[2]) == CONST_INT && + (INTVAL(operands[2]) & 0xffffff00) == 0) + return "orb %2,%0"; + return "orw %2,%0"; +} +} + +static char * +output_103 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE (operands[2]) == CONST_INT) { + if ((INTVAL (operands[2]) & 0xffffff00) == 0) + return "xorb %2,%0"; + if ((INTVAL (operands[2]) & 0xffff0000) == 0) + return "xorw %2,%0"; + } + return "xord %2,%0"; +} +} + +static char * +output_104 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (GET_CODE(operands[2]) == CONST_INT && + (INTVAL(operands[2]) & 0xffffff00) == 0) + return "xorb %2,%0"; + return "xorw %2,%0"; +} +} + +static char * +output_114 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (TARGET_32532) + return "lshd %2,%0"; + else + return output_shift_insn (operands); +} +} + +static char * +output_115 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) == 1) + return "addw %0,%0"; + else if (INTVAL (operands[2]) == 2 && !TARGET_32532) + return "addw %0,%0\n\taddw %0,%0"; + } + if (TARGET_32532) + return "lshw %2,%0"; + else + return "ashw %2,%0"; +} +} + +static char * +output_116 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) == 1) + return "addb %0,%0"; + else if (INTVAL (operands[2]) == 2 && !TARGET_32532) + return "addb %0,%0\n\taddb %0,%0"; + } + if (TARGET_32532) + return "lshb %2,%0"; + else + return "ashb %2,%0"; +} +} + +static char * +output_150 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + if (REG_P (operands[0]) + && GET_CODE (operands[1]) == MULT + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && (INTVAL (XEXP (operands[1], 1)) == 2 + || INTVAL (XEXP (operands[1], 1)) == 4)) + { + rtx xoperands[3]; + xoperands[0] = operands[0]; + xoperands[1] = XEXP (operands[1], 0); + xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); + return output_shift_insn (xoperands); + } + return "addr %a1,%0"; +} +} + +static char * +output_155 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ cc_status.flags = CC_Z_IN_F; + return "tbitd %1,%0"; +} +} + +static char * +output_156 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + output_asm_insn ("movd %1,tos", operands); + if (INTVAL (operands[2]) == 16) + { + if (INTVAL (operands[3]) == 8) + output_asm_insn ("movzwd 1(sp),%0", operands); + else + output_asm_insn ("movzwd 2(sp),%0", operands); + } + else + { + if (INTVAL (operands[3]) == 8) + output_asm_insn ("movzbd 1(sp),%0", operands); + else if (INTVAL (operands[3]) == 16) + output_asm_insn ("movzbd 2(sp),%0", operands); + else + output_asm_insn ("movzbd 3(sp),%0", operands); + } + if (TARGET_32532 || TARGET_32332) + return "cmpqd %$0,tos"; + else + return "adjspb %$-4"; +} +} + +static char * +output_157 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[3]) == CONST_INT) + return "extsd %1,%0,%3,%2"; + else return "extd %3,%1,%0,%2"; +} +} + +static char * +output_158 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[3]) == CONST_INT) + return "extsd %1,%0,%3,%2"; + else return "extd %3,%1,%0,%2"; +} +} + +static char * +output_159 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) >= 8) + { + operands[0] = adj_offsettable_operand (operands[0], + INTVAL (operands[2]) / 8); + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8); + } + if (INTVAL (operands[1]) <= 8) + return "inssb %3,%0,%2,%1"; + else if (INTVAL (operands[1]) <= 16) + return "inssw %3,%0,%2,%1"; + else + return "inssd %3,%0,%2,%1"; + } + return "insd %2,%3,%0,%1"; +} +} + +static char * +output_160 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + if (INTVAL (operands[1]) <= 8) + return "inssb %3,%0,%2,%1"; + else if (INTVAL (operands[1]) <= 16) + return "inssw %3,%0,%2,%1"; + else + return "inssd %3,%0,%2,%1"; + return "insd %2,%3,%0,%1"; +} +} + +static char * +output_161 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (GET_CODE (operands[2]) == CONST_INT) + if (INTVAL (operands[1]) <= 8) + return "inssb %3,%0,%2,%1"; + else if (INTVAL (operands[1]) <= 16) + return "inssw %3,%0,%2,%1"; + else + return "inssd %3,%0,%2,%1"; + return "insd %2,%3,%0,%1"; +} +} + +static char * +output_163 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "bfc %l0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "bfs %l0"; + else return "beq %l0"; +} +} + +static char * +output_164 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "bfs %l0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "bfc %l0"; + else return "bne %l0"; +} +} + +static char * +output_173 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "bfs %l0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "bfc %l0"; + else return "bne %l0"; +} +} + +static char * +output_174 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "bfc %l0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "bfs %l0"; + else return "beq %l0"; +} +} + +static char * +output_185 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef JSR_ALWAYS + if (GET_CODE (operands[0]) == MEM) + { + rtx temp = XEXP (operands[0], 0); + if (CONSTANT_ADDRESS_P (temp)) + { +#ifdef ENCORE_ASM + return "bsr %?%0"; +#else +#ifdef CALL_MEMREF_IMPLICIT + operands[0] = temp; + return "bsr %0"; +#else +#ifdef GNX_V3 + return "bsr %0"; +#else + return "bsr %?%a0"; +#endif +#endif +#endif + } + if (GET_CODE (XEXP (operands[0], 0)) == REG) +#if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT) + return "jsr %0"; +#else + return "jsr %a0"; +#endif + } +#endif /* not JSR_ALWAYS */ + return "jsr %0"; +} +} + +static char * +output_186 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ +#ifndef JSR_ALWAYS + if (GET_CODE (operands[1]) == MEM) + { + rtx temp = XEXP (operands[1], 0); + if (CONSTANT_ADDRESS_P (temp)) + { +#ifdef ENCORE_ASM + return "bsr %?%1"; +#else +#ifdef CALL_MEMREF_IMPLICIT + operands[1] = temp; + return "bsr %1"; +#else +#ifdef GNX_V3 + return "bsr %1"; +#else + return "bsr %?%a1"; +#endif +#endif +#endif + } + if (GET_CODE (XEXP (operands[1], 0)) == REG) +#if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT) + return "jsr %1"; +#else + return "jsr %a1"; +#endif + } +#endif /* not JSR_ALWAYS */ + return "jsr %1"; +} +} + +static char * +output_197 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI", + CODE_LABEL_NUMBER (operands[1])); + return "casew %0"; +} +} + +static char * +output_198 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "sfcd %0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "sfsd %0"; + else return "seqd %0"; +} +} + +static char * +output_199 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "sfcw %0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "sfsw %0"; + else return "seqw %0"; +} +} + +static char * +output_200 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "sfcb %0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "sfsb %0"; + else return "seqb %0"; +} +} + +static char * +output_201 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "sfsd %0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "sfcd %0"; + else return "sned %0"; +} +} + +static char * +output_202 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "sfsw %0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "sfcw %0"; + else return "snew %0"; +} +} + +static char * +output_203 (operands, insn) + rtx *operands; + rtx insn; +{ + +{ if (cc_prev_status.flags & CC_Z_IN_F) + return "sfsb %0"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return "sfcb %0"; + else return "sneb %0"; +} +} + +char * const insn_template[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "cmpl %0,%1", + "cmpf %0,%1", + 0, + 0, + "movmd %1,%0,4", + 0, + "lprd sp,%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "movb %1,%0", + "movw %1,%0", + "movb %1,%0", + "movxwd %1,%0", + "movxbw %1,%0", + "movxbd %1,%0", + "movfl %1,%0", + "movlf %1,%0", + "movzwd %1,%0", + "movzbw %1,%0", + "movzbd %1,%0", + "movdf %1,%0", + "movdl %1,%0", + "movwf %1,%0", + "movwl %1,%0", + "movbf %1,%0", + "truncfb %1,%0", + "truncfw %1,%0", + "truncfd %1,%0", + "trunclb %1,%0", + "trunclw %1,%0", + "truncld %1,%0", + "truncfb %1,%0", + "truncfw %1,%0", + "truncfd %1,%0", + "trunclb %1,%0", + "trunclw %1,%0", + "truncld %1,%0", + "truncfb %1,%0", + "truncfw %1,%0", + "truncfd %1,%0", + "trunclb %1,%0", + "trunclw %1,%0", + "truncld %1,%0", + "addl %2,%0", + "addf %2,%0", + 0, + "addr %c1(fp),%0", + "addr %c1(sp),%0", + 0, + 0, + 0, + 0, + 0, + "subl %2,%0", + "subf %2,%0", + 0, + 0, + 0, + 0, + 0, + 0, + "mull %2,%0", + "mulf %2,%0", + "muld %2,%0", + "mulw %2,%0", + "mulb %2,%0", + "meid %2,%0", + "divl %2,%0", + "divf %2,%0", + "quod %2,%0", + "quow %2,%0", + "quob %2,%0", + 0, + 0, + 0, + "remd %2,%0", + "remw %2,%0", + "remb %2,%0", + "deid %2,%0", + "deiw %2,%0", + "deib %2,%0", + 0, + 0, + "andb %2,%0", + "bicd %1,%0", + "bicw %1,%0", + "bicb %1,%0", + 0, + 0, + "orb %2,%0", + 0, + 0, + "xorb %2,%0", + "negl %1,%0", + "negf %1,%0", + "negd %1,%0", + "negw %1,%0", + "negb %1,%0", + "comd %1,%0", + "comw %1,%0", + "comb %1,%0", + 0, + 0, + 0, + 0, + "ashd %$%n2,%0", + "ashd %2,%0", + 0, + "ashw %$%n2,%0", + "ashw %2,%0", + 0, + "ashb %$%n2,%0", + "ashb %2,%0", + "lshd %2,%0", + "lshw %2,%0", + "lshb %2,%0", + 0, + "lshd %$%n2,%0", + "lshd %2,%0", + 0, + "lshw %$%n2,%0", + "lshw %2,%0", + 0, + "lshb %$%n2,%0", + "lshb %2,%0", + "rotd %2,%0", + "rotw %2,%0", + "rotb %2,%0", + 0, + "rotd %$%n2,%0", + "rotd %2,%0", + 0, + "rotw %$%n2,%0", + "rotw %2,%0", + 0, + "rotb %$%n2,%0", + "rotb %2,%0", + 0, + "sbitd %1,%0", + "cbitd %1,%0", + "ibitd %1,%0", + "ibitb %1,%0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "br %l0", + 0, + 0, + "bgt %l0", + "bhi %l0", + "blt %l0", + "blo %l0", + "bge %l0", + "bhs %l0", + "ble %l0", + "bls %l0", + 0, + 0, + "ble %l0", + "bls %l0", + "bge %l0", + "bhs %l0", + "blt %l0", + "blo %l0", + "bgt %l0", + "bhi %l0", + "acbd %$%n1,%0,%l2", + "acbd %3,%0,%l2", + 0, + 0, + 0, + "", + "ret 0", + "absf %1,%0", + "absl %1,%0", + "absd %1,%0", + "absw %1,%0", + "absb %1,%0", + "nop", + "jump %0", + 0, + 0, + 0, + 0, + 0, + 0, + 0, + "sgtd %0", + "sgtw %0", + "sgtb %0", + "shid %0", + "shiw %0", + "shib %0", + "sltd %0", + "sltw %0", + "sltb %0", + "slod %0", + "slow %0", + "slob %0", + "sged %0", + "sgew %0", + "sgeb %0", + "shsd %0", + "shsw %0", + "shsb %0", + "sled %0", + "slew %0", + "sleb %0", + "slsd %0", + "slsw %0", + "slsb %0", + }; + +char *(*const insn_outfun[])() = + { + output_0, + output_1, + output_2, + output_3, + output_4, + output_5, + output_6, + output_7, + 0, + 0, + output_10, + output_11, + 0, + output_13, + 0, + output_15, + output_16, + output_17, + output_18, + output_19, + 0, + output_21, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_58, + 0, + 0, + output_61, + output_62, + output_63, + output_64, + output_65, + 0, + 0, + output_68, + output_69, + output_70, + output_71, + output_72, + output_73, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_85, + output_86, + output_87, + 0, + 0, + 0, + 0, + 0, + 0, + output_94, + output_95, + 0, + 0, + 0, + 0, + output_100, + output_101, + 0, + output_103, + output_104, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_114, + output_115, + output_116, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_150, + 0, + 0, + 0, + 0, + output_155, + output_156, + output_157, + output_158, + output_159, + output_160, + output_161, + 0, + output_163, + output_164, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_173, + output_174, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_185, + output_186, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + output_197, + output_198, + output_199, + output_200, + output_201, + output_202, + output_203, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + }; + +rtx (*const insn_gen_function[]) () = + { + gen_tstsi, + gen_tsthi, + gen_tstqi, + gen_tstdf, + gen_tstsf, + gen_cmpsi, + gen_cmphi, + gen_cmpqi, + gen_cmpdf, + gen_cmpsf, + gen_movdf, + gen_movsf, + 0, + gen_movdi, + 0, + gen_movsi, + gen_movhi, + gen_movstricthi, + gen_movqi, + gen_movstrictqi, + gen_movstrsi, + gen_movstrsi1, + gen_truncsiqi2, + gen_truncsihi2, + gen_trunchiqi2, + gen_extendhisi2, + gen_extendqihi2, + gen_extendqisi2, + gen_extendsfdf2, + gen_truncdfsf2, + gen_zero_extendhisi2, + gen_zero_extendqihi2, + gen_zero_extendqisi2, + gen_floatsisf2, + gen_floatsidf2, + gen_floathisf2, + gen_floathidf2, + gen_floatqisf2, + gen_fixsfqi2, + gen_fixsfhi2, + gen_fixsfsi2, + gen_fixdfqi2, + gen_fixdfhi2, + gen_fixdfsi2, + gen_fixunssfqi2, + gen_fixunssfhi2, + gen_fixunssfsi2, + gen_fixunsdfqi2, + gen_fixunsdfhi2, + gen_fixunsdfsi2, + gen_fix_truncsfqi2, + gen_fix_truncsfhi2, + gen_fix_truncsfsi2, + gen_fix_truncdfqi2, + gen_fix_truncdfhi2, + gen_fix_truncdfsi2, + gen_adddf3, + gen_addsf3, + 0, + 0, + 0, + gen_addsi3, + gen_addhi3, + 0, + gen_addqi3, + 0, + gen_subdf3, + gen_subsf3, + 0, + gen_subsi3, + gen_subhi3, + 0, + gen_subqi3, + 0, + gen_muldf3, + gen_mulsf3, + gen_mulsi3, + gen_mulhi3, + gen_mulqi3, + gen_umulsidi3, + gen_divdf3, + gen_divsf3, + gen_divsi3, + gen_divhi3, + gen_divqi3, + gen_udivsi3, + gen_udivhi3, + gen_udivqi3, + gen_modsi3, + gen_modhi3, + gen_modqi3, + gen_umodsi3, + gen_umodhi3, + gen_umodqi3, + gen_andsi3, + gen_andhi3, + gen_andqi3, + 0, + 0, + 0, + gen_iorsi3, + gen_iorhi3, + gen_iorqi3, + gen_xorsi3, + gen_xorhi3, + gen_xorqi3, + gen_negdf2, + gen_negsf2, + gen_negsi2, + gen_neghi2, + gen_negqi2, + gen_one_cmplsi2, + gen_one_cmplhi2, + gen_one_cmplqi2, + gen_ashlsi3, + gen_ashlhi3, + gen_ashlqi3, + gen_ashrsi3, + 0, + 0, + gen_ashrhi3, + 0, + 0, + gen_ashrqi3, + 0, + 0, + gen_lshlsi3, + gen_lshlhi3, + gen_lshlqi3, + gen_lshrsi3, + 0, + 0, + gen_lshrhi3, + 0, + 0, + gen_lshrqi3, + 0, + 0, + gen_rotlsi3, + gen_rotlhi3, + gen_rotlqi3, + gen_rotrsi3, + 0, + 0, + gen_rotrhi3, + 0, + 0, + gen_rotrqi3, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_extzv, + 0, + 0, + gen_insv, + gen_jump, + gen_beq, + gen_bne, + gen_bgt, + gen_bgtu, + gen_blt, + gen_bltu, + gen_bge, + gen_bgeu, + gen_ble, + gen_bleu, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + gen_call, + gen_call_value, + gen_untyped_call, + gen_blockage, + gen_return, + gen_abssf2, + gen_absdf2, + gen_abssi2, + gen_abshi2, + gen_absqi2, + gen_nop, + gen_indirect_jump, + gen_tablejump, + gen_seq, + 0, + 0, + gen_sne, + 0, + 0, + gen_sgt, + 0, + 0, + gen_sgtu, + 0, + 0, + gen_slt, + 0, + 0, + gen_sltu, + 0, + 0, + gen_sge, + 0, + 0, + gen_sgeu, + 0, + 0, + gen_sle, + 0, + 0, + gen_sleu, + 0, + 0, + }; + +char *insn_name[] = + { + "tstsi", + "tsthi", + "tstqi", + "tstdf", + "tstsf", + "cmpsi", + "cmphi", + "cmpqi", + "cmpdf", + "cmpsf", + "movdf", + "movsf", + "movsf+1", + "movdi", + "movdi+1", + "movsi", + "movhi", + "movstricthi", + "movqi", + "movstrictqi", + "movstrsi", + "movstrsi1", + "truncsiqi2", + "truncsihi2", + "trunchiqi2", + "extendhisi2", + "extendqihi2", + "extendqisi2", + "extendsfdf2", + "truncdfsf2", + "zero_extendhisi2", + "zero_extendqihi2", + "zero_extendqisi2", + "floatsisf2", + "floatsidf2", + "floathisf2", + "floathidf2", + "floatqisf2", + "fixsfqi2", + "fixsfhi2", + "fixsfsi2", + "fixdfqi2", + "fixdfhi2", + "fixdfsi2", + "fixunssfqi2", + "fixunssfhi2", + "fixunssfsi2", + "fixunsdfqi2", + "fixunsdfhi2", + "fixunsdfsi2", + "fix_truncsfqi2", + "fix_truncsfhi2", + "fix_truncsfsi2", + "fix_truncdfqi2", + "fix_truncdfhi2", + "fix_truncdfsi2", + "adddf3", + "addsf3", + "addsf3+1", + "addsf3+2", + "addsi3-1", + "addsi3", + "addhi3", + "addhi3+1", + "addqi3", + "addqi3+1", + "subdf3", + "subsf3", + "subsf3+1", + "subsi3", + "subhi3", + "subhi3+1", + "subqi3", + "subqi3+1", + "muldf3", + "mulsf3", + "mulsi3", + "mulhi3", + "mulqi3", + "umulsidi3", + "divdf3", + "divsf3", + "divsi3", + "divhi3", + "divqi3", + "udivsi3", + "udivhi3", + "udivqi3", + "modsi3", + "modhi3", + "modqi3", + "umodsi3", + "umodhi3", + "umodqi3", + "andsi3", + "andhi3", + "andqi3", + "andqi3+1", + "andqi3+2", + "iorsi3-1", + "iorsi3", + "iorhi3", + "iorqi3", + "xorsi3", + "xorhi3", + "xorqi3", + "negdf2", + "negsf2", + "negsi2", + "neghi2", + "negqi2", + "one_cmplsi2", + "one_cmplhi2", + "one_cmplqi2", + "ashlsi3", + "ashlhi3", + "ashlqi3", + "ashrsi3", + "ashrsi3+1", + "ashrhi3-1", + "ashrhi3", + "ashrhi3+1", + "ashrqi3-1", + "ashrqi3", + "ashrqi3+1", + "lshlsi3-1", + "lshlsi3", + "lshlhi3", + "lshlqi3", + "lshrsi3", + "lshrsi3+1", + "lshrhi3-1", + "lshrhi3", + "lshrhi3+1", + "lshrqi3-1", + "lshrqi3", + "lshrqi3+1", + "rotlsi3-1", + "rotlsi3", + "rotlhi3", + "rotlqi3", + "rotrsi3", + "rotrsi3+1", + "rotrhi3-1", + "rotrhi3", + "rotrhi3+1", + "rotrqi3-1", + "rotrqi3", + "rotrqi3+1", + "rotrqi3+2", + "rotrqi3+3", + "rotrqi3+4", + "rotrqi3+5", + "extzv-5", + "extzv-4", + "extzv-3", + "extzv-2", + "extzv-1", + "extzv", + "extzv+1", + "insv-1", + "insv", + "jump", + "beq", + "bne", + "bgt", + "bgtu", + "blt", + "bltu", + "bge", + "bgeu", + "ble", + "bleu", + "bleu+1", + "bleu+2", + "bleu+3", + "bleu+4", + "bleu+5", + "bleu+6", + "call-6", + "call-5", + "call-4", + "call-3", + "call-2", + "call-1", + "call", + "call_value", + "untyped_call", + "blockage", + "return", + "abssf2", + "absdf2", + "abssi2", + "abshi2", + "absqi2", + "nop", + "indirect_jump", + "tablejump", + "seq", + "seq+1", + "sne-1", + "sne", + "sne+1", + "sgt-1", + "sgt", + "sgt+1", + "sgtu-1", + "sgtu", + "sgtu+1", + "slt-1", + "slt", + "slt+1", + "sltu-1", + "sltu", + "sltu+1", + "sge-1", + "sge", + "sge+1", + "sgeu-1", + "sgeu", + "sgeu+1", + "sle-1", + "sle", + "sle+1", + "sleu-1", + "sleu", + "sleu+1", + "sleu+2", + }; +char **insn_name_ptr = insn_name; + +const int insn_n_operands[] = + { + 1, + 1, + 1, + 1, + 1, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 1, + 2, + 2, + 2, + 2, + 2, + 4, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 1, + 2, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + 4, + 4, + 4, + 4, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2, + 4, + 2, + 3, + 3, + 0, + 0, + 2, + 2, + 2, + 2, + 2, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + }; + +const int insn_n_dups[] = + { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 3, + 2, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + }; + +char *const insn_operand_constraint[][MAX_RECOG_OPERANDS] = + { + { "rm", }, + { "g", }, + { "g", }, + { "fmF", }, + { "fmF", }, + { "rmn", "rmn", }, + { "g", "g", }, + { "g", "g", }, + { "fmF", "fmF", }, + { "fmF", "fmF", }, + { "=&fg<", "fFg", }, + { "=fg<", "fFg", }, + { "=m", "m", }, + { "=&g<,*f,g", "gF,g,*f", }, + { "rmn", }, + { "=g<,g<,*f,g", "g,?xy,g,*f", }, + { "=g<,*f,g", "g,g,*f", }, + { "+r", "g", }, + { "=g<,*f,g", "g,g,*f", }, + { "+r", "g", }, + { "=g", "g", "rmn", "", }, + { "=g", "g", "rmn", }, + { "=g<", "rmn", }, + { "=g<", "rmn", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=fm<", "fmF", }, + { "=fm<", "fmF", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=fm<", "rm", }, + { "=fm<", "rm", }, + { "=fm<", "rm", }, + { "=fm<", "rm", }, + { "=fm<", "rm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=g<", "fm", }, + { "=fm", "%0", "fmF", }, + { "=fm", "%0", "fmF", }, + { "i", }, + { "=g<", "i", }, + { "=g<", "i", }, + { "=g,=g&<", "%0,r", "rmn,n", }, + { "=g", "%0", "g", }, + { "=r", "0", "g", }, + { "=g", "%0", "g", }, + { "=r", "0", "g", }, + { "=fm", "0", "fmF", }, + { "=fm", "0", "fmF", }, + { "i", }, + { "=g", "0", "rmn", }, + { "=g", "0", "g", }, + { "=r", "0", "g", }, + { "=g", "0", "g", }, + { "=r", "0", "g", }, + { "=fm", "%0", "fmF", }, + { "=fm", "%0", "fmF", }, + { "=g", "%0", "rmn", }, + { "=g", "%0", "g", }, + { "=g", "%0", "g", }, + { "=g", "0", "rmn", }, + { "=fm", "0", "fmF", }, + { "=fm", "0", "fmF", }, + { "=g", "0", "rmn", }, + { "=g", "0", "g", }, + { "=g", "0", "g", }, + { "=r", "0", "rmn", }, + { "=r", "0", "g", }, + { "=r", "0", "g", }, + { "=g", "0", "rmn", }, + { "=g", "0", "g", }, + { "=g", "0", "g", }, + { "=r", "0", "rmn", }, + { "=r", "0", "g", }, + { "=r", "0", "g", }, + { "=g", "%0", "rmn", }, + { "=g", "%0", "g", }, + { "=g", "%0", "g", }, + { "=g", "rmn", "0", }, + { "=g", "g", "0", }, + { "=g", "g", "0", }, + { "=g", "%0", "rmn", }, + { "=g", "%0", "g", }, + { "=g", "%0", "g", }, + { "=g", "%0", "rmn", }, + { "=g", "%0", "g", }, + { "=g", "%0", "g", }, + { "=fm<", "fmF", }, + { "=fm<", "fmF", }, + { "=g<", "rmn", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=g<", "rmn", }, + { "=g<", "g", }, + { "=g<", "g", }, + { "=g,g", "r,0", "I,rmn", }, + { "=g", "0", "rmn", }, + { "=g", "0", "rmn", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "0", "rmn", }, + { "=g", "0", "rmn", }, + { "=g", "0", "rmn", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "0", "rmn", }, + { "=g", "0", "rmn", }, + { "=g", "0", "rmn", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g", "g", "g", }, + { "=g", "0", "i", }, + { "=g", "0", "r", }, + { "=g<", "p", }, + { "+g", "rmn", }, + { "+g", "rmn", }, + { "+g", "rmn", }, + { "=g", "rmn", }, + { "rm", "g", }, + { "=ro", "r", "i", "i", }, + { "=g<", "g", "i", "rK", }, + { "=g<", "g", "i", "rK", }, + { "+o", "i", "rn", "rm", }, + { "+r", "i", "rK", "rm", }, + { "+g", "i", "rK", "rm", }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { "+g", "i", }, + { "+g", "i", "", "i", }, + { "m", "g", }, + { "=rf", "m", "g", }, + { "", "", "", }, + { 0 }, + { 0 }, + { "=fm<", "fmF", }, + { "=fm<", "fmF", }, + { "=g<", "rmn", }, + { "=g<", "g", }, + { "=g<", "g", }, + { 0 }, + { "r", }, + { "g", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + { "=g<", }, + }; + +const enum machine_mode insn_operand_mode[][MAX_RECOG_OPERANDS] = + { + { SImode, }, + { HImode, }, + { QImode, }, + { DFmode, }, + { SFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { TImode, TImode, }, + { DImode, DImode, }, + { SImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { QImode, QImode, }, + { BLKmode, BLKmode, SImode, VOIDmode, }, + { BLKmode, BLKmode, SImode, }, + { QImode, SImode, }, + { HImode, SImode, }, + { QImode, HImode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { DFmode, SFmode, }, + { SFmode, DFmode, }, + { SImode, HImode, }, + { HImode, QImode, }, + { SImode, QImode, }, + { SFmode, SImode, }, + { DFmode, SImode, }, + { SFmode, HImode, }, + { DFmode, HImode, }, + { SFmode, QImode, }, + { QImode, SFmode, }, + { HImode, SFmode, }, + { SImode, SFmode, }, + { QImode, DFmode, }, + { HImode, DFmode, }, + { SImode, DFmode, }, + { QImode, SFmode, }, + { HImode, SFmode, }, + { SImode, SFmode, }, + { QImode, DFmode, }, + { HImode, DFmode, }, + { SImode, DFmode, }, + { QImode, SFmode, }, + { HImode, SFmode, }, + { SImode, SFmode, }, + { QImode, DFmode, }, + { HImode, DFmode, }, + { SImode, DFmode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { QImode, QImode, QImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DImode, SImode, SImode, }, + { DFmode, DFmode, DFmode, }, + { SFmode, SFmode, SFmode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, DImode, SImode, }, + { HImode, DImode, HImode, }, + { QImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, DImode, SImode, }, + { HImode, DImode, HImode, }, + { QImode, DImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, HImode, }, + { QImode, QImode, QImode, }, + { DFmode, DFmode, }, + { SFmode, SFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, SImode, }, + { QImode, QImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, SImode, }, + { HImode, HImode, SImode, }, + { HImode, HImode, SImode, }, + { QImode, QImode, SImode, }, + { QImode, QImode, SImode, }, + { QImode, QImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, SImode, }, + { QImode, QImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, SImode, }, + { HImode, HImode, SImode, }, + { HImode, HImode, SImode, }, + { QImode, QImode, SImode, }, + { QImode, QImode, SImode, }, + { QImode, QImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, SImode, }, + { QImode, QImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { SImode, SImode, SImode, }, + { HImode, HImode, SImode, }, + { HImode, HImode, SImode, }, + { HImode, HImode, SImode, }, + { QImode, QImode, SImode, }, + { QImode, QImode, SImode, }, + { QImode, QImode, SImode, }, + { SImode, QImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { SImode, SImode, }, + { QImode, QImode, }, + { SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, QImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { SImode, SImode, SImode, SImode, }, + { QImode, SImode, SImode, SImode, }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { VOIDmode }, + { SImode, SImode, }, + { SImode, SImode, VOIDmode, SImode, }, + { QImode, QImode, }, + { VOIDmode, QImode, QImode, }, + { VOIDmode, VOIDmode, VOIDmode, }, + { VOIDmode }, + { VOIDmode }, + { SFmode, SFmode, }, + { DFmode, DFmode, }, + { SImode, SImode, }, + { HImode, HImode, }, + { QImode, QImode, }, + { VOIDmode }, + { SImode, }, + { HImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + { SImode, }, + { HImode, }, + { QImode, }, + }; + +const char insn_operand_strict_low[][MAX_RECOG_OPERANDS] = + { + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, }, + { 1, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, 0, }, + { 0, 0, 0, }, + { 1, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, 0, 0, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0, 0, }, + { 0, 0, 0, 0, }, + { 0, 0, }, + { 0, 0, 0, }, + { 0, 0, 0, }, + { 0 }, + { 0 }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0, 0, }, + { 0 }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + { 0, }, + }; + +extern int nonimmediate_operand (); +extern int general_operand (); +extern int memory_operand (); +extern int immediate_operand (); +extern int register_operand (); +extern int reg_or_mem_operand (); +extern int address_operand (); +extern int const_int_operand (); + +int (*const insn_operand_predicate[][MAX_RECOG_OPERANDS])() = + { + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { nonimmediate_operand, }, + { general_operand, }, + { general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { nonimmediate_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { memory_operand, memory_operand, }, + { general_operand, general_operand, }, + { general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, 0, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, nonimmediate_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { immediate_operand, }, + { general_operand, immediate_operand, }, + { general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, nonimmediate_operand, nonimmediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, reg_or_mem_operand, general_operand, }, + { register_operand, reg_or_mem_operand, general_operand, }, + { register_operand, reg_or_mem_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { register_operand, reg_or_mem_operand, general_operand, }, + { register_operand, reg_or_mem_operand, general_operand, }, + { register_operand, reg_or_mem_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, general_operand, immediate_operand, }, + { general_operand, general_operand, general_operand, }, + { general_operand, address_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, register_operand, const_int_operand, const_int_operand, }, + { general_operand, register_operand, const_int_operand, general_operand, }, + { general_operand, general_operand, const_int_operand, general_operand, }, + { memory_operand, const_int_operand, general_operand, general_operand, }, + { register_operand, const_int_operand, general_operand, general_operand, }, + { general_operand, const_int_operand, general_operand, general_operand, }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 0 }, + { general_operand, const_int_operand, }, + { general_operand, const_int_operand, 0, const_int_operand, }, + { memory_operand, general_operand, }, + { 0, memory_operand, general_operand, }, + { 0, 0, 0, }, + { 0 }, + { 0 }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { general_operand, general_operand, }, + { 0 }, + { register_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + { general_operand, }, + }; + +const int insn_n_alternatives[] = + { + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 3, + 1, + 4, + 3, + 1, + 3, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 2, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + }; diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-peep.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-peep.c new file mode 100644 index 000000000000..37136c4333d0 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-peep.c @@ -0,0 +1,28 @@ +/* Generated automatically by the program `genpeep' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "output.h" +#include "real.h" + +extern rtx peep_operand[]; + +#define operands peep_operand + +rtx +peephole (ins1) + rtx ins1; +{ + rtx insn, x, pat; + int i; + + if (NEXT_INSN (ins1) + && GET_CODE (NEXT_INSN (ins1)) == BARRIER) + return 0; + + return 0; +} + +rtx peep_operand[2]; diff --git a/gnu/usr.bin/gcc2/arch/ns32k/insn-recog.c b/gnu/usr.bin/gcc2/arch/ns32k/insn-recog.c new file mode 100644 index 000000000000..4a12463b9907 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/insn-recog.c @@ -0,0 +1,4381 @@ +/* Generated automatically by the program `genrecog' +from the machine description file `md'. */ + +#include "config.h" +#include "rtl.h" +#include "insn-config.h" +#include "recog.h" +#include "real.h" +#include "output.h" +#include "flags.h" + + +/* `recog' contains a decision tree + that recognizes whether the rtx X0 is a valid instruction. + + recog returns -1 if the rtx is not valid. + If the rtx is valid, recog returns a nonnegative number + which is the insn code number for the pattern that matched. + This is the same as the order in the machine description of + the entry that matched. This number can be used as an index into + entry that matched. This number can be used as an index into various + insn_* tables, such as insn_templates, insn_outfun, and insn_n_operands + (found in insn-output.c). + + The third argument to recog is an optional pointer to an int. + If present, recog will accept a pattern if it matches except for + missing CLOBBER expressions at the end. In that case, the value + pointed to by the optional pointer will be set to the number of + CLOBBERs that need to be added (it should be initialized to zero by + the caller). If it is set nonzero, the caller should allocate a + PARALLEL of the appropriate size, copy the initial entries, and call + add_clobbers (found in insn-emit.c) to fill in the CLOBBERs.*/ + +rtx recog_operand[MAX_RECOG_OPERANDS]; + +rtx *recog_operand_loc[MAX_RECOG_OPERANDS]; + +rtx *recog_dup_loc[MAX_DUP_OPERANDS]; + +char recog_dup_num[MAX_DUP_OPERANDS]; + +#define operands recog_operand + +int +recog_1 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case SIGN_EXTEND: + goto L105; + case ZERO_EXTEND: + goto L125; + case FIX: + goto L167; + case UNSIGNED_FIX: + goto L197; + case PLUS: + goto L256; + case MINUS: + goto L308; + case MULT: + goto L345; + case DIV: + goto L377; + case MOD: + goto L410; + case AND: + goto L458; + case IOR: + goto L476; + case XOR: + goto L697; + case NEG: + goto L514; + case NOT: + goto L526; + case ASHIFT: + goto L538; + case ASHIFTRT: + goto L553; + case LSHIFT: + goto L586; + case LSHIFTRT: + goto L601; + case ROTATE: + goto L634; + case ROTATERT: + goto L649; + case ZERO_EXTRACT: + goto L718; + } + } + if (general_operand (x1, SImode)) + { + ro[1] = x1; + return 15; + } + L681: + if (address_operand (x1, QImode)) + { + ro[1] = x1; + return 150; + } + goto ret0; + + L105: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 25; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 27; + } + } + goto ret0; + + L125: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 30; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 32; + } + } + goto ret0; + + L167: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SFmode: + switch (GET_CODE (x2)) + { + case FIX: + goto L168; + } + break; + case DFmode: + if (GET_CODE (x2) == FIX && 1) + goto L183; + } + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 52; + } + L237: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 55; + } + goto ret0; + + L168: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 40; + } + goto ret0; + + L183: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 43; + } + goto ret0; + + L197: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) != FIX) + goto ret0; + switch (GET_MODE (x2)) + { + case SFmode: + goto L198; + case DFmode: + goto L213; + } + goto ret0; + + L198: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 46; + } + goto ret0; + + L213: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 49; + } + goto ret0; + + L256: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + switch (GET_CODE (x2)) + { + case REG: + if (XINT (x2, 0) == 16 && 1) + goto L257; + if (XINT (x2, 0) == 17 && 1) + goto L262; + } + } + L266: + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L267; + } + goto L681; + + L257: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[1]) == CONST_INT) + return 59; + } + x2 = XEXP (x1, 0); + goto L266; + + L262: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[1] = x2; + if (GET_CODE (operands[1]) == CONST_INT) + return 60; + } + x2 = XEXP (x1, 0); + goto L266; + + L267: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 61; + } + goto L681; + + L308: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L309; + } + goto L681; + + L309: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 69; + } + goto L681; + + L345: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L346; + } + goto L681; + + L346: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 76; + } + goto L681; + + L377: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L378; + } + goto ret0; + + L378: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 82; + } + goto ret0; + + L410: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L411; + } + goto ret0; + + L411: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 88; + } + goto ret0; + + L458: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NOT && 1) + goto L459; + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L444; + } + goto ret0; + + L459: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L460; + } + goto ret0; + + L460: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 97; + } + goto ret0; + + L444: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 94; + } + goto ret0; + + L476: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L477; + } + goto ret0; + + L477: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 100; + } + goto ret0; + + L697: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == ASHIFT && 1) + goto L698; + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L492; + } + goto ret0; + + L698: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 1 && 1) + goto L699; + goto ret0; + + L699: + x3 = XEXP (x2, 1); + if (general_operand (x3, SImode)) + { + ro[1] = x3; + goto L700; + } + goto ret0; + + L700: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 153; + goto ret0; + + L492: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 103; + } + goto ret0; + + L514: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 108; + } + goto ret0; + + L526: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 111; + } + goto ret0; + + L538: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L539; + } + goto ret0; + + L539: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 114; + } + goto ret0; + + L553: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L559; + } + goto ret0; + + L559: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L560; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 118; + } + goto ret0; + + L560: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 119; + } + goto ret0; + + L586: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L587; + } + goto ret0; + + L587: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 126; + } + goto ret0; + + L601: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L607; + } + goto ret0; + + L607: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L608; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 130; + } + goto ret0; + + L608: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 131; + } + goto ret0; + + L634: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L635; + } + goto ret0; + + L635: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 138; + } + goto ret0; + + L649: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L655; + } + goto ret0; + + L655: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L656; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 142; + } + goto ret0; + + L656: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 143; + } + goto ret0; + + L718: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (register_operand (x2, SImode)) + { + ro[1] = x2; + goto L719; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L731; + } + } + goto ret0; + + L719: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + goto L720; + } + goto ret0; + + L720: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[3] = x2; + if ((INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) + && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)) + return 156; + } + L726: + if (general_operand (x2, SImode)) + { + ro[3] = x2; + return 157; + } + goto ret0; + + L731: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[2] = x2; + goto L732; + } + goto ret0; + + L732: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[3] = x2; + return 158; + } + goto ret0; + ret0: return -1; +} + +int +recog_2 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case HImode: + switch (GET_CODE (x1)) + { + case TRUNCATE: + goto L97; + case SIGN_EXTEND: + goto L109; + case ZERO_EXTEND: + goto L129; + case FIX: + goto L162; + case UNSIGNED_FIX: + goto L192; + case PLUS: + goto L271; + case MINUS: + goto L313; + case MULT: + goto L350; + case DIV: + goto L382; + case MOD: + goto L415; + case AND: + goto L464; + case IOR: + goto L481; + case XOR: + goto L496; + case NEG: + goto L518; + case NOT: + goto L530; + case ASHIFT: + goto L543; + case ASHIFTRT: + goto L564; + case LSHIFT: + goto L591; + case LSHIFTRT: + goto L612; + case ROTATE: + goto L639; + case ROTATERT: + goto L660; + } + } + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 16; + } + goto ret0; + + L97: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + return 23; + } + goto ret0; + + L109: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 26; + } + goto ret0; + + L129: + x2 = XEXP (x1, 0); + if (nonimmediate_operand (x2, QImode)) + { + ro[1] = x2; + return 31; + } + goto ret0; + + L162: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SFmode: + switch (GET_CODE (x2)) + { + case FIX: + goto L163; + } + break; + case DFmode: + if (GET_CODE (x2) == FIX && 1) + goto L178; + } + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 51; + } + L233: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 54; + } + goto ret0; + + L163: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 39; + } + goto ret0; + + L178: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 42; + } + goto ret0; + + L192: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) != FIX) + goto ret0; + switch (GET_MODE (x2)) + { + case SFmode: + goto L193; + case DFmode: + goto L208; + } + goto ret0; + + L193: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 45; + } + goto ret0; + + L208: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 48; + } + goto ret0; + + L271: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L272; + } + goto ret0; + + L272: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 62; + } + goto ret0; + + L313: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L314; + } + goto ret0; + + L314: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 70; + } + goto ret0; + + L350: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L351; + } + goto ret0; + + L351: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 77; + } + goto ret0; + + L382: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L383; + } + goto ret0; + + L383: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 83; + } + goto ret0; + + L415: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L416; + } + goto ret0; + + L416: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 89; + } + goto ret0; + + L464: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == NOT && 1) + goto L465; + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L449; + } + goto ret0; + + L465: + x3 = XEXP (x2, 0); + if (general_operand (x3, HImode)) + { + ro[1] = x3; + goto L466; + } + goto ret0; + + L466: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 98; + } + goto ret0; + + L449: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 95; + } + goto ret0; + + L481: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L482; + } + goto ret0; + + L482: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 101; + } + goto ret0; + + L496: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L497; + } + goto ret0; + + L497: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 104; + } + goto ret0; + + L518: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 109; + } + goto ret0; + + L530: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 112; + } + goto ret0; + + L543: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L544; + } + goto ret0; + + L544: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 115; + } + goto ret0; + + L564: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L570; + } + goto ret0; + + L570: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L571; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 121; + } + goto ret0; + + L571: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 122; + } + goto ret0; + + L591: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L592; + } + goto ret0; + + L592: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 127; + } + goto ret0; + + L612: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L618; + } + goto ret0; + + L618: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L619; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 133; + } + goto ret0; + + L619: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 134; + } + goto ret0; + + L639: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L640; + } + goto ret0; + + L640: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 139; + } + goto ret0; + + L660: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L666; + } + goto ret0; + + L666: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L667; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 145; + } + goto ret0; + + L667: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 146; + } + goto ret0; + ret0: return -1; +} + +int +recog_3 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + int tem; + + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case QImode: + switch (GET_CODE (x1)) + { + case TRUNCATE: + goto L93; + case FIX: + goto L157; + case UNSIGNED_FIX: + goto L187; + case PLUS: + goto L282; + case MINUS: + goto L324; + case MULT: + goto L355; + case DIV: + goto L387; + case MOD: + goto L420; + case AND: + goto L470; + case IOR: + goto L486; + case XOR: + goto L704; + case NEG: + goto L522; + case NOT: + goto L534; + case ASHIFT: + goto L548; + case ASHIFTRT: + goto L575; + case LSHIFT: + goto L596; + case LSHIFTRT: + goto L623; + case ROTATE: + goto L644; + case ROTATERT: + goto L671; + } + } + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 18; + } + goto ret0; + + L93: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[1] = x2; + return 22; + } + break; + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[1] = x2; + return 24; + } + } + goto ret0; + + L157: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SFmode: + switch (GET_CODE (x2)) + { + case FIX: + goto L158; + } + break; + case DFmode: + if (GET_CODE (x2) == FIX && 1) + goto L173; + } + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 50; + } + L229: + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 53; + } + goto ret0; + + L158: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 38; + } + goto ret0; + + L173: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 41; + } + goto ret0; + + L187: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) != FIX) + goto ret0; + switch (GET_MODE (x2)) + { + case SFmode: + goto L188; + case DFmode: + goto L203; + } + goto ret0; + + L188: + x3 = XEXP (x2, 0); + if (general_operand (x3, SFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 44; + } + goto ret0; + + L203: + x3 = XEXP (x2, 0); + if (general_operand (x3, DFmode)) + { + ro[1] = x3; + if (TARGET_32081) + return 47; + } + goto ret0; + + L282: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L283; + } + goto ret0; + + L283: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 64; + } + goto ret0; + + L324: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L325; + } + goto ret0; + + L325: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 72; + } + goto ret0; + + L355: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L356; + } + goto ret0; + + L356: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 78; + } + goto ret0; + + L387: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L388; + } + goto ret0; + + L388: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 84; + } + goto ret0; + + L420: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L421; + } + goto ret0; + + L421: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 90; + } + goto ret0; + + L470: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == NOT && 1) + goto L471; + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L454; + } + goto ret0; + + L471: + x3 = XEXP (x2, 0); + if (general_operand (x3, QImode)) + { + ro[1] = x3; + goto L472; + } + goto ret0; + + L472: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 99; + } + goto ret0; + + L454: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 96; + } + goto ret0; + + L486: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L487; + } + goto ret0; + + L487: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 102; + } + goto ret0; + + L704: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L705; + L501: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L502; + } + goto ret0; + + L705: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == SImode && GET_CODE (x3) == ASHIFT && 1) + goto L706; + goto L501; + + L706: + x4 = XEXP (x3, 0); + if (GET_CODE (x4) == CONST_INT && XWINT (x4, 0) == 1 && 1) + goto L707; + goto L501; + + L707: + x4 = XEXP (x3, 1); + if (general_operand (x4, QImode)) + { + ro[1] = x4; + goto L708; + } + goto L501; + + L708: + x2 = XEXP (x1, 1); + if (rtx_equal_p (x2, ro[0]) && 1) + return 154; + x2 = XEXP (x1, 0); + goto L501; + + L502: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 105; + } + goto ret0; + + L522: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 110; + } + goto ret0; + + L534: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 113; + } + goto ret0; + + L548: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L549; + } + goto ret0; + + L549: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 116; + } + goto ret0; + + L575: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L581; + } + goto ret0; + + L581: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L582; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 124; + } + goto ret0; + + L582: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 125; + } + goto ret0; + + L596: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L597; + } + goto ret0; + + L597: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 128; + } + goto ret0; + + L623: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L629; + } + goto ret0; + + L629: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L630; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 136; + } + goto ret0; + + L630: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 137; + } + goto ret0; + + L644: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L645; + } + goto ret0; + + L645: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 140; + } + goto ret0; + + L671: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L677; + } + goto ret0; + + L677: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == NEG && 1) + goto L678; + if (immediate_operand (x2, SImode)) + { + ro[2] = x2; + return 148; + } + goto ret0; + + L678: + x3 = XEXP (x2, 0); + if (general_operand (x3, SImode)) + { + ro[2] = x3; + return 149; + } + goto ret0; + ret0: return -1; +} + +int +recog_4 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + int tem; + + x1 = XEXP (x0, 1); + x2 = XEXP (x1, 0); + switch (GET_CODE (x2)) + { + case EQ: + goto L759; + case NE: + goto L768; + case GT: + goto L777; + case GTU: + goto L786; + case LT: + goto L795; + case LTU: + goto L804; + case GE: + goto L813; + case GEU: + goto L822; + case LE: + goto L831; + case LEU: + goto L840; + } + goto ret0; + + L759: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L760; + goto ret0; + + L760: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L761; + goto ret0; + + L761: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L762; + case PC: + goto L852; + } + goto ret0; + + L762: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L763; + + L763: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 163; + goto ret0; + + L852: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L853; + goto ret0; + + L853: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 173; + + L768: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L769; + goto ret0; + + L769: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L770; + goto ret0; + + L770: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L771; + case PC: + goto L861; + } + goto ret0; + + L771: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L772; + + L772: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 164; + goto ret0; + + L861: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L862; + goto ret0; + + L862: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 174; + + L777: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L778; + goto ret0; + + L778: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L779; + goto ret0; + + L779: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L780; + case PC: + goto L870; + } + goto ret0; + + L780: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L781; + + L781: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 165; + goto ret0; + + L870: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L871; + goto ret0; + + L871: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 175; + + L786: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L787; + goto ret0; + + L787: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L788; + goto ret0; + + L788: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L789; + case PC: + goto L879; + } + goto ret0; + + L789: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L790; + + L790: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 166; + goto ret0; + + L879: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L880; + goto ret0; + + L880: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 176; + + L795: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L796; + goto ret0; + + L796: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L797; + goto ret0; + + L797: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L798; + case PC: + goto L888; + } + goto ret0; + + L798: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L799; + + L799: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 167; + goto ret0; + + L888: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L889; + goto ret0; + + L889: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 177; + + L804: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L805; + goto ret0; + + L805: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L806; + goto ret0; + + L806: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L807; + case PC: + goto L897; + } + goto ret0; + + L807: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L808; + + L808: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 168; + goto ret0; + + L897: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L898; + goto ret0; + + L898: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 178; + + L813: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L814; + goto ret0; + + L814: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L815; + goto ret0; + + L815: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L816; + case PC: + goto L906; + } + goto ret0; + + L816: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L817; + + L817: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 169; + goto ret0; + + L906: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L907; + goto ret0; + + L907: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 179; + + L822: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L823; + goto ret0; + + L823: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L824; + goto ret0; + + L824: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L825; + case PC: + goto L915; + } + goto ret0; + + L825: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L826; + + L826: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 170; + goto ret0; + + L915: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L916; + goto ret0; + + L916: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 180; + + L831: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L832; + goto ret0; + + L832: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L833; + goto ret0; + + L833: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L834; + case PC: + goto L924; + } + goto ret0; + + L834: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L835; + + L835: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 171; + goto ret0; + + L924: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L925; + goto ret0; + + L925: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 181; + + L840: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == CC0 && 1) + goto L841; + goto ret0; + + L841: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && XWINT (x3, 0) == 0 && 1) + goto L842; + goto ret0; + + L842: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case LABEL_REF: + goto L843; + case PC: + goto L933; + } + goto ret0; + + L843: + x3 = XEXP (x2, 0); + ro[0] = x3; + goto L844; + + L844: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == PC && 1) + return 172; + goto ret0; + + L933: + x2 = XEXP (x1, 2); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L934; + goto ret0; + + L934: + x3 = XEXP (x2, 0); + ro[0] = x3; + return 182; + ret0: return -1; +} + +int +recog_5 (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + int tem; + + x1 = XEXP (x0, 0); + switch (GET_MODE (x1)) + { + case DFmode: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + goto L116; + } + break; + case SFmode: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + goto L120; + } + break; + case TImode: + if (memory_operand (x1, TImode)) + { + ro[0] = x1; + goto L48; + } + break; + case DImode: + if (general_operand (x1, DImode)) + { + ro[0] = x1; + goto L359; + } + break; + case SImode: + switch (GET_CODE (x1)) + { + case REG: + if (XINT (x1, 0) == 17 && 1) + goto L250; + break; + case ZERO_EXTRACT: + goto L684; + } + L56: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L104; + } + L390: + if (register_operand (x1, SImode)) + { + ro[0] = x1; + goto L391; + } + break; + case HImode: + if (general_operand (x1, HImode)) + { + ro[0] = x1; + goto L96; + } + L396: + if (register_operand (x1, HImode)) + { + ro[0] = x1; + goto L397; + } + break; + case QImode: + if (general_operand (x1, QImode)) + { + ro[0] = x1; + goto L92; + } + L402: + if (register_operand (x1, QImode)) + { + ro[0] = x1; + goto L403; + } + } + switch (GET_CODE (x1)) + { + case CC0: + goto L2; + case STRICT_LOW_PART: + goto L63; + case PC: + goto L753; + } + L969: + ro[0] = x1; + goto L970; + L977: + switch (GET_MODE (x1)) + { + case SFmode: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + goto L978; + } + break; + case DFmode: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + goto L982; + } + break; + case SImode: + if (general_operand (x1, SImode)) + { + ro[0] = x1; + goto L986; + } + break; + case HImode: + if (general_operand (x1, HImode)) + { + ro[0] = x1; + goto L990; + } + break; + case QImode: + if (general_operand (x1, QImode)) + { + ro[0] = x1; + goto L994; + } + } + if (GET_CODE (x1) == PC && 1) + goto L999; + goto ret0; + + L116: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case DFmode: + switch (GET_CODE (x1)) + { + case FLOAT_EXTEND: + goto L117; + case FLOAT: + goto L141; + case PLUS: + goto L241; + case MINUS: + goto L293; + case MULT: + goto L335; + case DIV: + goto L367; + case NEG: + goto L506; + } + } + if (general_operand (x1, DFmode)) + { + ro[1] = x1; + return 10; + } + x1 = XEXP (x0, 0); + goto L969; + + L117: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 28; + } + x1 = XEXP (x0, 0); + goto L969; + + L141: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_32081) + return 34; + } + L149: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_32081) + return 36; + } + x1 = XEXP (x0, 0); + goto L969; + + L241: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L242; + } + x1 = XEXP (x0, 0); + goto L969; + + L242: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 56; + } + x1 = XEXP (x0, 0); + goto L969; + + L293: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L294; + } + x1 = XEXP (x0, 0); + goto L969; + + L294: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 66; + } + x1 = XEXP (x0, 0); + goto L969; + + L335: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L336; + } + x1 = XEXP (x0, 0); + goto L969; + + L336: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 74; + } + x1 = XEXP (x0, 0); + goto L969; + + L367: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + goto L368; + } + x1 = XEXP (x0, 0); + goto L969; + + L368: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 80; + } + x1 = XEXP (x0, 0); + goto L969; + + L506: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 106; + } + x1 = XEXP (x0, 0); + goto L969; + + L120: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SFmode: + switch (GET_CODE (x1)) + { + case FLOAT_TRUNCATE: + goto L121; + case FLOAT: + goto L137; + case PLUS: + goto L246; + case MINUS: + goto L298; + case MULT: + goto L340; + case DIV: + goto L372; + case NEG: + goto L510; + } + } + if (general_operand (x1, SFmode)) + { + ro[1] = x1; + return 11; + } + x1 = XEXP (x0, 0); + goto L969; + + L121: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 29; + } + x1 = XEXP (x0, 0); + goto L969; + + L137: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + if (TARGET_32081) + return 33; + } + L145: + if (general_operand (x2, HImode)) + { + ro[1] = x2; + if (TARGET_32081) + return 35; + } + L153: + if (general_operand (x2, QImode)) + { + ro[1] = x2; + if (TARGET_32081) + return 37; + } + x1 = XEXP (x0, 0); + goto L969; + + L246: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L247; + } + x1 = XEXP (x0, 0); + goto L969; + + L247: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 57; + } + x1 = XEXP (x0, 0); + goto L969; + + L298: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L299; + } + x1 = XEXP (x0, 0); + goto L969; + + L299: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 67; + } + x1 = XEXP (x0, 0); + goto L969; + + L340: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L341; + } + x1 = XEXP (x0, 0); + goto L969; + + L341: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 75; + } + x1 = XEXP (x0, 0); + goto L969; + + L372: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + goto L373; + } + x1 = XEXP (x0, 0); + goto L969; + + L373: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[2] = x2; + if (TARGET_32081) + return 81; + } + x1 = XEXP (x0, 0); + goto L969; + + L510: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 107; + } + x1 = XEXP (x0, 0); + goto L969; + + L48: + x1 = XEXP (x0, 1); + if (memory_operand (x1, TImode)) + { + ro[1] = x1; + return 12; + } + x1 = XEXP (x0, 0); + goto L969; + + L359: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == DImode && GET_CODE (x1) == MULT && 1) + goto L360; + if (general_operand (x1, DImode)) + { + ro[1] = x1; + return 13; + } + x1 = XEXP (x0, 0); + goto L969; + + L360: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == DImode && GET_CODE (x2) == ZERO_EXTEND && 1) + goto L361; + x1 = XEXP (x0, 0); + goto L969; + + L361: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SImode)) + { + ro[1] = x3; + goto L362; + } + x1 = XEXP (x0, 0); + goto L969; + + L362: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) == DImode && GET_CODE (x2) == ZERO_EXTEND && 1) + goto L363; + x1 = XEXP (x0, 0); + goto L969; + + L363: + x3 = XEXP (x2, 0); + if (nonimmediate_operand (x3, SImode)) + { + ro[2] = x3; + return 79; + } + x1 = XEXP (x0, 0); + goto L969; + + L250: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L251; + case MINUS: + goto L303; + } + } + if (general_operand (x1, SImode)) + { + ro[0] = x1; + return 14; + } + x1 = XEXP (x0, 0); + goto L56; + + L251: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 17 && 1) + goto L252; + x1 = XEXP (x0, 0); + goto L56; + + L252: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[0] = x2; + if (GET_CODE (operands[0]) == CONST_INT) + return 58; + } + x1 = XEXP (x0, 0); + goto L56; + + L303: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 17 && 1) + goto L304; + x1 = XEXP (x0, 0); + goto L56; + + L304: + x2 = XEXP (x1, 1); + if (immediate_operand (x2, SImode)) + { + ro[0] = x2; + if (GET_CODE (operands[0]) == CONST_INT) + return 68; + } + x1 = XEXP (x0, 0); + goto L56; + + L684: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (general_operand (x2, SImode)) + { + ro[0] = x2; + goto L685; + } + L735: + if (memory_operand (x2, SImode)) + { + ro[0] = x2; + goto L736; + } + L741: + if (register_operand (x2, SImode)) + { + ro[0] = x2; + goto L742; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L748; + } + } + goto L969; + + L685: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 1 && 1) + goto L686; + x2 = XEXP (x1, 0); + goto L735; + + L686: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + goto L687; + } + x2 = XEXP (x1, 0); + goto L735; + + L687: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) != CONST_INT) + { + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L735; + } + if (XWINT (x1, 0) == 1 && 1) + return 151; + if (XWINT (x1, 0) == 0 && 1) + return 152; + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L735; + + L736: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[1] = x2; + goto L737; + } + x2 = XEXP (x1, 0); + goto L741; + + L737: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L738; + } + x2 = XEXP (x1, 0); + goto L741; + + L738: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[3] = x1; + return 159; + } + x1 = XEXP (x0, 0); + x2 = XEXP (x1, 0); + goto L741; + + L742: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[1] = x2; + goto L743; + } + goto L969; + + L743: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L744; + } + goto L969; + + L744: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[3] = x1; + return 160; + } + x1 = XEXP (x0, 0); + goto L969; + + L748: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && 1) + { + ro[1] = x2; + goto L749; + } + goto L969; + + L749: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L750; + } + goto L969; + + L750: + x1 = XEXP (x0, 1); + if (general_operand (x1, SImode)) + { + ro[3] = x1; + return 161; + } + x1 = XEXP (x0, 0); + goto L969; + L104: + tem = recog_1 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L390; + + L391: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SImode) + { + x1 = XEXP (x0, 0); + goto L969; + } + switch (GET_CODE (x1)) + { + case UDIV: + goto L392; + case UMOD: + goto L425; + } + x1 = XEXP (x0, 0); + goto L969; + + L392: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L393; + x1 = XEXP (x0, 0); + goto L969; + + L393: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DImode && reg_or_mem_operand (x3, DImode)) + { + ro[1] = x3; + goto L394; + } + x1 = XEXP (x0, 0); + goto L969; + + L394: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 85; + } + x1 = XEXP (x0, 0); + goto L969; + + L425: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L426; + x1 = XEXP (x0, 0); + goto L969; + + L426: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DImode && reg_or_mem_operand (x3, DImode)) + { + ro[1] = x3; + goto L427; + } + x1 = XEXP (x0, 0); + goto L969; + + L427: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + return 91; + } + x1 = XEXP (x0, 0); + goto L969; + L96: + tem = recog_2 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L396; + + L397: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != HImode) + { + x1 = XEXP (x0, 0); + goto L969; + } + switch (GET_CODE (x1)) + { + case UDIV: + goto L398; + case UMOD: + goto L431; + } + x1 = XEXP (x0, 0); + goto L969; + + L398: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L399; + x1 = XEXP (x0, 0); + goto L969; + + L399: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DImode && reg_or_mem_operand (x3, DImode)) + { + ro[1] = x3; + goto L400; + } + x1 = XEXP (x0, 0); + goto L969; + + L400: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 86; + } + x1 = XEXP (x0, 0); + goto L969; + + L431: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == HImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L432; + x1 = XEXP (x0, 0); + goto L969; + + L432: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DImode && reg_or_mem_operand (x3, DImode)) + { + ro[1] = x3; + goto L433; + } + x1 = XEXP (x0, 0); + goto L969; + + L433: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 92; + } + x1 = XEXP (x0, 0); + goto L969; + L92: + tem = recog_3 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L402; + + L403: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != QImode) + { + x1 = XEXP (x0, 0); + goto L969; + } + switch (GET_CODE (x1)) + { + case UDIV: + goto L404; + case UMOD: + goto L437; + } + x1 = XEXP (x0, 0); + goto L969; + + L404: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L405; + x1 = XEXP (x0, 0); + goto L969; + + L405: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DImode && reg_or_mem_operand (x3, DImode)) + { + ro[1] = x3; + goto L406; + } + x1 = XEXP (x0, 0); + goto L969; + + L406: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 87; + } + x1 = XEXP (x0, 0); + goto L969; + + L437: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == QImode && GET_CODE (x2) == SUBREG && XINT (x2, 1) == 0 && 1) + goto L438; + x1 = XEXP (x0, 0); + goto L969; + + L438: + x3 = XEXP (x2, 0); + if (GET_MODE (x3) == DImode && reg_or_mem_operand (x3, DImode)) + { + ro[1] = x3; + goto L439; + } + x1 = XEXP (x0, 0); + goto L969; + + L439: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 93; + } + x1 = XEXP (x0, 0); + goto L969; + + L2: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case SImode: + if (nonimmediate_operand (x1, SImode)) + { + ro[0] = x1; + return 0; + } + break; + case HImode: + if (nonimmediate_operand (x1, HImode)) + { + ro[0] = x1; + return 1; + } + break; + case QImode: + if (nonimmediate_operand (x1, QImode)) + { + ro[0] = x1; + return 2; + } + } + switch (GET_CODE (x1)) + { + case COMPARE: + goto L18; + case ZERO_EXTRACT: + goto L712; + case CONST_INT: + case CONST_DOUBLE: + case CONST: + case SYMBOL_REF: + case LABEL_REF: + case SUBREG: + case REG: + case MEM: + L11: + if (general_operand (x1, DFmode)) + { + ro[0] = x1; + if (TARGET_32081) + return 3; + } + } + L14: + if (general_operand (x1, SFmode)) + { + ro[0] = x1; + if (TARGET_32081) + return 4; + } + x1 = XEXP (x0, 0); + goto L969; + + L18: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case SImode: + if (nonimmediate_operand (x2, SImode)) + { + ro[0] = x2; + goto L19; + } + break; + case HImode: + if (nonimmediate_operand (x2, HImode)) + { + ro[0] = x2; + goto L24; + } + break; + case QImode: + if (nonimmediate_operand (x2, QImode)) + { + ro[0] = x2; + goto L29; + } + break; + case DFmode: + if (general_operand (x2, DFmode)) + { + ro[0] = x2; + goto L34; + } + break; + case SFmode: + if (general_operand (x2, SFmode)) + { + ro[0] = x2; + goto L39; + } + } + x1 = XEXP (x0, 0); + goto L969; + + L19: + x2 = XEXP (x1, 1); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 5; + } + x1 = XEXP (x0, 0); + goto L969; + + L24: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 6; + } + x1 = XEXP (x0, 0); + goto L969; + + L29: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 7; + } + x1 = XEXP (x0, 0); + goto L969; + + L34: + x2 = XEXP (x1, 1); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 8; + } + x1 = XEXP (x0, 0); + goto L969; + + L39: + x2 = XEXP (x1, 1); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 9; + } + x1 = XEXP (x0, 0); + goto L969; + + L712: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && general_operand (x2, SImode)) + { + ro[0] = x2; + goto L713; + } + x1 = XEXP (x0, 0); + goto L969; + + L713: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 1 && 1) + goto L714; + x1 = XEXP (x0, 0); + goto L969; + + L714: + x2 = XEXP (x1, 2); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 155; + } + x1 = XEXP (x0, 0); + goto L969; + + L63: + x2 = XEXP (x1, 0); + switch (GET_MODE (x2)) + { + case HImode: + if (general_operand (x2, HImode)) + { + ro[0] = x2; + goto L276; + } + break; + case QImode: + if (general_operand (x2, QImode)) + { + ro[0] = x2; + goto L287; + } + } + goto L969; + + L276: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case HImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L277; + case MINUS: + goto L319; + } + } + if (general_operand (x1, HImode)) + { + ro[1] = x1; + return 17; + } + x1 = XEXP (x0, 0); + goto L969; + + L277: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L278; + } + x1 = XEXP (x0, 0); + goto L969; + + L278: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 63; + } + x1 = XEXP (x0, 0); + goto L969; + + L319: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + goto L320; + } + x1 = XEXP (x0, 0); + goto L969; + + L320: + x2 = XEXP (x1, 1); + if (general_operand (x2, HImode)) + { + ro[2] = x2; + return 71; + } + x1 = XEXP (x0, 0); + goto L969; + + L287: + x1 = XEXP (x0, 1); + switch (GET_MODE (x1)) + { + case QImode: + switch (GET_CODE (x1)) + { + case PLUS: + goto L288; + case MINUS: + goto L330; + } + } + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 19; + } + x1 = XEXP (x0, 0); + goto L969; + + L288: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L289; + } + x1 = XEXP (x0, 0); + goto L969; + + L289: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 65; + } + x1 = XEXP (x0, 0); + goto L969; + + L330: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + goto L331; + } + x1 = XEXP (x0, 0); + goto L969; + + L331: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 73; + } + x1 = XEXP (x0, 0); + goto L969; + + L753: + x1 = XEXP (x0, 1); + switch (GET_CODE (x1)) + { + case LABEL_REF: + goto L754; + case IF_THEN_ELSE: + goto L758; + } + x1 = XEXP (x0, 0); + goto L969; + + L754: + x2 = XEXP (x1, 0); + ro[0] = x2; + return 162; + L758: + tem = recog_4 (x0, insn, pnum_clobbers); + if (tem >= 0) return tem; + x1 = XEXP (x0, 0); + goto L969; + + L970: + x1 = XEXP (x0, 1); + if (GET_CODE (x1) == CALL && 1) + goto L971; + x1 = XEXP (x0, 0); + goto L977; + + L971: + x2 = XEXP (x1, 0); + if (memory_operand (x2, QImode)) + { + ro[1] = x2; + goto L972; + } + x1 = XEXP (x0, 0); + goto L977; + + L972: + x2 = XEXP (x1, 1); + if (general_operand (x2, QImode)) + { + ro[2] = x2; + return 186; + } + x1 = XEXP (x0, 0); + goto L977; + + L978: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == SFmode && GET_CODE (x1) == ABS && 1) + goto L979; + goto ret0; + + L979: + x2 = XEXP (x1, 0); + if (general_operand (x2, SFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 190; + } + goto ret0; + + L982: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) == DFmode && GET_CODE (x1) == ABS && 1) + goto L983; + goto ret0; + + L983: + x2 = XEXP (x1, 0); + if (general_operand (x2, DFmode)) + { + ro[1] = x2; + if (TARGET_32081) + return 191; + } + goto ret0; + + L986: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != SImode) + goto ret0; + switch (GET_CODE (x1)) + { + case ABS: + goto L987; + case EQ: + goto L1012; + case NE: + goto L1027; + case GT: + goto L1042; + case GTU: + goto L1057; + case LT: + goto L1072; + case LTU: + goto L1087; + case GE: + goto L1102; + case GEU: + goto L1117; + case LE: + goto L1132; + case LEU: + goto L1147; + } + goto ret0; + + L987: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[1] = x2; + return 192; + } + goto ret0; + + L1012: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1013; + goto ret0; + + L1013: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 198; + goto ret0; + + L1027: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1028; + goto ret0; + + L1028: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 201; + goto ret0; + + L1042: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1043; + goto ret0; + + L1043: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 204; + goto ret0; + + L1057: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1058; + goto ret0; + + L1058: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 207; + goto ret0; + + L1072: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1073; + goto ret0; + + L1073: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 210; + goto ret0; + + L1087: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1088; + goto ret0; + + L1088: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 213; + goto ret0; + + L1102: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1103; + goto ret0; + + L1103: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 216; + goto ret0; + + L1117: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1118; + goto ret0; + + L1118: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 219; + goto ret0; + + L1132: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1133; + goto ret0; + + L1133: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 222; + goto ret0; + + L1147: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1148; + goto ret0; + + L1148: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 225; + goto ret0; + + L990: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != HImode) + goto ret0; + switch (GET_CODE (x1)) + { + case ABS: + goto L991; + case EQ: + goto L1017; + case NE: + goto L1032; + case GT: + goto L1047; + case GTU: + goto L1062; + case LT: + goto L1077; + case LTU: + goto L1092; + case GE: + goto L1107; + case GEU: + goto L1122; + case LE: + goto L1137; + case LEU: + goto L1152; + } + goto ret0; + + L991: + x2 = XEXP (x1, 0); + if (general_operand (x2, HImode)) + { + ro[1] = x2; + return 193; + } + goto ret0; + + L1017: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1018; + goto ret0; + + L1018: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 199; + goto ret0; + + L1032: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1033; + goto ret0; + + L1033: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 202; + goto ret0; + + L1047: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1048; + goto ret0; + + L1048: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 205; + goto ret0; + + L1062: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1063; + goto ret0; + + L1063: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 208; + goto ret0; + + L1077: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1078; + goto ret0; + + L1078: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 211; + goto ret0; + + L1092: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1093; + goto ret0; + + L1093: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 214; + goto ret0; + + L1107: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1108; + goto ret0; + + L1108: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 217; + goto ret0; + + L1122: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1123; + goto ret0; + + L1123: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 220; + goto ret0; + + L1137: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1138; + goto ret0; + + L1138: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 223; + goto ret0; + + L1152: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1153; + goto ret0; + + L1153: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 226; + goto ret0; + + L994: + x1 = XEXP (x0, 1); + if (GET_MODE (x1) != QImode) + goto ret0; + switch (GET_CODE (x1)) + { + case ABS: + goto L995; + case EQ: + goto L1022; + case NE: + goto L1037; + case GT: + goto L1052; + case GTU: + goto L1067; + case LT: + goto L1082; + case LTU: + goto L1097; + case GE: + goto L1112; + case GEU: + goto L1127; + case LE: + goto L1142; + case LEU: + goto L1157; + } + goto ret0; + + L995: + x2 = XEXP (x1, 0); + if (general_operand (x2, QImode)) + { + ro[1] = x2; + return 194; + } + goto ret0; + + L1022: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1023; + goto ret0; + + L1023: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 200; + goto ret0; + + L1037: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1038; + goto ret0; + + L1038: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 203; + goto ret0; + + L1052: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1053; + goto ret0; + + L1053: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 206; + goto ret0; + + L1067: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1068; + goto ret0; + + L1068: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 209; + goto ret0; + + L1082: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1083; + goto ret0; + + L1083: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 212; + goto ret0; + + L1097: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1098; + goto ret0; + + L1098: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 215; + goto ret0; + + L1112: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1113; + goto ret0; + + L1113: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 218; + goto ret0; + + L1127: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1128; + goto ret0; + + L1128: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 221; + goto ret0; + + L1142: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1143; + goto ret0; + + L1143: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 224; + goto ret0; + + L1157: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == CC0 && 1) + goto L1158; + goto ret0; + + L1158: + x2 = XEXP (x1, 1); + if (GET_CODE (x2) == CONST_INT && XWINT (x2, 0) == 0 && 1) + return 227; + goto ret0; + + L999: + x1 = XEXP (x0, 1); + if (register_operand (x1, SImode)) + { + ro[0] = x1; + return 196; + } + goto ret0; + ret0: return -1; +} + +int +recog (x0, insn, pnum_clobbers) + register rtx x0; + rtx insn; + int *pnum_clobbers; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + int tem; + + L0: + switch (GET_CODE (x0)) + { + case SET: + goto L41; + case PARALLEL: + if (XVECLEN (x0, 0) == 5 && 1) + goto L73; + if (XVECLEN (x0, 0) == 2 && 1) + goto L85; + break; + case CALL: + goto L966; + case UNSPEC_VOLATILE: + if (XINT (x0, 1) == 0 && XVECLEN (x0, 0) == 1 && 1) + goto L974; + break; + case RETURN: + if (0) + return 189; + break; + case CONST_INT: + if (XWINT (x0, 0) == 0 && 1) + return 195; + } + goto ret0; + L41: + return recog_5 (x0, insn, pnum_clobbers); + + L73: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L74; + goto ret0; + + L74: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == BLKmode && general_operand (x2, BLKmode)) + { + ro[0] = x2; + goto L75; + } + goto ret0; + + L75: + x2 = XEXP (x1, 1); + if (general_operand (x2, BLKmode)) + { + ro[1] = x2; + goto L76; + } + goto ret0; + + L76: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L77; + goto ret0; + + L77: + x2 = XEXP (x1, 0); + if (general_operand (x2, SImode)) + { + ro[2] = x2; + goto L78; + } + goto ret0; + + L78: + x1 = XVECEXP (x0, 0, 2); + if (GET_CODE (x1) == CLOBBER && 1) + goto L79; + goto ret0; + + L79: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 0 && 1) + goto L80; + goto ret0; + + L80: + x1 = XVECEXP (x0, 0, 3); + if (GET_CODE (x1) == CLOBBER && 1) + goto L81; + goto ret0; + + L81: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 1 && 1) + goto L82; + goto ret0; + + L82: + x1 = XVECEXP (x0, 0, 4); + if (GET_CODE (x1) == CLOBBER && 1) + goto L83; + goto ret0; + + L83: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == SImode && GET_CODE (x2) == REG && XINT (x2, 0) == 2 && 1) + return 21; + goto ret0; + + L85: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == SET && 1) + goto L86; + goto ret0; + + L86: + x2 = XEXP (x1, 0); + if (GET_MODE (x2) == BLKmode && general_operand (x2, BLKmode)) + { + ro[0] = x2; + goto L87; + } + if (GET_CODE (x2) == PC && 1) + goto L1003; + goto ret0; + + L87: + x2 = XEXP (x1, 1); + if (general_operand (x2, BLKmode)) + { + ro[1] = x2; + goto L88; + } + goto ret0; + + L88: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L89; + goto ret0; + + L89: + x2 = XEXP (x1, 0); + if (pnum_clobbers != 0 && general_operand (x2, SImode)) + { + ro[2] = x2; + *pnum_clobbers = 3; + return 21; + } + goto ret0; + + L1003: + x2 = XEXP (x1, 1); + switch (GET_CODE (x2)) + { + case PLUS: + if (GET_MODE (x2) == SImode && 1) + goto L1004; + break; + case IF_THEN_ELSE: + goto L939; + } + goto ret0; + + L1004: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == PC && 1) + goto L1005; + goto ret0; + + L1005: + x3 = XEXP (x2, 1); + if (general_operand (x3, HImode)) + { + ro[0] = x3; + goto L1006; + } + goto ret0; + + L1006: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == USE && 1) + goto L1007; + goto ret0; + + L1007: + x2 = XEXP (x1, 0); + if (GET_CODE (x2) == LABEL_REF && 1) + goto L1008; + goto ret0; + + L1008: + x3 = XEXP (x2, 0); + ro[1] = x3; + return 197; + + L939: + x3 = XEXP (x2, 0); + if (GET_CODE (x3) == NE && 1) + goto L940; + goto ret0; + + L940: + x4 = XEXP (x3, 0); + if (GET_MODE (x4) == SImode && general_operand (x4, SImode)) + { + ro[0] = x4; + goto L941; + } + goto ret0; + + L941: + x4 = XEXP (x3, 1); + if (GET_CODE (x4) == CONST_INT && 1) + { + ro[1] = x4; + goto L942; + } + goto ret0; + + L942: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == LABEL_REF && 1) + goto L943; + goto ret0; + + L943: + x4 = XEXP (x3, 0); + ro[2] = x4; + goto L944; + + L944: + x3 = XEXP (x2, 2); + if (GET_CODE (x3) == PC && 1) + goto L945; + goto ret0; + + L945: + x1 = XVECEXP (x0, 0, 1); + if (GET_CODE (x1) == SET && 1) + goto L946; + goto ret0; + + L946: + x2 = XEXP (x1, 0); + if (rtx_equal_p (x2, ro[0]) && 1) + goto L947; + goto ret0; + + L947: + x2 = XEXP (x1, 1); + if (GET_MODE (x2) != SImode) + goto ret0; + switch (GET_CODE (x2)) + { + case MINUS: + goto L948; + case PLUS: + goto L963; + } + goto ret0; + + L948: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L949; + goto ret0; + + L949: + x3 = XEXP (x2, 1); + if (rtx_equal_p (x3, ro[1]) && 1) + if (INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8) + return 183; + goto ret0; + + L963: + x3 = XEXP (x2, 0); + if (rtx_equal_p (x3, ro[0]) && 1) + goto L964; + goto ret0; + + L964: + x3 = XEXP (x2, 1); + if (GET_CODE (x3) == CONST_INT && 1) + { + ro[3] = x3; + if (INTVAL (operands[1]) == - INTVAL (operands[3]) + && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8) + return 184; + } + goto ret0; + + L966: + x1 = XEXP (x0, 0); + if (memory_operand (x1, QImode)) + { + ro[0] = x1; + goto L967; + } + goto ret0; + + L967: + x1 = XEXP (x0, 1); + if (general_operand (x1, QImode)) + { + ro[1] = x1; + return 185; + } + goto ret0; + + L974: + x1 = XVECEXP (x0, 0, 0); + if (GET_CODE (x1) == CONST_INT && XWINT (x1, 0) == 0 && 1) + return 188; + goto ret0; + ret0: return -1; +} + +rtx +split_insns (x0, insn) + register rtx x0; + rtx insn; +{ + register rtx *ro = &recog_operand[0]; + register rtx x1, x2, x3, x4; + rtx tem; + + goto ret0; + ret0: return 0; +} + diff --git a/gnu/usr.bin/gcc2/arch/ns32k/md b/gnu/usr.bin/gcc2/arch/ns32k/md new file mode 100644 index 000000000000..dd0c21f07d4a --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/md @@ -0,0 +1,2599 @@ +; BUGS: +;; Insert no-op between an insn with memory read-write operands +;; following by a scale-indexing operation. +;; The Sequent assembler does not allow addresses to be used +;; except in insns which explicitly compute an effective address. +;; I.e., one cannot say "cmpd _p,@_x" +;; Implement unsigned multiplication?? + +;;- Machine description for GNU compiler +;;- ns32000 Version +;; Copyright (C) 1988 Free Software Foundation, Inc. +;; Contributed by Michael Tiemann (tiemann@mcc.com) + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. + + +;;- Instruction patterns. When multiple patterns apply, +;;- the first one in the file is chosen. +;;- +;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. +;;- +;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code +;;- updates for most instructions. + +;; We don't want to allow a constant operand for test insns because +;; (set (cc0) (const_int foo)) has no mode information. Such insns will +;; be folded while optimizing anyway. + +(define_insn "tstsi" + [(set (cc0) + (match_operand:SI 0 "nonimmediate_operand" "rm"))] + "" + "* +{ cc_status.flags |= CC_REVERSED; + operands[1] = const0_rtx; + return \"cmpqd %1,%0\"; }") + +(define_insn "tsthi" + [(set (cc0) + (match_operand:HI 0 "nonimmediate_operand" "g"))] + "" + "* +{ cc_status.flags |= CC_REVERSED; + operands[1] = const0_rtx; + return \"cmpqw %1,%0\"; }") + +(define_insn "tstqi" + [(set (cc0) + (match_operand:QI 0 "nonimmediate_operand" "g"))] + "" + "* +{ cc_status.flags |= CC_REVERSED; + operands[1] = const0_rtx; + return \"cmpqb %1,%0\"; }") + +(define_insn "tstdf" + [(set (cc0) + (match_operand:DF 0 "general_operand" "fmF"))] + "TARGET_32081" + "* +{ cc_status.flags |= CC_REVERSED; + operands[1] = CONST0_RTX (DFmode); + return \"cmpl %1,%0\"; }") + +(define_insn "tstsf" + [(set (cc0) + (match_operand:SF 0 "general_operand" "fmF"))] + "TARGET_32081" + "* +{ cc_status.flags |= CC_REVERSED; + operands[1] = CONST0_RTX (SFmode); + return \"cmpf %1,%0\"; }") + +(define_insn "cmpsi" + [(set (cc0) + (compare (match_operand:SI 0 "nonimmediate_operand" "rmn") + (match_operand:SI 1 "general_operand" "rmn")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + int i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + cc_status.flags |= CC_REVERSED; + return \"cmpqd %1,%0\"; + } + } + cc_status.flags &= ~CC_REVERSED; + if (GET_CODE (operands[0]) == CONST_INT) + { + int i = INTVAL (operands[0]); + if (i <= 7 && i >= -8) + return \"cmpqd %0,%1\"; + } + return \"cmpd %0,%1\"; +}") + +(define_insn "cmphi" + [(set (cc0) + (compare (match_operand:HI 0 "nonimmediate_operand" "g") + (match_operand:HI 1 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + short i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + cc_status.flags |= CC_REVERSED; + if (INTVAL (operands[1]) > 7) + operands[1] = gen_rtx(CONST_INT, VOIDmode, i); + return \"cmpqw %1,%0\"; + } + } + cc_status.flags &= ~CC_REVERSED; + if (GET_CODE (operands[0]) == CONST_INT) + { + short i = INTVAL (operands[0]); + if (i <= 7 && i >= -8) + { + if (INTVAL (operands[0]) > 7) + operands[0] = gen_rtx(CONST_INT, VOIDmode, i); + return \"cmpqw %0,%1\"; + } + } + return \"cmpw %0,%1\"; +}") + +(define_insn "cmpqi" + [(set (cc0) + (compare (match_operand:QI 0 "nonimmediate_operand" "g") + (match_operand:QI 1 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + char i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + cc_status.flags |= CC_REVERSED; + if (INTVAL (operands[1]) > 7) + operands[1] = gen_rtx(CONST_INT, VOIDmode, i); + return \"cmpqb %1,%0\"; + } + } + cc_status.flags &= ~CC_REVERSED; + if (GET_CODE (operands[0]) == CONST_INT) + { + char i = INTVAL (operands[0]); + if (i <= 7 && i >= -8) + { + if (INTVAL (operands[0]) > 7) + operands[0] = gen_rtx(CONST_INT, VOIDmode, i); + return \"cmpqb %0,%1\"; + } + } + return \"cmpb %0,%1\"; +}") + +(define_insn "cmpdf" + [(set (cc0) + (compare (match_operand:DF 0 "general_operand" "fmF") + (match_operand:DF 1 "general_operand" "fmF")))] + "TARGET_32081" + "cmpl %0,%1") + +(define_insn "cmpsf" + [(set (cc0) + (compare (match_operand:SF 0 "general_operand" "fmF") + (match_operand:SF 1 "general_operand" "fmF")))] + "TARGET_32081" + "cmpf %0,%1") + +(define_insn "movdf" + [(set (match_operand:DF 0 "general_operand" "=&fg<") + (match_operand:DF 1 "general_operand" "fFg"))] + "" + "* +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) + return \"movl %1,%0\"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"movd %1,tos\", xoperands); + output_asm_insn (\"movd %1,tos\", operands); + return \"movl tos,%0\"; + } + return \"movl %1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"movd tos,%0\"; + } + else + return \"movl %1,%0\"; + } + return output_move_double (operands); +}") + +(define_insn "movsf" + [(set (match_operand:SF 0 "general_operand" "=fg<") + (match_operand:SF 1 "general_operand" "fFg"))] + "" + "* +{ + if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return \"movd %1,tos\;movf tos,%0\"; + else + return \"movf %1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return \"movf %1,tos\;movd tos,%0\"; + return \"movf %1,%0\"; + } +#if 0 /* Someone suggested this for the Sequent. Is it needed? */ + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + return \"movf %1,%0\"; +#endif +/* There was a #if 0 around this, but that was erroneous + for many machines -- rms. */ +#ifndef MOVD_FLOAT_OK + /* GAS understands floating constants in ordinary movd instructions + but other assemblers might object. */ + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + union {int i[2]; float f; double d;} convrt; + convrt.i[0] = CONST_DOUBLE_LOW (operands[1]); + convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]); + convrt.f = convrt.d; + + /* Is there a better machine-independent way to to this? */ + operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]); + return \"movd %1,%0\"; + } +#endif + else return \"movd %1,%0\"; +}") + +(define_insn "" + [(set (match_operand:TI 0 "memory_operand" "=m") + (match_operand:TI 1 "memory_operand" "m"))] + "" + "movmd %1,%0,4") + +(define_insn "movdi" + [(set (match_operand:DI 0 "general_operand" "=&g<,*f,g") + (match_operand:DI 1 "general_operand" "gF,g,*f"))] + "" + "* +{ + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) + return \"movl %1,%0\"; + if (REG_P (operands[1])) + { + rtx xoperands[2]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"movd %1,tos\", xoperands); + output_asm_insn (\"movd %1,tos\", operands); + return \"movl tos,%0\"; + } + return \"movl %1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + { + output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands); + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"movd tos,%0\"; + } + else + return \"movl %1,%0\"; + } + return output_move_double (operands); +}") + +;; This special case must precede movsi. +(define_insn "" + [(set (reg:SI 17) + (match_operand:SI 0 "general_operand" "rmn"))] + "" + "lprd sp,%0") + +(define_insn "movsi" + [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g") + (match_operand:SI 1 "general_operand" "g,?xy,g,*f"))] + "" + "* +{ + if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return \"movd %1,tos\;movf tos,%0\"; + else + return \"movf %1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return \"movf %1,tos\;movd tos,%0\"; + return \"movf %1,%0\"; + } + if (GET_CODE (operands[1]) == CONST_INT) + { + int i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + return \"movqd %1,%0\"; + if (i < 0x4000 && i >= -0x4000 && ! TARGET_32532) +#if defined (GNX_V3) || defined (UTEK_ASM) + return \"addr %c1,%0\"; +#else + return \"addr @%c1,%0\"; +#endif + return \"movd %1,%0\"; + } + else if (GET_CODE (operands[1]) == REG) + { + if (REGNO (operands[1]) < 16) + return \"movd %1,%0\"; + else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM) + { + if (GET_CODE(operands[0]) == REG) + return \"sprd fp,%0\"; + else + return \"addr 0(fp),%0\" ; + } + else if (REGNO (operands[1]) == STACK_POINTER_REGNUM) + { + if (GET_CODE(operands[0]) == REG) + return \"sprd sp,%0\"; + else + return \"addr 0(sp),%0\" ; + } + else abort (); + } + else if (GET_CODE (operands[1]) == MEM) + return \"movd %1,%0\"; + /* Check if this effective address can be + calculated faster by pulling it apart. */ + if (REG_P (operands[0]) + && GET_CODE (operands[1]) == MULT + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && (INTVAL (XEXP (operands[1], 1)) == 2 + || INTVAL (XEXP (operands[1], 1)) == 4)) + { + rtx xoperands[3]; + xoperands[0] = operands[0]; + xoperands[1] = XEXP (operands[1], 0); + xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); + return output_shift_insn (xoperands); + } + return \"addr %a1,%0\"; +}") + +(define_insn "movhi" + [(set (match_operand:HI 0 "general_operand" "=g<,*f,g") + (match_operand:HI 1 "general_operand" "g,g,*f"))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT) + { + short i = INTVAL (operands[1]); + if (i <= 7 && i >= -8) + { + if (INTVAL (operands[1]) > 7) + operands[1] = + gen_rtx (CONST_INT, VOIDmode, i); + return \"movqw %1,%0\"; + } + return \"movw %1,%0\"; + } + else if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return \"movwf %1,tos\;movf tos,%0\"; + else + return \"movwf %1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return \"movf %1,tos\;movd tos,%0\"; + return \"movf %1,%0\"; + } + else + return \"movw %1,%0\"; +}") + +(define_insn "movstricthi" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r")) + (match_operand:HI 1 "general_operand" "g"))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8) + return \"movqw %1,%0\"; + return \"movw %1,%0\"; +}") + +(define_insn "movqi" + [(set (match_operand:QI 0 "general_operand" "=g<,*f,g") + (match_operand:QI 1 "general_operand" "g,g,*f"))] + "" + "* +{ if (GET_CODE (operands[1]) == CONST_INT) + { + char char_val = (char)INTVAL (operands[1]); + if (char_val <= 7 && char_val >= -8) + { + if (INTVAL (operands[1]) > 7) + operands[1] = + gen_rtx (CONST_INT, VOIDmode, char_val); + return \"movqb %1,%0\"; + } + return \"movb %1,%0\"; + } + else if (FP_REG_P (operands[0])) + { + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) + return \"movbf %1,tos\;movf tos,%0\"; + else + return \"movbf %1,%0\"; + } + else if (FP_REG_P (operands[1])) + { + if (REG_P (operands[0])) + return \"movf %1,tos\;movd tos,%0\"; + return \"movf %1,%0\"; + } + else + return \"movb %1,%0\"; +}") + +(define_insn "movstrictqi" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r")) + (match_operand:QI 1 "general_operand" "g"))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9) + return \"movqb %1,%0\"; + return \"movb %1,%0\"; +}") + +;; This is here to accept 4 arguments and pass the first 3 along +;; to the movstrsi1 pattern that really does the work. +(define_expand "movstrsi" + [(set (match_operand:BLK 0 "general_operand" "=g") + (match_operand:BLK 1 "general_operand" "g")) + (use (match_operand:SI 2 "general_operand" "rmn")) + (match_operand 3 "" "")] + "" + " + emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2])); + DONE; +") + +;; The definition of this insn does not really explain what it does, +;; but it should suffice +;; that anything generated as this insn will be recognized as one +;; and that it won't successfully combine with anything. +(define_insn "movstrsi1" + [(set (match_operand:BLK 0 "general_operand" "=g") + (match_operand:BLK 1 "general_operand" "g")) + (use (match_operand:SI 2 "general_operand" "rmn")) + (clobber (reg:SI 0)) + (clobber (reg:SI 1)) + (clobber (reg:SI 2))] + "" + "* +{ + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + abort (); + operands[0] = XEXP (operands[0], 0); + operands[1] = XEXP (operands[1], 0); + if (GET_CODE (operands[0]) == MEM) + if (GET_CODE (operands[1]) == MEM) + output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands); + else + output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands); + else if (GET_CODE (operands[1]) == MEM) + output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands); + else + output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands); + +#ifdef UTEK_ASM + if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); + if ((unsigned) INTVAL (operands[2]) <= 7) + return \"movqd %2,r0\;movsd $0\"; + else + return \"movd %2,r0\;movsd $0\"; + } + else + { + return \"movd %2,r0\;movsb $0\"; + } +#else + if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); + if ((unsigned) INTVAL (operands[2]) <= 7) + return \"movqd %2,r0\;movsd\"; + else + return \"movd %2,r0\;movsd\"; + } + else + { + return \"movd %2,r0\;movsb\"; + } +#endif +}") + +;; Extension and truncation insns. +;; Those for integer source operand +;; are ordered widest source type first. + +(define_insn "truncsiqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))] + "" + "movb %1,%0") + +(define_insn "truncsihi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))] + "" + "movw %1,%0") + +(define_insn "trunchiqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))] + "" + "movb %1,%0") + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] + "" + "movxwd %1,%0") + +(define_insn "extendqihi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] + "" + "movxbw %1,%0") + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] + "" + "movxbd %1,%0") + +(define_insn "extendsfdf2" + [(set (match_operand:DF 0 "general_operand" "=fm<") + (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] + "TARGET_32081" + "movfl %1,%0") + +(define_insn "truncdfsf2" + [(set (match_operand:SF 0 "general_operand" "=fm<") + (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))] + "TARGET_32081" + "movlf %1,%0") + +(define_insn "zero_extendhisi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] + "" + "movzwd %1,%0") + +(define_insn "zero_extendqihi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] + "" + "movzbw %1,%0") + +(define_insn "zero_extendqisi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] + "" + "movzbd %1,%0") + +;; Fix-to-float conversion insns. +;; Note that the ones that start with SImode come first. +;; That is so that an operand that is a CONST_INT +;; (and therefore lacks a specific machine mode). +;; will be recognized as SImode (which is always valid) +;; rather than as QImode or HImode. + +;; Rumor has it that the National part does not correctly convert +;; constant ints to floats. This conversion is therefore disabled. +;; A register must be used to perform the conversion. + +(define_insn "floatsisf2" + [(set (match_operand:SF 0 "general_operand" "=fm<") + (float:SF (match_operand:SI 1 "general_operand" "rm")))] + "TARGET_32081" + "movdf %1,%0") + +(define_insn "floatsidf2" + [(set (match_operand:DF 0 "general_operand" "=fm<") + (float:DF (match_operand:SI 1 "general_operand" "rm")))] + "TARGET_32081" + "movdl %1,%0") + +(define_insn "floathisf2" + [(set (match_operand:SF 0 "general_operand" "=fm<") + (float:SF (match_operand:HI 1 "general_operand" "rm")))] + "TARGET_32081" + "movwf %1,%0") + +(define_insn "floathidf2" + [(set (match_operand:DF 0 "general_operand" "=fm<") + (float:DF (match_operand:HI 1 "general_operand" "rm")))] + "TARGET_32081" + "movwl %1,%0") + +(define_insn "floatqisf2" + [(set (match_operand:SF 0 "general_operand" "=fm<") + (float:SF (match_operand:QI 1 "general_operand" "rm")))] + "TARGET_32081" + "movbf %1,%0") + +; Some assemblers warn that this insn doesn't work. +; Maybe they know something we don't. +;(define_insn "floatqidf2" +; [(set (match_operand:DF 0 "general_operand" "=fm<") +; (float:DF (match_operand:QI 1 "general_operand" "rm")))] +; "TARGET_32081" +; "movbl %1,%0") + +;; Float-to-fix conversion insns. +;; The sequent compiler always generates "trunc" insns. + +(define_insn "fixsfqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncfb %1,%0") + +(define_insn "fixsfhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncfw %1,%0") + +(define_insn "fixsfsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncfd %1,%0") + +(define_insn "fixdfqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] + "TARGET_32081" + "trunclb %1,%0") + +(define_insn "fixdfhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] + "TARGET_32081" + "trunclw %1,%0") + +(define_insn "fixdfsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncld %1,%0") + +;; Unsigned + +(define_insn "fixunssfqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncfb %1,%0") + +(define_insn "fixunssfhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncfw %1,%0") + +(define_insn "fixunssfsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncfd %1,%0") + +(define_insn "fixunsdfqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] + "TARGET_32081" + "trunclb %1,%0") + +(define_insn "fixunsdfhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] + "TARGET_32081" + "trunclw %1,%0") + +(define_insn "fixunsdfsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] + "TARGET_32081" + "truncld %1,%0") + +;;; These are not yet used by GCC +(define_insn "fix_truncsfqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (fix:QI (match_operand:SF 1 "general_operand" "fm")))] + "TARGET_32081" + "truncfb %1,%0") + +(define_insn "fix_truncsfhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (fix:HI (match_operand:SF 1 "general_operand" "fm")))] + "TARGET_32081" + "truncfw %1,%0") + +(define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (fix:SI (match_operand:SF 1 "general_operand" "fm")))] + "TARGET_32081" + "truncfd %1,%0") + +(define_insn "fix_truncdfqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (fix:QI (match_operand:DF 1 "general_operand" "fm")))] + "TARGET_32081" + "trunclb %1,%0") + +(define_insn "fix_truncdfhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (fix:HI (match_operand:DF 1 "general_operand" "fm")))] + "TARGET_32081" + "trunclw %1,%0") + +(define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (fix:SI (match_operand:DF 1 "general_operand" "fm")))] + "TARGET_32081" + "truncld %1,%0") + +;;- All kinds of add instructions. + +(define_insn "adddf3" + [(set (match_operand:DF 0 "general_operand" "=fm") + (plus:DF (match_operand:DF 1 "general_operand" "%0") + (match_operand:DF 2 "general_operand" "fmF")))] + "TARGET_32081" + "addl %2,%0") + + +(define_insn "addsf3" + [(set (match_operand:SF 0 "general_operand" "=fm") + (plus:SF (match_operand:SF 1 "general_operand" "%0") + (match_operand:SF 2 "general_operand" "fmF")))] + "TARGET_32081" + "addf %2,%0") + +(define_insn "" + [(set (reg:SI 17) + (plus:SI (reg:SI 17) + (match_operand:SI 0 "immediate_operand" "i")))] + "GET_CODE (operands[0]) == CONST_INT" + "* +{ +#ifndef SEQUENT_ADJUST_STACK + if (TARGET_32532) + if (INTVAL (operands[0]) == 8) + return \"cmpd tos,tos\"; + if (TARGET_32532 || TARGET_32332) + if (INTVAL (operands[0]) == 4) + return \"cmpqd %$0,tos\"; +#endif + if (! TARGET_32532) + { + if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64) + return \"adjspb %$%n0\"; + else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192) + return \"adjspw %$%n0\"; + } + return \"adjspd %$%n0\"; +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g<") + (plus:SI (reg:SI 16) + (match_operand:SI 1 "immediate_operand" "i")))] + "GET_CODE (operands[1]) == CONST_INT" + "addr %c1(fp),%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g<") + (plus:SI (reg:SI 17) + (match_operand:SI 1 "immediate_operand" "i")))] + "GET_CODE (operands[1]) == CONST_INT" + "addr %c1(sp),%0") + +(define_insn "addsi3" + [(set (match_operand:SI 0 "general_operand" "=g,=g&<") + (plus:SI (match_operand:SI 1 "general_operand" "%0,r") + (match_operand:SI 2 "general_operand" "rmn,n")))] + "" + "* +{ + if (which_alternative == 1) + { + int i = INTVAL (operands[2]); + if (NS32K_DISPLACEMENT_P (i)) + return \"addr %c2(%1),%0\"; + else + return \"movd %1,%0\;addd %2,%0\"; + } + if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 7 && i >= -8) + return \"addqd %2,%0\"; + else if (GET_CODE (operands[0]) == REG + && i < 0x4000 && i >= -0x4000 && ! TARGET_32532) + return \"addr %c2(%0),%0\"; + } + return \"addd %2,%0\"; +}") + +(define_insn "addhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (plus:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + if (i <= 7 && i >= -8) + return \"addqw %2,%0\"; + } + return \"addw %2,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) + (plus:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) + return \"addqw %1,%0\"; + return \"addw %1,%0\"; +}") + +(define_insn "addqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (plus:QI (match_operand:QI 1 "general_operand" "%0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + if (i <= 7 && i >= -8) + return \"addqb %2,%0\"; + } + return \"addb %2,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) + (plus:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) + return \"addqb %1,%0\"; + return \"addb %1,%0\"; +}") + +;;- All kinds of subtract instructions. + +(define_insn "subdf3" + [(set (match_operand:DF 0 "general_operand" "=fm") + (minus:DF (match_operand:DF 1 "general_operand" "0") + (match_operand:DF 2 "general_operand" "fmF")))] + "TARGET_32081" + "subl %2,%0") + +(define_insn "subsf3" + [(set (match_operand:SF 0 "general_operand" "=fm") + (minus:SF (match_operand:SF 1 "general_operand" "0") + (match_operand:SF 2 "general_operand" "fmF")))] + "TARGET_32081" + "subf %2,%0") + +(define_insn "" + [(set (reg:SI 17) + (minus:SI (reg:SI 17) + (match_operand:SI 0 "immediate_operand" "i")))] + "GET_CODE (operands[0]) == CONST_INT" + "* +{ + if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64 + && INTVAL(operands[0]) > -64 && ! TARGET_32532) + return \"adjspb %0\"; + return \"adjspd %0\"; +}") + +(define_insn "subsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (minus:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 8 && i >= -7) + return \"addqd %$%n2,%0\"; + } + return \"subd %2,%0\"; +}") + +(define_insn "subhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (minus:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 8 && i >= -7) + return \"addqw %$%n2,%0\"; + } + return \"subw %2,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) + (minus:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) + return \"addqw %$%n1,%0\"; + return \"subw %1,%0\"; +}") + +(define_insn "subqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (minus:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + int i = INTVAL (operands[2]); + + if (i <= 8 && i >= -7) + return \"addqb %$%n2,%0\"; + } + return \"subb %2,%0\"; +}") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) + (minus:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) + return \"addqb %$%n1,%0\"; + return \"subb %1,%0\"; +}") + +;;- Multiply instructions. + +(define_insn "muldf3" + [(set (match_operand:DF 0 "general_operand" "=fm") + (mult:DF (match_operand:DF 1 "general_operand" "%0") + (match_operand:DF 2 "general_operand" "fmF")))] + "TARGET_32081" + "mull %2,%0") + +(define_insn "mulsf3" + [(set (match_operand:SF 0 "general_operand" "=fm") + (mult:SF (match_operand:SF 1 "general_operand" "%0") + (match_operand:SF 2 "general_operand" "fmF")))] + "TARGET_32081" + "mulf %2,%0") + +(define_insn "mulsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (mult:SI (match_operand:SI 1 "general_operand" "%0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "muld %2,%0") + +(define_insn "mulhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (mult:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "mulw %2,%0") + +(define_insn "mulqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (mult:QI (match_operand:QI 1 "general_operand" "%0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "mulb %2,%0") + +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "general_operand" "=g") + (mult:DI (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "0")) + (zero_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "rmn"))))] + "" + "meid %2,%0") + +;;- Divide instructions. + +(define_insn "divdf3" + [(set (match_operand:DF 0 "general_operand" "=fm") + (div:DF (match_operand:DF 1 "general_operand" "0") + (match_operand:DF 2 "general_operand" "fmF")))] + "TARGET_32081" + "divl %2,%0") + +(define_insn "divsf3" + [(set (match_operand:SF 0 "general_operand" "=fm") + (div:SF (match_operand:SF 1 "general_operand" "0") + (match_operand:SF 2 "general_operand" "fmF")))] + "TARGET_32081" + "divf %2,%0") + +(define_insn "divsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "quod %2,%0") + +(define_insn "divhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (div:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "quow %2,%0") + +(define_insn "divqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (div:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "quob %2,%0") + +(define_insn "udivsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return \"deid %2,%0\;movd %1,%0\"; +}") + +(define_insn "udivhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1); + return \"deiw %2,%0\;movw %1,%0\"; +}") + +(define_insn "udivqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) + (match_operand:QI 2 "general_operand" "g")))] + "" + "* +{ + operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1); + return \"deib %2,%0\;movb %1,%0\"; +}") + +;; Remainder instructions. + +(define_insn "modsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (mod:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "remd %2,%0") + +(define_insn "modhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (mod:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "remw %2,%0") + +(define_insn "modqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (mod:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "remb %2,%0") + +(define_insn "umodsi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "deid %2,%0") + +(define_insn "umodhi3" + [(set (match_operand:HI 0 "register_operand" "=r") + (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) + (match_operand:HI 2 "general_operand" "g")))] + "" + "deiw %2,%0") + +(define_insn "umodqi3" + [(set (match_operand:QI 0 "register_operand" "=r") + (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) + (match_operand:QI 2 "general_operand" "g")))] + "" + "deib %2,%0") + +; This isn't be usable in its current form. +;(define_insn "udivmoddisi4" +; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1) +; (udiv:SI (match_operand:DI 1 "general_operand" "0") +; (match_operand:SI 2 "general_operand" "rmn"))) +; (set (subreg:SI (match_dup 0) 0) +; (umod:SI (match_dup 1) (match_dup 2)))] +; "" +; "deid %2,%0") + +;;- Logical Instructions: AND + +(define_insn "andsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (and:SI (match_operand:SI 1 "general_operand" "%0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + { + if ((INTVAL (operands[2]) | 0xff) == 0xffffffff) + { + if (INTVAL (operands[2]) == 0xffffff00) + return \"movqb %$0,%0\"; + else + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xff); + return \"andb %2,%0\"; + } + } + if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff) + { + if (INTVAL (operands[2]) == 0xffff0000) + return \"movqw %$0,%0\"; + else + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xffff); + return \"andw %2,%0\"; + } + } + } + return \"andd %2,%0\"; +}") + +(define_insn "andhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (and:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) | 0xff) == 0xffffffff) + { + if (INTVAL (operands[2]) == 0xffffff00) + return \"movqb %$0,%0\"; + else + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xff); + return \"andb %2,%0\"; + } + } + return \"andw %2,%0\"; +}") + +(define_insn "andqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (and:QI (match_operand:QI 1 "general_operand" "%0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "andb %2,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn")) + (match_operand:SI 2 "general_operand" "0")))] + "" + "bicd %1,%0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (and:HI (not:HI (match_operand:HI 1 "general_operand" "g")) + (match_operand:HI 2 "general_operand" "0")))] + "" + "bicw %1,%0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (and:QI (not:QI (match_operand:QI 1 "general_operand" "g")) + (match_operand:QI 2 "general_operand" "0")))] + "" + "bicb %1,%0") + +;;- Bit set instructions. + +(define_insn "iorsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (ior:SI (match_operand:SI 1 "general_operand" "%0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) { + if ((INTVAL (operands[2]) & 0xffffff00) == 0) + return \"orb %2,%0\"; + if ((INTVAL (operands[2]) & 0xffff0000) == 0) + return \"orw %2,%0\"; + } + return \"ord %2,%0\"; +}") + +(define_insn "iorhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (ior:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE(operands[2]) == CONST_INT && + (INTVAL(operands[2]) & 0xffffff00) == 0) + return \"orb %2,%0\"; + return \"orw %2,%0\"; +}") + +(define_insn "iorqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (ior:QI (match_operand:QI 1 "general_operand" "%0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "orb %2,%0") + +;;- xor instructions. + +(define_insn "xorsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (xor:SI (match_operand:SI 1 "general_operand" "%0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) { + if ((INTVAL (operands[2]) & 0xffffff00) == 0) + return \"xorb %2,%0\"; + if ((INTVAL (operands[2]) & 0xffff0000) == 0) + return \"xorw %2,%0\"; + } + return \"xord %2,%0\"; +}") + +(define_insn "xorhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (xor:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "g")))] + "" + "* +{ + if (GET_CODE(operands[2]) == CONST_INT && + (INTVAL(operands[2]) & 0xffffff00) == 0) + return \"xorb %2,%0\"; + return \"xorw %2,%0\"; +}") + +(define_insn "xorqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (xor:QI (match_operand:QI 1 "general_operand" "%0") + (match_operand:QI 2 "general_operand" "g")))] + "" + "xorb %2,%0") + +(define_insn "negdf2" + [(set (match_operand:DF 0 "general_operand" "=fm<") + (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] + "TARGET_32081" + "negl %1,%0") + +(define_insn "negsf2" + [(set (match_operand:SF 0 "general_operand" "=fm<") + (neg:SF (match_operand:SF 1 "general_operand" "fmF")))] + "TARGET_32081" + "negf %1,%0") + +(define_insn "negsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (neg:SI (match_operand:SI 1 "general_operand" "rmn")))] + "" + "negd %1,%0") + +(define_insn "neghi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (neg:HI (match_operand:HI 1 "general_operand" "g")))] + "" + "negw %1,%0") + +(define_insn "negqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (neg:QI (match_operand:QI 1 "general_operand" "g")))] + "" + "negb %1,%0") + +(define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (not:SI (match_operand:SI 1 "general_operand" "rmn")))] + "" + "comd %1,%0") + +(define_insn "one_cmplhi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (not:HI (match_operand:HI 1 "general_operand" "g")))] + "" + "comw %1,%0") + +(define_insn "one_cmplqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (not:QI (match_operand:QI 1 "general_operand" "g")))] + "" + "comb %1,%0") + +;; arithmetic left and right shift operations +;; on the 32532 we will always use lshd for arithmetic left shifts, +;; because it is three times faster. Broken programs which +;; use negative shift counts are probably broken differently +;; than elsewhere. + +;; alternative 0 never matches on the 32532 +(define_insn "ashlsi3" + [(set (match_operand:SI 0 "general_operand" "=g,g") + (ashift:SI (match_operand:SI 1 "general_operand" "r,0") + (match_operand:SI 2 "general_operand" "I,rmn")))] + "" + "* +{ if (TARGET_32532) + return \"lshd %2,%0\"; + else + return output_shift_insn (operands); +}") + +(define_insn "ashlhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (ashift:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) == 1) + return \"addw %0,%0\"; + else if (INTVAL (operands[2]) == 2 && !TARGET_32532) + return \"addw %0,%0\;addw %0,%0\"; + } + if (TARGET_32532) + return \"lshw %2,%0\"; + else + return \"ashw %2,%0\"; +}") + +(define_insn "ashlqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (ashift:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) == 1) + return \"addb %0,%0\"; + else if (INTVAL (operands[2]) == 2 && !TARGET_32532) + return \"addb %0,%0\;addb %0,%0\"; + } + if (TARGET_32532) + return \"lshb %2,%0\"; + else + return \"ashb %2,%0\"; +}") + +;; Arithmetic right shift on the 32k works by negating the shift count. +(define_expand "ashrsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "ashd %$%n2,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "ashd %2,%0") + +(define_expand "ashrhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (ashiftrt:HI (match_operand:HI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "ashw %$%n2,%0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "ashw %2,%0") + +(define_expand "ashrqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (ashiftrt:QI (match_operand:QI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "ashb %$%n2,%0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "ashb %2,%0") + +;; logical shift instructions + +(define_insn "lshlsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (lshift:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "lshd %2,%0") + +(define_insn "lshlhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (lshift:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "lshw %2,%0") + +(define_insn "lshlqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (lshift:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "lshb %2,%0") + +;; Logical right shift on the 32k works by negating the shift count. +(define_expand "lshrsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (lshiftrt:SI (match_operand:SI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "lshd %$%n2,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "lshd %2,%0") + +(define_expand "lshrhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (lshiftrt:HI (match_operand:HI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "lshw %$%n2,%0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "lshw %2,%0") + +(define_expand "lshrqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (lshiftrt:QI (match_operand:QI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "lshb %$%n2,%0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "lshb %2,%0") + +;; Rotate instructions + +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (rotate:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "rotd %2,%0") + +(define_insn "rotlhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (rotate:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "rotw %2,%0") + +(define_insn "rotlqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (rotate:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:SI 2 "general_operand" "rmn")))] + "" + "rotb %2,%0") + +;; Right rotate on the 32k works by negating the shift count. +(define_expand "rotrsi3" + [(set (match_operand:SI 0 "general_operand" "=g") + (rotatert:SI (match_operand:SI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (rotatert:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "rotd %$%n2,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g") + (rotatert:SI (match_operand:SI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "rotd %2,%0") + +(define_expand "rotrhi3" + [(set (match_operand:HI 0 "general_operand" "=g") + (rotatert:HI (match_operand:HI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (rotatert:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "rotw %$%n2,%0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g") + (rotatert:HI (match_operand:HI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "rotw %2,%0") + +(define_expand "rotrqi3" + [(set (match_operand:QI 0 "general_operand" "=g") + (rotatert:QI (match_operand:QI 1 "general_operand" "g") + (match_operand:SI 2 "general_operand" "g")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (rotatert:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:SI 2 "immediate_operand" "i")))] + "" + "rotb %$%n2,%0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (rotatert:QI (match_operand:QI 1 "general_operand" "0") + (neg:SI (match_operand:SI 2 "general_operand" "r"))))] + "" + "rotb %2,%0") + +;;- load or push effective address +;; These come after the move, add, and multiply patterns +;; because we don't want pushl $1 turned into pushad 1. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g<") + (match_operand:QI 1 "address_operand" "p"))] + "" + "* +{ + if (REG_P (operands[0]) + && GET_CODE (operands[1]) == MULT + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && (INTVAL (XEXP (operands[1], 1)) == 2 + || INTVAL (XEXP (operands[1], 1)) == 4)) + { + rtx xoperands[3]; + xoperands[0] = operands[0]; + xoperands[1] = XEXP (operands[1], 0); + xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); + return output_shift_insn (xoperands); + } + return \"addr %a1,%0\"; +}") + +;;; Index insns. These are about the same speed as multiply-add counterparts. +;;; but slower then using power-of-2 shifts if we can use them +; +;(define_insn "" +; [(set (match_operand:SI 0 "register_operand" "=r") +; (plus:SI (match_operand:SI 1 "general_operand" "rmn") +; (mult:SI (match_operand:SI 2 "register_operand" "0") +; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))] +; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8" +; "indexd %0,%3,%1") +; +;(define_insn "" +; [(set (match_operand:SI 0 "register_operand" "=r") +; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") +; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1))) +; (match_operand:SI 3 "general_operand" "rmn")))] +; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8" +; "indexd %0,%2,%3") + +;; Set, Clear, and Invert bit + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g") + (const_int 1) + (match_operand:SI 1 "general_operand" "rmn")) + (const_int 1))] + "" + "sbitd %1,%0") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g") + (const_int 1) + (match_operand:SI 1 "general_operand" "rmn")) + (const_int 0))] + "" + "cbitd %1,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "+g") + (xor:SI (ashift:SI (const_int 1) + (match_operand:SI 1 "general_operand" "rmn")) + (match_dup 0)))] + "" + "ibitd %1,%0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g") + (xor:QI (subreg:QI + (ashift:SI (const_int 1) + (match_operand:QI 1 "general_operand" "rmn")) 0) + (match_dup 0)))] + "" + "ibitb %1,%0") + +;; Recognize jbs and jbc instructions. + +(define_insn "" + [(set (cc0) + (zero_extract (match_operand:SI 0 "general_operand" "rm") + (const_int 1) + (match_operand:SI 1 "general_operand" "g")))] + "" + "* +{ cc_status.flags = CC_Z_IN_F; + return \"tbitd %1,%0\"; +}") + +;; extract(base, width, offset) +;; Signed bitfield extraction is not supported in hardware on the +;; NS 32032. It is therefore better to let GCC figure out a +;; good strategy for generating the proper instruction sequence +;; and represent it as rtl. + +;; Optimize the case of extracting a byte or word from a register. +;; Otherwise we must load a register with the offset of the +;; chunk we want, and perform an extract insn (each of which +;; is very expensive). Since we use the stack to do our bit-twiddling +;; we cannot use it for a destination. Perhaps things are fast +;; enough on the 32532 that such hacks are not needed. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=ro") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")))] + "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) + && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)" + "* +{ + output_asm_insn (\"movd %1,tos\", operands); + if (INTVAL (operands[2]) == 16) + { + if (INTVAL (operands[3]) == 8) + output_asm_insn (\"movzwd 1(sp),%0\", operands); + else + output_asm_insn (\"movzwd 2(sp),%0\", operands); + } + else + { + if (INTVAL (operands[3]) == 8) + output_asm_insn (\"movzbd 1(sp),%0\", operands); + else if (INTVAL (operands[3]) == 16) + output_asm_insn (\"movzbd 2(sp),%0\", operands); + else + output_asm_insn (\"movzbd 3(sp),%0\", operands); + } + if (TARGET_32532 || TARGET_32332) + return \"cmpqd %$0,tos\"; + else + return \"adjspb %$-4\"; +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g<") + (zero_extract:SI (match_operand:SI 1 "register_operand" "g") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "general_operand" "rK")))] + "" + "* +{ if (GET_CODE (operands[3]) == CONST_INT) + return \"extsd %1,%0,%3,%2\"; + else return \"extd %3,%1,%0,%2\"; +}") + +(define_insn "extzv" + [(set (match_operand:SI 0 "general_operand" "=g<") + (zero_extract:SI (match_operand:QI 1 "general_operand" "g") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "general_operand" "rK")))] + "" + "* +{ if (GET_CODE (operands[3]) == CONST_INT) + return \"extsd %1,%0,%3,%2\"; + else return \"extd %3,%1,%0,%2\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o") + (match_operand:SI 1 "const_int_operand" "i") + (match_operand:SI 2 "general_operand" "rn")) + (match_operand:SI 3 "general_operand" "rm"))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) >= 8) + { + operands[0] = adj_offsettable_operand (operands[0], + INTVAL (operands[2]) / 8); + operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8); + } + if (INTVAL (operands[1]) <= 8) + return \"inssb %3,%0,%2,%1\"; + else if (INTVAL (operands[1]) <= 16) + return \"inssw %3,%0,%2,%1\"; + else + return \"inssd %3,%0,%2,%1\"; + } + return \"insd %2,%3,%0,%1\"; +}") + +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") + (match_operand:SI 1 "const_int_operand" "i") + (match_operand:SI 2 "general_operand" "rK")) + (match_operand:SI 3 "general_operand" "rm"))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + if (INTVAL (operands[1]) <= 8) + return \"inssb %3,%0,%2,%1\"; + else if (INTVAL (operands[1]) <= 16) + return \"inssw %3,%0,%2,%1\"; + else + return \"inssd %3,%0,%2,%1\"; + return \"insd %2,%3,%0,%1\"; +}") + +(define_insn "insv" + [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g") + (match_operand:SI 1 "const_int_operand" "i") + (match_operand:SI 2 "general_operand" "rK")) + (match_operand:SI 3 "general_operand" "rm"))] + "" + "* +{ if (GET_CODE (operands[2]) == CONST_INT) + if (INTVAL (operands[1]) <= 8) + return \"inssb %3,%0,%2,%1\"; + else if (INTVAL (operands[1]) <= 16) + return \"inssw %3,%0,%2,%1\"; + else + return \"inssd %3,%0,%2,%1\"; + return \"insd %2,%3,%0,%1\"; +}") + + +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + "br %l0") + +(define_insn "beq" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"bfc %l0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"bfs %l0\"; + else return \"beq %l0\"; +}") + +(define_insn "bne" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"bfs %l0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"bfc %l0\"; + else return \"bne %l0\"; +}") + +(define_insn "bgt" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "bgt %l0") + +(define_insn "bgtu" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "bhi %l0") + +(define_insn "blt" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "blt %l0") + +(define_insn "bltu" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "blo %l0") + +(define_insn "bge" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "bge %l0") + +(define_insn "bgeu" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "bhs %l0") + +(define_insn "ble" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "ble %l0") + +(define_insn "bleu" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "bls %l0") + +(define_insn "" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"bfs %l0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"bfc %l0\"; + else return \"bne %l0\"; +}") + +(define_insn "" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"bfc %l0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"bfs %l0\"; + else return \"beq %l0\"; +}") + +(define_insn "" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "ble %l0") + +(define_insn "" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "bls %l0") + +(define_insn "" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "bge %l0") + +(define_insn "" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "bhs %l0") + +(define_insn "" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "blt %l0") + +(define_insn "" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "blo %l0") + +(define_insn "" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "bgt %l0") + +(define_insn "" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "bhi %l0") + +;; Subtract-and-jump and Add-and-jump insns. +;; These can actually be used for adding numbers in the range -8 to 7 + +(define_insn "" + [(set (pc) + (if_then_else + (ne (match_operand:SI 0 "general_operand" "+g") + (match_operand:SI 1 "const_int_operand" "i")) + (label_ref (match_operand 2 "" "")) + (pc))) + (set (match_dup 0) + (minus:SI (match_dup 0) + (match_dup 1)))] + "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8" + "acbd %$%n1,%0,%l2") + +(define_insn "" + [(set (pc) + (if_then_else + (ne (match_operand:SI 0 "general_operand" "+g") + (match_operand:SI 1 "const_int_operand" "i")) + (label_ref (match_operand 2 "" "")) + (pc))) + (set (match_dup 0) + (plus:SI (match_dup 0) + (match_operand:SI 3 "const_int_operand" "i")))] + "INTVAL (operands[1]) == - INTVAL (operands[3]) + && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8" + "acbd %3,%0,%l2") + +(define_insn "call" + [(call (match_operand:QI 0 "memory_operand" "m") + (match_operand:QI 1 "general_operand" "g"))] + "" + "* +{ +#ifndef JSR_ALWAYS + if (GET_CODE (operands[0]) == MEM) + { + rtx temp = XEXP (operands[0], 0); + if (CONSTANT_ADDRESS_P (temp)) + { +#ifdef ENCORE_ASM + return \"bsr %?%0\"; +#else +#ifdef CALL_MEMREF_IMPLICIT + operands[0] = temp; + return \"bsr %0\"; +#else +#ifdef GNX_V3 + return \"bsr %0\"; +#else + return \"bsr %?%a0\"; +#endif +#endif +#endif + } + if (GET_CODE (XEXP (operands[0], 0)) == REG) +#if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT) + return \"jsr %0\"; +#else + return \"jsr %a0\"; +#endif + } +#endif /* not JSR_ALWAYS */ + return \"jsr %0\"; +}") + +(define_insn "call_value" + [(set (match_operand 0 "" "=rf") + (call (match_operand:QI 1 "memory_operand" "m") + (match_operand:QI 2 "general_operand" "g")))] + "" + "* +{ +#ifndef JSR_ALWAYS + if (GET_CODE (operands[1]) == MEM) + { + rtx temp = XEXP (operands[1], 0); + if (CONSTANT_ADDRESS_P (temp)) + { +#ifdef ENCORE_ASM + return \"bsr %?%1\"; +#else +#ifdef CALL_MEMREF_IMPLICIT + operands[1] = temp; + return \"bsr %1\"; +#else +#ifdef GNX_V3 + return \"bsr %1\"; +#else + return \"bsr %?%a1\"; +#endif +#endif +#endif + } + if (GET_CODE (XEXP (operands[1], 0)) == REG) +#if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT) + return \"jsr %1\"; +#else + return \"jsr %a1\"; +#endif + } +#endif /* not JSR_ALWAYS */ + return \"jsr %1\"; +}") + +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + +(define_insn "return" + [(return)] + "0" + "ret 0") + +(define_insn "abssf2" + [(set (match_operand:SF 0 "general_operand" "=fm<") + (abs:SF (match_operand:SF 1 "general_operand" "fmF")))] + "TARGET_32081" + "absf %1,%0") + +(define_insn "absdf2" + [(set (match_operand:DF 0 "general_operand" "=fm<") + (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] + "TARGET_32081" + "absl %1,%0") + +(define_insn "abssi2" + [(set (match_operand:SI 0 "general_operand" "=g<") + (abs:SI (match_operand:SI 1 "general_operand" "rmn")))] + "" + "absd %1,%0") + +(define_insn "abshi2" + [(set (match_operand:HI 0 "general_operand" "=g<") + (abs:HI (match_operand:HI 1 "general_operand" "g")))] + "" + "absw %1,%0") + +(define_insn "absqi2" + [(set (match_operand:QI 0 "general_operand" "=g<") + (abs:QI (match_operand:QI 1 "general_operand" "g")))] + "" + "absb %1,%0") + +(define_insn "nop" + [(const_int 0)] + "" + "nop") + +(define_insn "indirect_jump" + [(set (pc) (match_operand:SI 0 "register_operand" "r"))] + "" + "jump %0") + +;;(define_insn "tablejump" +;; [(set (pc) +;; (plus:SI (match_operand:SI 0 "general_operand" "g") +;; (pc)))] +;; "" +;; "cased %0") + +(define_insn "tablejump" + [(set (pc) + (plus:SI (pc) (match_operand:HI 0 "general_operand" "g"))) + (use (label_ref (match_operand 1 "" "")))] + "" + "* +{ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", + CODE_LABEL_NUMBER (operands[1])); + return \"casew %0\"; +}") + +;;(define_insn "" +;; [(set (pc) +;; (plus:SI (match_operand:QI 0 "general_operand" "g") +;; (pc)))] +;; "" +;; "caseb %0") + +;; Scondi instructions +(define_insn "seq" + [(set (match_operand:SI 0 "general_operand" "=g<") + (eq:SI (cc0) (const_int 0)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"sfcd %0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"sfsd %0\"; + else return \"seqd %0\"; +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (eq:HI (cc0) (const_int 0)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"sfcw %0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"sfsw %0\"; + else return \"seqw %0\"; +}") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (eq:QI (cc0) (const_int 0)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"sfcb %0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"sfsb %0\"; + else return \"seqb %0\"; +}") + +(define_insn "sne" + [(set (match_operand:SI 0 "general_operand" "=g<") + (ne:SI (cc0) (const_int 0)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"sfsd %0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"sfcd %0\"; + else return \"sned %0\"; +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (ne:HI (cc0) (const_int 0)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"sfsw %0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"sfcw %0\"; + else return \"snew %0\"; +}") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (ne:QI (cc0) (const_int 0)))] + "" + "* +{ if (cc_prev_status.flags & CC_Z_IN_F) + return \"sfsb %0\"; + else if (cc_prev_status.flags & CC_Z_IN_NOT_F) + return \"sfcb %0\"; + else return \"sneb %0\"; +}") + +(define_insn "sgt" + [(set (match_operand:SI 0 "general_operand" "=g<") + (gt:SI (cc0) (const_int 0)))] + "" + "sgtd %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (gt:HI (cc0) (const_int 0)))] + "" + "sgtw %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (gt:QI (cc0) (const_int 0)))] + "" + "sgtb %0") + +(define_insn "sgtu" + [(set (match_operand:SI 0 "general_operand" "=g<") + (gtu:SI (cc0) (const_int 0)))] + "" + "shid %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (gtu:HI (cc0) (const_int 0)))] + "" + "shiw %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (gtu:QI (cc0) (const_int 0)))] + "" + "shib %0") + +(define_insn "slt" + [(set (match_operand:SI 0 "general_operand" "=g<") + (lt:SI (cc0) (const_int 0)))] + "" + "sltd %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (lt:HI (cc0) (const_int 0)))] + "" + "sltw %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (lt:QI (cc0) (const_int 0)))] + "" + "sltb %0") + +(define_insn "sltu" + [(set (match_operand:SI 0 "general_operand" "=g<") + (ltu:SI (cc0) (const_int 0)))] + "" + "slod %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (ltu:HI (cc0) (const_int 0)))] + "" + "slow %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (ltu:QI (cc0) (const_int 0)))] + "" + "slob %0") + +(define_insn "sge" + [(set (match_operand:SI 0 "general_operand" "=g<") + (ge:SI (cc0) (const_int 0)))] + "" + "sged %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (ge:HI (cc0) (const_int 0)))] + "" + "sgew %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (ge:QI (cc0) (const_int 0)))] + "" + "sgeb %0") + +(define_insn "sgeu" + [(set (match_operand:SI 0 "general_operand" "=g<") + (geu:SI (cc0) (const_int 0)))] + "" + "shsd %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (geu:HI (cc0) (const_int 0)))] + "" + "shsw %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (geu:QI (cc0) (const_int 0)))] + "" + "shsb %0") + +(define_insn "sle" + [(set (match_operand:SI 0 "general_operand" "=g<") + (le:SI (cc0) (const_int 0)))] + "" + "sled %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (le:HI (cc0) (const_int 0)))] + "" + "slew %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (le:QI (cc0) (const_int 0)))] + "" + "sleb %0") + +(define_insn "sleu" + [(set (match_operand:SI 0 "general_operand" "=g<") + (leu:SI (cc0) (const_int 0)))] + "" + "slsd %0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g<") + (leu:HI (cc0) (const_int 0)))] + "" + "slsw %0") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=g<") + (leu:QI (cc0) (const_int 0)))] + "" + "slsb %0") diff --git a/gnu/usr.bin/gcc2/arch/ns32k/ns32k.h b/gnu/usr.bin/gcc2/arch/ns32k/ns32k.h new file mode 100644 index 000000000000..12b8fa11031f --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/ns32k.h @@ -0,0 +1,1352 @@ +/* Definitions of target machine for GNU compiler. NS32000 version. + Copyright (C) 1988 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@mcc.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* Note that some other tm.h files include this one and then override + many of the definitions that relate to assembler syntax. */ + +extern enum reg_class secondary_reload_class(); + +/* Names to predefine in the preprocessor for this target machine. */ + +#define CPP_PREDEFINES "-Dns32000 -Dunix" + +/* Print subsidiary information on the compiler version in use. */ +#define TARGET_VERSION fprintf (stderr, " (32000, GAS syntax)"); + + +/* ABSOLUTE PREFIX, IMMEDIATE_PREFIX and EXTERNAL_PREFIX can be defined + to cover most NS32k addressing syntax variations. This way we don't + need to redefine long macros in all the tm.h files for just slight + variations in assembler syntax. */ + +#ifndef ABSOLUTE_PREFIX +#define ABSOLUTE_PREFIX '@' +#endif + +#if defined(IMMEDIATE_PREFIX) && IMMEDIATE_PREFIX +#define PUT_IMMEDIATE_PREFIX(FILE) putc(IMMEDIATE_PREFIX, FILE) +#else +#define PUT_IMMEDIATE_PREFIX(FILE) +#endif +#if defined(ABSOLUTE_PREFIX) && ABSOLUTE_PREFIX +#define PUT_ABSOLUTE_PREFIX(FILE) putc(ABSOLUTE_PREFIX, FILE) +#else +#define PUT_ABSOLUTE_PREFIX(FILE) +#endif +#if defined(EXTERNAL_PREFIX) && EXTERNAL_PREFIX +#define PUT_EXTERNAL_PREFIX(FILE) putc(EXTERNAL_PREFIX, FILE) +#else +#define PUT_EXTERNAL_PREFIX(FILE) +#endif + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Macros used in the machine description to test the flags. */ + +/* Compile 32081 insns for floating point (not library calls). */ +#define TARGET_32081 (target_flags & 1) + +/* Compile using rtd insn calling sequence. + This will not work unless you use prototypes at least + for all functions that can take varying numbers of args. */ +#define TARGET_RTD (target_flags & 2) + +/* Compile passing first two args in regs 0 and 1. */ +#define TARGET_REGPARM (target_flags & 4) + +/* Options to select type of CPU, for better optimization. + The output is correct for any kind of 32000 regardless of these options. */ +#define TARGET_32532 (target_flags & 8) +#define TARGET_32332 (target_flags & 16) + +/* Ok to use the static base register (and presume it's 0) */ +#define TARGET_SB ((target_flags & 32) == 0) + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ + { { "32081", 1}, \ + { "soft-float", -1}, \ + { "rtd", 2}, \ + { "nortd", -2}, \ + { "regparm", 4}, \ + { "noregparm", -4}, \ + { "32532", 24}, \ + { "32332", -8}, \ + { "32332", 16}, \ + { "32032", -24}, \ + { "sb", -32}, \ + { "nosb", 32}, \ + { "", TARGET_DEFAULT}} +/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */ + +/* target machine storage layout */ + +/* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. + This is not true on the ns32k. */ +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is not true on the ns32k. */ +#define BYTES_BIG_ENDIAN 0 + +/* Define this if most significant word of a multiword number is lowest + numbered. This is not true on the ns32k. */ +#define WORDS_BIG_ENDIAN 0 + +/* Number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 32000, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD 32 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE 32 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY 32 + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY 32 + +/* Allocation boundary (in *bits*) for the code of a function. */ +#define FUNCTION_BOUNDARY 16 + +/* Alignment of field after `int : 0' in a structure. */ +#define EMPTY_FIELD_BOUNDARY 32 + +/* Every structure's size must be a multiple of this. */ +#define STRUCTURE_SIZE_BOUNDARY 8 + +/* No data type wants to be aligned rounder than this. */ +#define BIGGEST_ALIGNMENT 32 + +/* Set this nonzero if move instructions will actually fail to work + when given unaligned data. National claims that the NS32032 + works without strict alignment, but rumor has it that operands + crossing a page boundary cause unpredictable results. */ +#define STRICT_ALIGNMENT 1 + +/* If bit field type is int, dont let it cross an int, + and give entire struct the alignment of an int. */ +/* Required on the 386 since it doesn't have a full set of bitfield insns. + (There is no signed extv insn.) */ +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* Standard register usage. */ + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. */ +#define FIRST_PSEUDO_REGISTER 18 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the ns32k, these are the FP, SP, (SB and PC are not included here). */ +#define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1} + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ +#define CALL_USED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 0, 0, 0, 0, \ + 1, 1} + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + On the ns32k, all registers are 32 bits long. */ +#define HARD_REGNO_NREGS(REGNO, MODE) \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ +#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok (REGNO, MODE) + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ +#define MODES_TIEABLE_P(MODE1, MODE2) \ + (((MODE1) == DFmode || (MODE1) == DCmode || (MODE1) == DImode) == \ + ((MODE2) == DFmode || (MODE2) == DCmode || (MODE2) == DImode)) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* NS32000 pc is not overloaded on a register. */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 17 + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 16 + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED 0 + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM 16 + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM 1 + +/* Register in which address to store a structure value + is passed to a function. */ +#define STRUCT_VALUE_REGNUM 2 + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + +enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, GEN_AND_FP_REGS, + FRAME_POINTER_REG, STACK_POINTER_REG, + GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES }; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ + {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "GEN_AND_FP_REGS", \ + "FRAME_POINTER_REG", "STACK_POINTER_REG", "GEN_AND_MEM_REGS", "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS {0, 0x00ff, 0xff00, 0xffff, \ + 0x10000, 0x20000, 0x300ff, 0x3ffff } + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +#define REGNO_REG_CLASS(REGNO) \ + ((REGNO) < 8 ? GENERAL_REGS \ + : (REGNO) < 16 ? FLOAT_REGS \ + : (REGNO) == 16 ? FRAME_POINTER_REG \ + : (REGNO) == 17 ? STACK_POINTER_REG \ + : NO_REGS) + +/* The class value for index registers, and the one for base regs. */ + +#define INDEX_REG_CLASS GENERAL_REGS +#define BASE_REG_CLASS GEN_AND_MEM_REGS + +/* Get reg_class from a letter such as appears in the machine description. */ + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'f' ? FLOAT_REGS \ + : (C) == 'x' ? FRAME_POINTER_REG \ + : (C) == 'y' ? STACK_POINTER_REG \ + : NO_REGS) + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + On the ns32k, these letters are used as follows: + + I : Matches integers which are valid shift amounts for scaled indexing. + These are 0, 1, 2, 3 for byte, word, double, and quadword. + Used for matching arithmetic shifts only on 32032 & 32332. + J : Matches integers which fit a "quick" operand. + K : Matches integers 0 to 7 (for inss and exts instructions). + */ + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((VALUE) < 8 && (VALUE) + 8 >= 0 ? \ + ((C) == 'I' ? (!TARGET_32532 && 0 <= (VALUE) && (VALUE) <= 3) : \ + (C) == 'J' ? (VALUE) <= 7 : \ + (C) == 'K' ? 0 <= (VALUE) : 0) : 0) + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. */ + +/* We return GENERAL_REGS instead of GEN_AND_MEM_REGS. + The latter offers no real additional possibilities + and can cause spurious secondary reloading. */ +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + ((CLASS) == GEN_AND_MEM_REGS ? GENERAL_REGS : (CLASS)) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +/* On the 32000, this is the size of MODE in words */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On the 32000, sp@- in a byte insn really pushes a BYTE. */ +#define PUSH_ROUNDING(BYTES) (BYTES) + +/* Offset of first parameter from the argument pointer register value. */ +#define FIRST_PARM_OFFSET(FNDECL) 8 + +/* Value is the number of byte of arguments automatically + popped when returning from a subroutine call. + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. + + On the 32000, the RET insn may be used to pop them if the number + of args is fixed, but if the number is variable then the caller + must pop them all. RET can't be used for library calls now + because the library is compiled with the Unix compiler. + Use of RET is a selectable option, since it is incompatible with + standard Unix calling sequences. If the option is not selected, + the caller must always pop the args. */ + +#define RETURN_POPS_ARGS(FUNTYPE,SIZE) \ + ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) \ + ? (SIZE) : 0) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + +/* On the 32000 the return value is in R0, + or perhaps in F0 is there is fp support. */ + +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + (TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_32081 \ + ? gen_rtx (REG, TYPE_MODE (VALTYPE), 8) \ + : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +/* On the 32000 the return value is in R0, + or perhaps F0 is there is fp support. */ + +#define LIBCALL_VALUE(MODE) \ + (((MODE) == DFmode || (MODE) == SFmode) && TARGET_32081 \ + ? gen_rtx (REG, MODE, 8) \ + : gen_rtx (REG, MODE, 0)) + +/* Define this if PCC uses the nonreentrant convention for returning + structure and union values. */ + +#define PCC_STATIC_STRUCT_RETURN + +/* 1 if N is a possible register number for a function value. + On the 32000, R0 and F0 are the only registers thus used. */ + +#define FUNCTION_VALUE_REGNO_P(N) (((N) & ~8) == 0) + +/* 1 if N is a possible register number for function argument passing. + On the 32000, no registers are used in this way. */ + +#define FUNCTION_ARG_REGNO_P(N) 0 + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + On the ns32k, this is a single integer, which is a number of bytes + of arguments scanned so far. */ + +#define CUMULATIVE_ARGS int + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + On the ns32k, the offset starts at 0. */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + ((CUM) = 0) + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + ((CUM) += ((MODE) != BLKmode \ + ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ + : (int_size_in_bytes (TYPE) + 3) & ~3)) + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +/* On the 32000 all args are pushed, except if -mregparm is specified + then the first two words of arguments are passed in r0, r1. + *NOTE* -mregparm does not work. + It exists only to test register calling conventions. */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ +((TARGET_REGPARM && (CUM) < 8 \ + && 8 < ((CUM) + ((MODE) == BLKmode \ + ? int_size_in_bytes (TYPE) \ + : GET_MODE_SIZE (MODE)))) \ + ? 2 - (CUM) / 4 : 0) + +#ifndef MAIN_FUNCTION_PROLOGUE +#define MAIN_FUNCTION_PROLOGUE +#endif + +/* + * The function prologue for the ns32k is fairly simple. + * If a frame pointer is needed (decided in reload.c ?) then + * we need assembler of the form + * + * # Save the oldframe pointer, set the new frame pointer, make space + * # on the stack and save any general purpose registers necessary + * + * enter [], + * + * movf fn, tos # Save any floating point registers necessary + * . + * . + * + * If a frame pointer is not needed we need assembler of the form + * # Save any general purpose registers necessary + * + * save [] + * + * movf fn, tos # Save any floating point registers necessary + * . + * . + */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) \ +{ register int regno, g_regs_used = 0; \ + int used_regs_buf[8], *bufp = used_regs_buf; \ + int used_fregs_buf[8], *fbufp = used_fregs_buf; \ + extern char call_used_regs[]; \ + MAIN_FUNCTION_PROLOGUE; \ + for (regno = 0; regno < 8; regno++) \ + if (regs_ever_live[regno] \ + && ! call_used_regs[regno]) \ + { \ + *bufp++ = regno; g_regs_used++; \ + } \ + *bufp = -1; \ + for (; regno < 16; regno++) \ + if (regs_ever_live[regno] && !call_used_regs[regno]) { \ + *fbufp++ = regno; \ + } \ + *fbufp = -1; \ + bufp = used_regs_buf; \ + if (frame_pointer_needed) \ + fprintf (FILE, "\tenter ["); \ + else if (g_regs_used) \ + fprintf (FILE, "\tsave ["); \ + while (*bufp >= 0) \ + { \ + fprintf (FILE, "r%d", *bufp++); \ + if (*bufp >= 0) \ + fputc (',', FILE); \ + } \ + if (frame_pointer_needed) \ + fprintf (FILE, "],%d\n", SIZE); \ + else if (g_regs_used) \ + fprintf (FILE, "]\n"); \ + fbufp = used_fregs_buf; \ + while (*fbufp >= 0) \ + { \ + if ((*fbufp & 1) || (fbufp[0] != fbufp[1] - 1)) \ + fprintf (FILE, "\tmovf f%d,tos\n", *fbufp++ - 8); \ + else \ + { \ + fprintf (FILE, "\tmovl f%d,tos\n", fbufp[0] - 8); \ + fbufp += 2; \ + } \ + } \ +} + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. + + THIS DEFINITION FOR THE 32000 IS A GUESS. IT HAS NOT BEEN TESTED. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ + fprintf (FILE, "\taddr LP%d,r0\n\tbsr mcount\n", (LABELNO)) + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. + + We use 0, because using 1 requires hair in FUNCTION_EPILOGUE + that is worse than the stack adjust we could save. */ + +/* #define EXIT_IGNORE_STACK 1 */ + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer, + if EXIT_IGNORE_STACK is nonzero. That doesn't apply here. + + If a frame pointer is needed (decided in reload.c ?) then + we need assembler of the form + + movf tos, fn # Restore any saved floating point registers + . + . + + # Restore any saved general purpose registers, restore the stack + # pointer from the frame pointer, restore the old frame pointer. + exit [] + + If a frame pointer is not needed we need assembler of the form + # Restore any general purpose registers saved + + movf tos, fn # Restore any saved floating point registers + . + . + . + restore [] */ + +#define FUNCTION_EPILOGUE(FILE, SIZE) \ +{ register int regno, g_regs_used = 0, f_regs_used = 0; \ + int used_regs_buf[8], *bufp = used_regs_buf; \ + int used_fregs_buf[8], *fbufp = used_fregs_buf; \ + extern char call_used_regs[]; \ + *fbufp++ = -2; \ + for (regno = 8; regno < 16; regno++) \ + if (regs_ever_live[regno] && !call_used_regs[regno]) { \ + *fbufp++ = regno; f_regs_used++; \ + } \ + fbufp--; \ + for (regno = 0; regno < 8; regno++) \ + if (regs_ever_live[regno] \ + && ! call_used_regs[regno]) \ + { \ + *bufp++ = regno; g_regs_used++; \ + } \ + while (fbufp > used_fregs_buf) \ + { \ + if ((*fbufp & 1) && fbufp[0] == fbufp[-1] + 1) \ + { \ + fprintf (FILE, "\tmovl tos,f%d\n", fbufp[-1] - 8); \ + fbufp -= 2; \ + } \ + else fprintf (FILE, "\tmovf tos,f%d\n", *fbufp-- - 8); \ + } \ + if (frame_pointer_needed) \ + fprintf (FILE, "\texit ["); \ + else if (g_regs_used) \ + fprintf (FILE, "\trestore ["); \ + while (bufp > used_regs_buf) \ + { \ + fprintf (FILE, "r%d", *--bufp); \ + if (bufp > used_regs_buf) \ + fputc (',', FILE); \ + } \ + if (g_regs_used || frame_pointer_needed) \ + fprintf (FILE, "]\n"); \ + if (current_function_pops_args) \ + fprintf (FILE, "\tret %d\n", current_function_pops_args); \ + else fprintf (FILE, "\tret 0\n"); } + +/* Store in the variable DEPTH the initial difference between the + frame pointer reg contents and the stack pointer reg contents, + as of the start of the function body. This depends on the layout + of the fixed parts of the stack frame and on how registers are saved. */ + +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ +{ \ + int regno; \ + int offset = -4; \ + for (regno = 0; regno < 16; regno++) \ + if (regs_ever_live[regno] && ! call_used_regs[regno]) \ + offset += 4; \ + (DEPTH) = offset - get_frame_size (); \ +} + + +/* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + +/* On the 32k, the trampoline looks like this: + addr .,r2 + jump @__trampoline + .int STATIC + .int FUNCTION +Doing trampolines with a library assist function is easier than figuring +out how to do stores to memory in reverse byte order (the way immediate +operands on the 32k are stored). */ + +#define TRAMPOLINE_TEMPLATE(FILE) \ +{ \ + fprintf (FILE, "\taddr .,r2\n" ); \ + fprintf (FILE, "\tjump " ); \ + PUT_ABSOLUTE_PREFIX (FILE); \ + fprintf (FILE, "__trampoline\n" ); \ + ASM_OUTPUT_INT (FILE, const0_rtx); \ + ASM_OUTPUT_INT (FILE, const0_rtx); \ +} + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE 20 + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), CXT); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), FNADDR); \ +} + +/* This is the library routine that is used + to transfer control from the trampoline + to the actual nested function. */ + +/* The function name __transfer_from_trampoline is not actually used. + The function definition just permits use of "asm with operands" + (though the operand list is empty). */ +#define TRANSFER_FROM_TRAMPOLINE \ +void \ +__transfer_from_trampoline () \ +{ \ + asm ("___trampoline:"); \ + asm ("movd 16(r2),tos"); \ + asm ("movd 12(r2),r2"); \ + asm ("ret 0"); \ +} + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_INCREMENT */ +/* #define HAVE_POST_DECREMENT */ + +/* #define HAVE_PRE_DECREMENT */ +/* #define HAVE_PRE_INCREMENT */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +/* note that FP and SP cannot be used as an index. What about PC? */ +#define REGNO_OK_FOR_INDEX_P(REGNO) \ +((REGNO) < 8 || (unsigned)reg_renumber[REGNO] < 8) +#define REGNO_OK_FOR_BASE_P(REGNO) \ +((REGNO) < 8 || (unsigned)reg_renumber[REGNO] < 8 \ + || (REGNO) == FRAME_POINTER_REGNUM || (REGNO) == STACK_POINTER_REGNUM) + +#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) > 7 && REGNO (X) < 16) + +/* Maximum number of registers that can appear in a valid memory address. */ + +#define MAX_REGS_PER_ADDRESS 2 + +/* Recognize any constant value that is a valid address. + This might not work on future ns32k processors as negative + displacements are not officially allowed but a mode reserved + to National. This works on processors up to 32532, though. */ + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST \ + || (GET_CODE (X) == CONST_INT \ + && ((unsigned)INTVAL (X) >= 0xe0000000 \ + || (unsigned)INTVAL (X) < 0x20000000))) + +#define CONSTANT_ADDRESS_NO_LABEL_P(X) \ + (GET_CODE (X) == CONST_INT \ + && ((unsigned)INTVAL (X) >= 0xe0000000 \ + || (unsigned)INTVAL (X) < 0x20000000)) + +/* Return the register class of a scratch register needed to copy IN into + or out of a register in CLASS in MODE. If it can be done directly, + NO_REGS is returned. */ + +#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ + secondary_reload_class (CLASS, MODE, IN) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) 1 + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index + or if it is a pseudo reg. */ +#define REG_OK_FOR_INDEX_P(X) \ + (REGNO (X) < 8 || REGNO (X) >= FIRST_PSEUDO_REGISTER) +/* Nonzero if X is a hard reg that can be used as a base reg + of if it is a pseudo reg. */ +#define REG_OK_FOR_BASE_P(X) (REGNO (X) < 8 || REGNO (X) >= FRAME_POINTER_REGNUM) +/* Nonzero if X is a floating point reg or a pseudo reg. */ + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) + +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ + +/* 1 if X is an address that we could indirect through. */ +/***** NOTE ***** There is a bug in the Sequent assembler which fails + to fixup addressing information for symbols used as offsets + from registers which are not FP or SP (or SB or PC). This + makes _x(fp) valid, while _x(r0) is invalid. */ + +#define INDIRECTABLE_1_ADDRESS_P(X) \ + (CONSTANT_ADDRESS_P (X) \ + || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ + || (GET_CODE (X) == PLUS \ + && GET_CODE (XEXP (X, 0)) == REG \ + && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ + && CONSTANT_ADDRESS_P (XEXP (X, 1)) \ + && (GET_CODE (X) != CONST_INT || NS32K_DISPLACEMENT_P (INTVAL (X))))) + +/* 1 if integer I will fit in a 4 byte displacement field. + Strictly speaking, we can't be sure that a symbol will fit this range. + But, in practice, it always will. */ + +/* idall@eleceng.adelaide.edu.au says that the 32016 and 32032 + can handle the full range of displacements--it is only the addresses + that have a limited range. So the following was deleted: + (((i) <= 16777215 && (i) >= -16777216) + || ((TARGET_32532 || TARGET_32332) && ...)) */ +#define NS32K_DISPLACEMENT_P(i) \ + ((i) < (1 << 29) && (i) >= - (1 << 29)) + +/* Check for frame pointer or stack pointer. */ +#define MEM_REG(X) \ + (GET_CODE (X) == REG && (REGNO (X) ^ 16) < 2) + +/* A memory ref whose address is the FP or SP, with optional integer offset, + or (on certain machines) a constant address. */ +#define INDIRECTABLE_2_ADDRESS_P(X) \ + (GET_CODE (X) == MEM \ + && (((xfoo0 = XEXP (X, 0), MEM_REG (xfoo0)) \ + || (GET_CODE (xfoo0) == PLUS \ + && MEM_REG (XEXP (xfoo0, 0)) \ + && CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1)))) \ + || (TARGET_SB && CONSTANT_ADDRESS_P (xfoo0)))) + +/* Go to ADDR if X is a valid address not using indexing. + (This much is the easy part.) */ +#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ +{ register rtx xfoob = (X); \ + if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \ + if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \ + if (GET_CODE (X) == PLUS) \ + if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \ + if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \ + goto ADDR; \ +} + +/* Go to ADDR if X is a valid address not using indexing. + (This much is the easy part.) */ +#define GO_IF_INDEXING(X, MODE, ADDR) \ +{ register rtx xfoob = (X); \ + if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 0), MODE)) \ + GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 1), ADDR); \ + if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 1), MODE)) \ + GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 0), ADDR); } \ + +#define GO_IF_INDEXABLE_ADDRESS(X, ADDR) \ +{ if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; \ + if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \ +} + +/* 1 if PROD is either a reg times size of mode MODE + or just a reg, if MODE is just one byte. Actually, on the ns32k, + since the index mode is independent of the operand size, + we can match more stuff... + + This macro's expansion uses the temporary variables xfoo0, xfoo1 + and xfoo2 that must be declared in the surrounding context. */ +#define INDEX_TERM_P(PROD, MODE) \ +((GET_CODE (PROD) == REG && REG_OK_FOR_INDEX_P (PROD)) \ + || (GET_CODE (PROD) == MULT \ + && (xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1), \ + (GET_CODE (xfoo1) == CONST_INT \ + && GET_CODE (xfoo0) == REG \ + && FITS_INDEX_RANGE (INTVAL (xfoo1)) \ + && REG_OK_FOR_INDEX_P (xfoo0))))) + +#define FITS_INDEX_RANGE(X) \ + ((xfoo2 = (unsigned)(X)-1), \ + ((xfoo2 < 4 && xfoo2 != 2) || xfoo2 == 7)) + +/* Note that xfoo0, xfoo1, xfoo2 are used in some of the submacros above. */ +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ register rtx xfooy, xfoo0, xfoo1; \ + unsigned xfoo2; \ + xfooy = X; \ + GO_IF_NONINDEXED_ADDRESS (xfooy, ADDR); \ + if (GET_CODE (xfooy) == PLUS) \ + { \ + if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 1)) \ + && GET_CODE (XEXP (xfooy, 0)) == PLUS) \ + xfooy = XEXP (xfooy, 0); \ + else if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 0)) \ + && GET_CODE (XEXP (xfooy, 1)) == PLUS) \ + xfooy = XEXP (xfooy, 1); \ + GO_IF_INDEXING (xfooy, MODE, ADDR); \ + } \ + else if (INDEX_TERM_P (xfooy, MODE)) \ + goto ADDR; \ + else if (GET_CODE (xfooy) == PRE_DEC) \ + if (REGNO (XEXP (xfooy, 0)) == STACK_POINTER_REGNUM) goto ADDR; \ + else abort (); \ +} + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the ns32k, we do nothing */ + +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the ns32k, only predecrement and postincrement address depend thus + (the amount of decrement or increment being the length of the operand). */ + +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ + { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ + goto LABEL;} + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. + Can do SImode, but HI mode is more efficient. */ +#define CASE_VECTOR_MODE HImode + +/* Define this if the tablejump instruction expects the table + to contain offsets from the address of the table. + Do not define this if the table should contain absolute addresses. */ +#define CASE_VECTOR_PC_RELATIVE + +/* Specify the tree operation to be used to convert reals to integers. */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 4 + +/* Define this if zero-extension is slow (more than one real instruction). */ +/* #define SLOW_ZERO_EXTEND */ + +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 0 + +/* Define if shifts truncate the shift count + which implies one can omit a sign-extension or zero-extension + of a shift count. */ +/* #define SHIFT_COUNT_TRUNCATED */ + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE 1 + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode SImode + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* Compute the cost of address ADDRESS. */ + +#define ADDRESS_COST(RTX) calc_address_cost (RTX) + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + if (INTVAL (RTX) <= 7 && INTVAL (RTX) >= -8) return 0; \ + if (INTVAL (RTX) < 0x4000 && INTVAL (RTX) >= -0x4000) \ + return 1; \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return 3; \ + case CONST_DOUBLE: \ + return 5; + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). */ + +/* This bit means that what ought to be in the Z bit + should be tested in the F bit. */ +#define CC_Z_IN_F 04000 + +/* This bit means that what ought to be in the Z bit + is complemented in the F bit. */ +#define CC_Z_IN_NOT_F 010000 + +/* Store in cc_status the expressions + that the condition codes will describe + after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +#define NOTICE_UPDATE_CC(EXP, INSN) \ +{ if (GET_CODE (EXP) == SET) \ + { if (GET_CODE (SET_DEST (EXP)) == CC0) \ + { cc_status.flags = 0; \ + cc_status.value1 = SET_DEST (EXP); \ + cc_status.value2 = SET_SRC (EXP); \ + } \ + else if (GET_CODE (SET_SRC (EXP)) == CALL) \ + { CC_STATUS_INIT; } \ + else if (GET_CODE (SET_DEST (EXP)) == REG) \ + { if (cc_status.value1 \ + && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \ + cc_status.value1 = 0; \ + if (cc_status.value2 \ + && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \ + cc_status.value2 = 0; \ + } \ + else if (GET_CODE (SET_DEST (EXP)) == MEM) \ + { CC_STATUS_INIT; } \ + } \ + else if (GET_CODE (EXP) == PARALLEL \ + && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ + { if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == CC0) \ + { cc_status.flags = 0; \ + cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \ + cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \ + } \ + else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == REG) \ + { if (cc_status.value1 \ + && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value1)) \ + cc_status.value1 = 0; \ + if (cc_status.value2 \ + && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value2)) \ + cc_status.value2 = 0; \ + } \ + else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == MEM) \ + { CC_STATUS_INIT; } \ + } \ + else if (GET_CODE (EXP) == CALL) \ + { /* all bets are off */ CC_STATUS_INIT; } \ + else { /* nothing happens? CC_STATUS_INIT; */} \ + if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ + && cc_status.value2 \ + && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ + abort (); \ +} + +/* Describe the costs of the following register moves which are discouraged: + 1.) Moves between the Floating point registers and the frame pointer and stack pointer + 2.) Moves between the stack pointer and the frame pointer + 3.) Moves between the floating point and general registers */ + +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + ((((CLASS1) == FLOAT_REGS && ((CLASS2) == STACK_POINTER_REG || (CLASS2) == FRAME_POINTER_REG)) \ + || ((CLASS2) == FLOAT_REGS && ((CLASS1) == STACK_POINTER_REG || (CLASS1) == FRAME_POINTER_REG)) \ + || ((CLASS1) == STACK_POINTER_REG && (CLASS2) == FRAME_POINTER_REG) \ + || ((CLASS2) == STACK_POINTER_REG && (CLASS1) == FRAME_POINTER_REG) \ + || ((CLASS1) == FLOAT_REGS && (CLASS2) == GENERAL_REGS) \ + || ((CLASS1) == GENERAL_REGS && (CLASS2) == FLOAT_REGS)) \ + ? 4 : 2) + +#define OUTPUT_JUMP(NORMAL, NO_OV) \ +{ if (cc_status.flags & CC_NO_OVERFLOW) \ + return NO_OV; \ + return NORMAL; } + +/* Dividing the output into sections */ + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* Define the output Assembly Language */ + +/* Output at beginning of assembler file. */ + +#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n"); + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "#APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "#NO_APP\n" + +/* Output of Data */ + +/* This is how to output an assembler line defining a `double' constant. */ + +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + fprintf (FILE, "\t.double 0d%.20e\n", (VALUE)) + +/* This is how to output an assembler line defining a `float' constant. */ + +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ + fprintf (FILE, "\t.float 0f%.20e\n", (VALUE)) + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "\t.long "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* Likewise for `char' and `short' constants. */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "\t.word "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "\t.byte "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) + +/* This is how to output an assembler line defining an external/static + address which is not in tree format (for collect.c). */ + +#define ASM_OUTPUT_LABELREF_AS_INT(STREAM, NAME) \ +do { \ + fprintf (STREAM, "\t.long\t"); \ + ASM_OUTPUT_LABELREF (STREAM, NAME); \ + fprintf (STREAM, "\n"); \ +} while (0) + +/* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tmovd %s,tos\n", reg_names[REGNO]) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tmovd tos,%s\n", reg_names[REGNO]) + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +#define REGISTER_NAMES \ +{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ + "fp", "sp"} + +/* How to renumber registers for dbx and gdb. + NS32000 may need more change in the numeration. */ + +#define DBX_REGISTER_NUMBER(REGNO) ((REGNO < 8) ? (REGNO)+4 : (REGNO)) + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#ifndef COLLECT +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) +#else +#define ASM_OUTPUT_LABEL(STREAM,NAME) \ +do { \ + fprintf (STREAM, "%s:\n", NAME); \ +} while (0) +#endif + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#ifndef COLLECT +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) +#else +#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ +do { \ + fprintf (STREAM, "\t.globl\t%s\n", NAME); \ +} while (0) +#endif + +/* This is how to output a reference to a user-level label named NAME. + `assemble_name' uses this. */ + +#define ASM_OUTPUT_LABELREF(FILE,NAME) \ + fprintf (FILE, "_%s", NAME) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) + +/* This is how to store into the string LABEL + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ + sprintf (LABEL, "*%s%d", PREFIX, NUM) + +/* This is how to align the code that follows an unconditional branch. + Note that 0xa2 is a no-op. */ + +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + fprintf (FILE, "\t.align 2,0xa2\n") + +/* This is how to output an element of a case-vector that is absolute. + (The ns32k does not use such vectors, + but we must define this macro anyway.) */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "\t.long L%d\n", VALUE) + +/* This is how to output an element of a case-vector that is relative. */ +/* ** Notice that the second element is LI format! */ +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.word L%d-LI%d\n", VALUE, REL) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + fprintf (FILE, "\t.align %d\n", (LOG)) + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.space %u\n", (SIZE)) + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".lcomm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "(" +#define ASM_CLOSE_PAREN ")" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* Print an instruction operand X on file FILE. + CODE is the code from the %-spec that requested printing this operand; + if `%z3' was used to print operand 3, then CODE is 'z'. */ + +/* %$ means print the prefix for an immediate operand. */ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ + ((CODE) == '$' || (CODE) == '?') + +#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) + +/* Print a memory operand whose address is X, on file FILE. */ + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR) + +/* Define functions in ns32k.c and used in insn-output.c. */ + +extern char *output_move_double (); +extern char *output_shift_insn (); + +/* +Local variables: +version-control: t +End: +*/ diff --git a/gnu/usr.bin/gcc2/arch/ns32k/tconfig.h b/gnu/usr.bin/gcc2/arch/ns32k/tconfig.h new file mode 100644 index 000000000000..0342169ebb6b --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/tconfig.h @@ -0,0 +1,46 @@ +/* Configuration for GNU C-compiler for Vax. + Copyright (C) 1987 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ +#include "tm.h" + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +#define memcpy(src,dst,len) bcopy ((dst),(src),(len)) +#define memset gcc_memset +#define memcmp(left,right,len) bcmp ((left),(right),(len)) + +/* If compiled with GNU C, use the built-in alloca */ +#ifdef __GNUC__ +#define alloca __builtin_alloca +#endif diff --git a/gnu/usr.bin/gcc2/arch/ns32k/tm.h b/gnu/usr.bin/gcc2/arch/ns32k/tm.h new file mode 100644 index 000000000000..b152de65e4a2 --- /dev/null +++ b/gnu/usr.bin/gcc2/arch/ns32k/tm.h @@ -0,0 +1,100 @@ +/* Definitions of target machine for GNU compiler. + PC532 with National 32532, running NetBSD 0.9 or later. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include "ns32k/ns32k.h" + +/* The NetBSD predefines ... */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dns32532 -Dpc532 -Dunix -D__NetBSD__ -Dns32k" + +/* Compile for the floating point unit & 32532 by default; + also presume SB is zero */ + +#define TARGET_DEFAULT 25 + +/* Write DBX debugging info for gdb to read */ + +#define DBX_DEBUGGING_INFO + +/* Use the re-entrant and potentially faster method */ + +#undef PCC_STATIC_STRUCT_RETURN + +/* 32-bit alignment for efficiency */ +#undef POINTER_BOUNDARY +#define POINTER_BOUNDARY 32 + +/* 32-bit alignment for efficiency */ +#undef FUNCTION_BOUNDARY +#define FUNCTION_BOUNDARY 32 + +/* 32532 spec says it can handle any alignment. Rumor from tm-ns32k.h + tells this might not be actually true (but it's for 32032, perhaps + National has fixed the bug for 32532). You might have to change this + if the bug still exists. */ + +#undef STRICT_ALIGNMENT +#define STRICT_ALIGNMENT 0 + +/* Use pc relative addressing whenever possible, + it's more efficient than absolute (ns32k.c) + You have to fix a bug in gas 1.38.1 to make this work with gas, + patch available from jkp@cs.hut.fi. */ + +#define PC_RELATIVE + +/* Operand of bsr or jsr should be just the address. */ + +#define CALL_MEMREF_IMPLICIT + +/* movd insns may have floating point constant operands. */ + +#define MOVD_FLOAT_OK + +/* Every address needs to use a base reg. */ + +#define BASE_REG_NEEDED + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ + +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Change the built-in type ideas ... */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#define WCHAR_UNSIGNED 1 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +/* NetBSD does have atexit. */ + +#define HAVE_ATEXIT +