With the new IPL world, things are easier for us: if we can get the
nell hardware interrupt handler run at IPL_VM, we can call the socket drivers interrupt handler directly. This is always possible on sparc64, but on sparc we might have to fall back to the old softint bounce. Since this uses arbitrary IPLs, we can not use the new softint_* for this - we'll have to use the old sparc_softintr_* functions.
This commit is contained in:
martin
parent
0c0de8072e
commit
258a4b78cf
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@ -1,4 +1,4 @@
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/* $NetBSD: stp4020.c,v 1.52 2007/10/19 12:01:12 ad Exp $ */
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/* $NetBSD: stp4020.c,v 1.53 2008/01/06 02:29:58 martin Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -41,7 +41,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.52 2007/10/19 12:01:12 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: stp4020.c,v 1.53 2008/01/06 02:29:58 martin Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -105,8 +105,10 @@ struct stp4020_socket {
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int sock; /* Socket number (0 or 1) */
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int sbus_intno; /* Do we use first (0) or second (1)
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interrupt? */
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#ifndef SUN4U
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int int_enable; /* ICR0 value for interrupt enabled */
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int int_disable; /* ICR0 value for interrupt disabled */
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#endif
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bus_space_tag_t tag; /* socket control io */
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bus_space_handle_t regs; /* space */
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bus_space_tag_t pcmciat; /* io space for pcmcia */
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@ -114,7 +116,9 @@ struct stp4020_socket {
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int (*intrhandler) /* Card driver interrupt handler */
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(void *);
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void *intrarg; /* Card interrupt handler argument */
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#ifndef SUN4U
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void *softint; /* cookie for the softintr */
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#endif
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struct {
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bus_space_handle_t winaddr;/* this window's address */
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@ -131,6 +135,9 @@ struct stp4020_softc {
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SIMPLEQ_HEAD(, stp4020_event) events; /* Pending events for thread */
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struct stp4020_socket sc_socks[STP4020_NSOCK];
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#ifndef SUN4U
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bool sc_use_softint;
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#endif
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};
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@ -140,7 +147,9 @@ static void stp4020attach(struct device *, struct device *, void *);
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static int stp4020_intr(void *);
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static void stp4020_map_window(struct stp4020_socket *h, int win, int speed);
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static void stp4020_calc_speed(int bus_speed, int ns, int *length, int *cmd_delay);
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#ifndef SUN4U
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static void stp4020_intr_dispatch(void *arg);
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#endif
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CFATTACH_DECL(nell, sizeof(struct stp4020_softc),
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stp4020match, stp4020attach, NULL, NULL);
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@ -366,13 +375,9 @@ stp4020attach(parent, self, aux)
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struct sbus_attach_args *sa = aux;
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struct stp4020_softc *sc = (void *)self;
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bus_space_tag_t tag;
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int rev;
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int i, sbus_intno;
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int rev, i, sbus_intno, hw_ipl;
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bus_space_handle_t bh;
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/* lsb of our config flags decides which interrupt we use */
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sbus_intno = device_cfdata(&sc->sc_dev)->cf_flags & 1;
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/* Transfer bus tags */
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#ifdef SUN4U
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tag = sa->sa_bustag;
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@ -390,6 +395,46 @@ stp4020attach(parent, self, aux)
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tag->sparc_write_8 = stp4020_write_8;
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#endif /* SUN4U */
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/* check interrupt options, decide if we need a softint */
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#ifdef SUN4U
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/*
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* On sparc64 the hardware interrupt priority does not restrict
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* the IPL we run our interrupt handler on, so we can always just
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* use the first interrupt and reqest the handler to run at
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* IPL_VM.
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*/
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sbus_intno = 0;
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hw_ipl = IPL_VM;
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#else
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/*
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* We need to check if one of the available interrupts has
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* a priority that allows us to establish a handler at IPL_VM.
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* If not (hard to imagine), use a soft interrupt.
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*/
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sbus_intno = -1;
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for (i = 0; i < sa->sa_nintr; i++) {
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struct sbus_softc *bus =
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(struct sbus_softc *) sa->sa_bustag->cookie;
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int ipl = bus->sc_intr2ipl[sa->sa_intr[i].oi_pri];
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if (ipl <= IPL_VM) {
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sbus_intno = i;
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sc->sc_use_softint = false;
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hw_ipl = IPL_VM;
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break;
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}
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}
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if (sbus_intno == -1) {
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/*
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* We have not found a usable hardware interrupt - so
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* use a softint to bounce to the proper IPL.
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*/
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printf("no usable HW interrupt found, using softint\n");
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sbus_intno = 0;
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sc->sc_use_softint = true;
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hw_ipl = IPL_NONE;
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}
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#endif
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/* Set up per-socket static initialization */
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sc->sc_socks[0].sc = sc->sc_socks[1].sc = sc;
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sc->sc_socks[0].tag = sc->sc_socks[1].tag = sa->sa_bustag;
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@ -460,7 +505,7 @@ stp4020attach(parent, self, aux)
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if (sa->sa_nintr > sbus_intno) {
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bus_intr_establish(sa->sa_bustag,
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sa->sa_intr[sbus_intno].oi_pri,
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IPL_NONE, stp4020_intr, sc);
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hw_ipl, stp4020_intr, sc);
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}
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rev = stp4020_rd_sockctl(&sc->sc_socks[0], STP4020_ISR1_IDX) &
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@ -503,9 +548,11 @@ stp4020_attach_socket(h, speed)
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/* no interrupt handlers yet */
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h->intrhandler = NULL;
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h->intrarg = NULL;
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#ifndef SUN4U
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h->softint = NULL;
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h->int_enable = 0;
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h->int_disable = 0;
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#endif
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/* Map all three windows */
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stp4020_map_window(h, STP_WIN_ATTR, speed);
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@ -623,6 +670,7 @@ stp4020_queue_event(sc, sock, event)
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wakeup(&sc->events);
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}
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#ifndef SUN4U
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/*
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* Softinterrupt called to invoke the real driver interrupt handler.
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*/
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@ -641,17 +689,23 @@ stp4020_intr_dispatch(arg)
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stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_enable);
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splx(s);
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}
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#endif
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int
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stp4020_intr(arg)
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void *arg;
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{
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struct stp4020_softc *sc = arg;
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int i, s, r = 0, cd_change = 0;
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#ifndef SUN4U
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int s;
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#endif
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int i, r = 0, cd_change = 0;
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#ifndef SUN4U
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/* protect hardware access by splhigh against softint */
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s = splhigh();
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#endif
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/*
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* Check each socket for pending requests.
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@ -710,17 +764,21 @@ stp4020_intr(arg)
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continue;
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}
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#ifndef SUN4U
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/*
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* Schedule softint to invoke driver interrupt
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* handler
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*/
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if (h->softint != NULL)
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softint_schedule(h->softint);
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sparc_softintr_schedule(h->softint);
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/*
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* Disable this sbus interrupt, until the soft-int
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* handler had a chance to run
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*/
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stp4020_wr_sockctl(h, STP4020_ICR0_IDX, h->int_disable);
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#else
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(*h->intrhandler)(h->intrarg);
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#endif
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}
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/* informational messages */
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@ -762,7 +820,9 @@ stp4020_intr(arg)
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printf("stp4020[%d]: unhandled interrupt: 0x%x\n", h->sock, v);
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}
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#ifndef SUN4U
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splx(s);
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#endif
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return (r);
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}
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@ -1022,12 +1082,16 @@ stp4020_chip_socket_settype(pch, type)
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|STP4020_ICR0_SPKREN;
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v |= h->sbus_intno ? STP4020_ICR0_IOILVL_SB1
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: STP4020_ICR0_IOILVL_SB0;
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#ifndef SUN4U
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h->int_enable = v;
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h->int_disable = v & ~STP4020_ICR0_IOIE;
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#endif
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DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname));
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} else {
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v |= STP4020_ICR0_IFTYPE_MEM;
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#ifndef SUN4U
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h->int_enable = h->int_disable = v;
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#endif
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DPRINTF(("%s: configuring card for IO useage\n", h->sc->sc_dev.dv_xname));
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DPRINTF(("%s: configuring card for MEM ONLY useage\n", h->sc->sc_dev.dv_xname));
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}
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@ -1073,8 +1137,13 @@ stp4020_chip_intr_establish(pch, pf, ipl, handler, arg)
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h->intrhandler = handler;
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h->intrarg = arg;
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h->softint = softint_establish(ipl, stp4020_intr_dispatch, h);
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return h->softint;
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#ifndef SUN4U
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if (h->sc->sc_use_softint) {
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h->softint = sparc_softintr_establish(ipl, stp4020_intr_dispatch, h);
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return h->softint;
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}
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#endif
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return h;
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}
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void
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@ -1086,10 +1155,12 @@ stp4020_chip_intr_disestablish(pch, ih)
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h->intrhandler = NULL;
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h->intrarg = NULL;
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#ifndef SUN4U
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if (h->softint) {
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softint_disestablish(h->softint);
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sparc_softintr_disestablish(h->softint);
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h->softint = NULL;
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}
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#endif
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}
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/*
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