Cleanup softint lossage.
This commit is contained in:
matt
parent
3ef8cd67cc
commit
0c0de8072e
@ -1,4 +1,4 @@
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/* $NetBSD: idle_machdep.c,v 1.2 2007/05/17 14:51:15 yamt Exp $ */
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/* $NetBSD: idle_machdep.c,v 1.3 2008/01/06 01:37:53 matt Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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@ -38,10 +38,11 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.2 2007/05/17 14:51:15 yamt Exp $");
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__KERNEL_RCSID(0, "$NetBSD: idle_machdep.c,v 1.3 2008/01/06 01:37:53 matt Exp $");
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#include <sys/param.h>
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#include <sys/cpu.h>
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#include <arm/cpufunc.h>
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void
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cpu_idle(void)
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@ -49,7 +50,7 @@ cpu_idle(void)
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if (cpu_do_powersave) {
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IRQdisable;
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cpufuncs.cf_sleep(0);
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cpu_sleep(0);
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IRQenable;
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}
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.c,v 1.25 2007/12/03 15:33:16 ad Exp $ */
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/* $NetBSD: intr.c,v 1.26 2008/01/06 01:37:53 matt Exp $ */
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/*
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* Copyright (c) 1994-1998 Mark Brinicombe.
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@ -36,7 +36,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.25 2007/12/03 15:33:16 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.26 2008/01/06 01:37:53 matt Exp $");
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#include "opt_irqstats.h"
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@ -58,15 +58,16 @@ __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.25 2007/12/03 15:33:16 ad Exp $");
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extern int current_spl_level;
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static u_int spl_smasks[_SPL_LEVELS];
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/* Eventually these will become macros */
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#ifdef __HAVE_FAST_SOFTINTS
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/* Generate soft interrupt counts if IRQSTATS is defined */
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/* Prototypes */
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static void clearsoftintr(u_int);
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static u_int soft_interrupts = 0;
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static u_int spl_smasks[_SPL_LEVELS];
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/* Eventually these will become macros */
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#define SI_SOFTMASK(si) (1U << (si))
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static inline void
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@ -81,7 +82,6 @@ _setsoftintr(int si)
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atomic_set_bit(&soft_interrupts, SI_SOFTMASK(si));
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}
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#ifdef __HAVE_FAST_SOFTINTS
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/* Handle software interrupts */
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void
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@ -157,6 +157,7 @@ set_spl_masks(void)
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spl_masks[_SPL_LEVELS] = 0;
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spl_smasks[_SPL_0] = 0xffffffff;
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#ifdef __HAVE_FAST_SOFTINTS
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for (loop = 0; loop < _SPL_SOFTSERIAL; ++loop)
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spl_smasks[loop] |= SI_SOFTMASK(SI_SOFTSERIAL);
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for (loop = 0; loop < _SPL_SOFTNET; ++loop)
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@ -165,6 +166,7 @@ set_spl_masks(void)
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spl_smasks[loop] |= SI_SOFTMASK(SI_SOFTCLOCK);
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for (loop = 0; loop < _SPL_SOFTBIO; ++loop)
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spl_smasks[loop] |= SI_SOFTMASK(SI_SOFTBIO);
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#endif
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}
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static const int ipl_to_spl_map[] = {
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@ -1,4 +1,4 @@
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/* $NetBSD: ep93xx_intr.c,v 1.9 2007/12/03 15:33:17 ad Exp $ */
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/* $NetBSD: ep93xx_intr.c,v 1.10 2008/01/06 01:37:53 matt Exp $ */
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/*
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -40,7 +40,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ep93xx_intr.c,v 1.9 2007/12/03 15:33:17 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: ep93xx_intr.c,v 1.10 2008/01/06 01:37:53 matt Exp $");
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/*
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* Interrupt support for the Cirrus Logic EP93XX
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@ -79,16 +79,21 @@ volatile u_int32_t vic2_intr_enabled;
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/* Interrupts pending. */
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static volatile int ipending;
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#ifdef __HAVE_FAST_SOFTINTS
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#define SI_SOFTCLOCK 0
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#define SI_SOFTBIO 1
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#define SI_SOFTNET 2
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#define SI_SOFTSERIAL 3
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/*
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* Map a software interrupt queue index (to the unused bits in the
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* VIC1 register -- XXX will need to revisit this if those bits are
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* ever used in future steppings).
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*/
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static const u_int32_t si_to_irqbit[SI_NQUEUES] = {
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EP93XX_INTR_bit30, /* SI_SOFTCLOCK */
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EP93XX_INTR_bit29, /* SI_SOFTBIO */
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EP93XX_INTR_bit28, /* SI_SOFTNET */
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EP93XX_INTR_bit27, /* SI_SOFTSERIAL */
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static const u_int32_t si_to_irqbit[] = {
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[SI_SOFTCLOCK] = EP93XX_INTR_bit30,
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[SI_SOFTBIO] = EP93XX_INTR_bit29,
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[SI_SOFTNET] = EP93XX_INTR_bit28,
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[SI_SOFTSERIAL] = EP93XX_INTR_bit27,
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};
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#define INT_SWMASK \
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@ -100,12 +105,13 @@ static const u_int32_t si_to_irqbit[SI_NQUEUES] = {
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/*
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* Map a software interrupt queue to an interrupt priority level.
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*/
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static const int si_to_ipl[SI_NQUEUES] = {
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IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
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IPL_SOFTBIO, /* SI_SOFTBIO */
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IPL_SOFTNET, /* SI_SOFTNET */
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IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
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static const int si_to_ipl[] = {
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[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
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[SI_SOFTBIO] = IPL_SOFTBIO,
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[SI_SOFTNET] = IPL_SOFTNET,
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[SI_SOFTSERIAl] = IPL_SOFTSERIAL,
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};
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#endif /* __HAVE_FAST_SOFTINTS */
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void ep93xx_intr_dispatch(struct irqframe *frame);
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@ -184,9 +190,10 @@ ep93xx_intr_calculate_masks(void)
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vic2_imask[ipl] = vic2_irqs;
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}
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vic1_imask[IPL_NONE] = 0;
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vic2_imask[IPL_NONE] = 0;
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KASSERT(vic1_imask[IPL_NONE] == 0);
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KASSERT(vic2_imask[IPL_NONE] == 0);
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#ifdef __HAVE_FAST_SOFTINTS
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/*
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* Initialize the soft interrupt masks to block themselves.
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*/
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@ -203,66 +210,49 @@ ep93xx_intr_calculate_masks(void)
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vic1_imask[IPL_SOFTCLOCK] |= vic1_imask[IPL_SOFT];
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vic2_imask[IPL_SOFTCLOCK] |= vic2_imask[IPL_SOFT];
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/*
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* splsoftbio() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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vic1_imask[IPL_SOFTBIO] |= vic1_imask[IPL_SOFTCLOCK];
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vic2_imask[IPL_SOFTBIO] |= vic2_imask[IPL_SOFTCLOCK];
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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vic1_imask[IPL_SOFTNET] |= vic1_imask[IPL_SOFTCLOCK];
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vic2_imask[IPL_SOFTNET] |= vic2_imask[IPL_SOFTCLOCK];
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vic1_imask[IPL_SOFTNET] |= vic1_imask[IPL_SOFTBIO];
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vic2_imask[IPL_SOFTNET] |= vic2_imask[IPL_SOFTBIO];
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/*
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* Enforce a hierarchy that gives "slow" device (or devices with
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* limited input buffer space/"real-time" requirements) a better
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* chance at not dropping data.
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*/
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vic1_imask[IPL_BIO] |= vic1_imask[IPL_SOFTNET];
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vic2_imask[IPL_BIO] |= vic2_imask[IPL_SOFTNET];
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vic1_imask[IPL_NET] |= vic1_imask[IPL_BIO];
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vic2_imask[IPL_NET] |= vic2_imask[IPL_BIO];
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vic1_imask[IPL_SOFTSERIAL] |= vic1_imask[IPL_NET];
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vic2_imask[IPL_SOFTSERIAL] |= vic2_imask[IPL_NET];
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vic1_imask[IPL_TTY] |= vic1_imask[IPL_SOFTSERIAL];
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vic2_imask[IPL_TTY] |= vic2_imask[IPL_SOFTSERIAL];
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vic1_imask[IPL_SOFTSERIAL] |= vic1_imask[IPL_SOFTNET];
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vic2_imask[IPL_SOFTSERIAL] |= vic2_imask[IPL_SOFTNET];
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/*
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* splvm() blocks all interrupts that use the kernel memory
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* allocation facilities.
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*/
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vic1_imask[IPL_VM] |= vic1_imask[IPL_TTY];
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vic2_imask[IPL_VM] |= vic2_imask[IPL_TTY];
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/*
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* Audio devices are not allowed to perform memory allocation
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* in their interrupt routines, and they have fairly "real-time"
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* requirements, so give them a high interrupt priority.
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*/
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vic1_imask[IPL_AUDIO] |= vic1_imask[IPL_VM];
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vic2_imask[IPL_AUDIO] |= vic2_imask[IPL_VM];
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vic1_imask[IPL_VM] |= vic1_imask[IPL_SOFTSERIAL];
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vic2_imask[IPL_VM] |= vic2_imask[IPL_SOFTSERIAL];
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#endif /* __HAVE_FAST_SOFTINTS */
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/*
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* splclock() must block anything that uses the scheduler.
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*/
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vic1_imask[IPL_CLOCK] |= vic1_imask[IPL_AUDIO];
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vic2_imask[IPL_CLOCK] |= vic2_imask[IPL_AUDIO];
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/*
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* No separate statclock on the EP93xx.
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*/
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vic1_imask[IPL_STATCLOCK] |= vic1_imask[IPL_CLOCK];
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vic2_imask[IPL_STATCLOCK] |= vic2_imask[IPL_CLOCK];
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/*
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* serial uarts have small buffers that need low-latency servicing
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*/
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vic1_imask[IPL_SERIAL] |= vic1_imask[IPL_STATCLOCK];
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vic2_imask[IPL_SERIAL] |= vic2_imask[IPL_STATCLOCK];
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vic1_imask[IPL_CLOCK] |= vic1_imask[IPL_VM];
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vic2_imask[IPL_CLOCK] |= vic2_imask[IPL_VM];
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/*
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* splhigh() must block "everything".
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*/
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vic1_imask[IPL_HIGH] |= vic1_imask[IPL_SERIAL];
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vic2_imask[IPL_HIGH] |= vic2_imask[IPL_SERIAL];
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vic1_imask[IPL_HIGH] |= vic1_imask[IPL_CLOCK];
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vic2_imask[IPL_HIGH] |= vic2_imask[IPL_CLOCK];
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/*
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* Now compute which IRQs must be blocked when servicing any
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@ -292,6 +282,7 @@ ep93xx_intr_calculate_masks(void)
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}
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}
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#ifdef __HAVE_FAST_SOFTINTS
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static void
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ep93xx_do_pending(void)
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{
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@ -325,6 +316,7 @@ ep93xx_do_pending(void)
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restore_interrupts(oldirqstate);
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}
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#endif
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inline void
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splx(int new)
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@ -341,9 +333,11 @@ splx(int new)
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}
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restore_interrupts(oldirqstate);
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#ifdef __HAVE_FAST_SOFTINTS
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/* If there are software interrupts to process, do it. */
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if ((ipending & INT_SWMASK) & ~vic1_imask[new])
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ep93xx_do_pending();
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#endif
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}
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int
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@ -370,6 +364,7 @@ _spllower(int ipl)
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return (old);
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}
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#ifdef __HAVE_FAST_SOFTINTS
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void
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_setsoftintr(int si)
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{
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@ -383,6 +378,7 @@ _setsoftintr(int si)
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if ((ipending & INT_SWMASK) & ~vic1_imask[current_spl_level])
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ep93xx_do_pending();
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}
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#endif
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/*
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* ep93xx_intr_init:
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@ -521,8 +517,10 @@ ep93xx_intr_dispatch(struct irqframe *frame)
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hardware_spl_level = pcpl;
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ep93xx_set_intrmask(vic1_imask[pcpl], vic2_imask[pcpl]);
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#ifdef __HAVE_FAST_SOFTINTS
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/* Check for pendings soft intrs. */
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if ((ipending & INT_SWMASK) & ~vic1_imask[pcpl]) {
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ep93xx_do_pending();
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}
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#endif
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: ep93xx_intr.h,v 1.2 2005/12/11 12:16:45 christos Exp $ */
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/* $NetBSD: ep93xx_intr.h,v 1.3 2008/01/06 01:37:53 matt Exp $ */
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/*
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* Copyright (c) 2004 Jesse Off
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@ -43,7 +43,9 @@
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int _splraise(int);
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int _spllower(int);
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void splx(int);
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#ifdef __HAVE_FAST_SOFTINTS
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void _setsoftintr(int);
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#endif
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#endif /* ! _LOCORE */
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@ -1,4 +1,4 @@
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/* $NetBSD: epcom.c,v 1.15 2007/11/19 18:51:38 ad Exp $ */
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/* $NetBSD: epcom.c,v 1.16 2008/01/06 01:37:54 matt Exp $ */
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/*
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* Copyright (c) 1998, 1999, 2001, 2002, 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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@ -80,7 +80,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: epcom.c,v 1.15 2007/11/19 18:51:38 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: epcom.c,v 1.16 2008/01/06 01:37:54 matt Exp $");
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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@ -242,7 +242,7 @@ epcom_attach_subr(struct epcom_softc *sc)
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aprint_normal("%s: console\n", sc->sc_dev.dv_xname);
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}
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sc->sc_si = softintr_establish(IPL_SOFTSERIAL, epcomsoft, sc);
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sc->sc_si = softint_establish(SOFTINT_SERIAL, epcomsoft, sc);
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#if NRND > 0 && defined(RND_COM)
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rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
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@ -1136,7 +1136,7 @@ epcomintr(void* arg)
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}
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/* Wake up the poller. */
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softintr_schedule(sc->sc_si);
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softint_schedule(sc->sc_si);
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#if 0 /* XXX: broken */
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#if NRND > 0 && defined(RND_COM)
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@ -1,4 +1,4 @@
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/* $NetBSD: psl.h,v 1.14 2007/12/03 15:33:19 ad Exp $ */
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/* $NetBSD: psl.h,v 1.15 2008/01/06 01:37:54 matt Exp $ */
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/*
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* Copyright (c) 1995 Mark Brinicombe.
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@ -57,6 +57,7 @@
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*/
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#define _SPL_0 0
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#ifdef __HAVE_FAST_SOFTINTS
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#define _SPL_SOFTCLOCK 1
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#define _SPL_SOFTBIO 2
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#define _SPL_SOFTNET 3
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@ -65,23 +66,42 @@
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#define _SPL_SCHED 6
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#define _SPL_HIGH 7
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#define _SPL_LEVELS 8
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#else
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#define _SPL_SOFTCLOCK _SPL_0
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#define _SPL_SOFTBIO _SPL_0
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#define _SPL_SOFTNET _SPL_0
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#define _SPL_SOFTSERIAL _SPL_0
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#define _SPL_VM 1
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#define _SPL_SCHED 2
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#define _SPL_HIGH 3
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#define _SPL_LEVELS 4
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#endif
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#define spl0() splx(_SPL_0)
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#ifdef __HAVE_FAST_SOFTINTS
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#define splsoftclock() raisespl(_SPL_SOFTCLOCK)
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#define splsoftbio() raisespl(_SPL_SOFTBIO)
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#define splsoftnet() raisespl(_SPL_SOFTNET)
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#define splsoftserial() raisespl(_SPL_SOFTSERIAL)
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#else
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#define splsoftclock() spl0()
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#define splsoftbio() spl0()
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#define splsoftnet() spl0()
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#define splsoftserial() spl0()
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#endif
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#define splvm() raisespl(_SPL_VM)
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#define splsched() raisespl(_SPL_SCHED)
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#define splhigh() raisespl(_SPL_HIGH)
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#ifdef _KERNEL
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#ifndef _LOCORE
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int raisespl __P((int));
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int lowerspl __P((int));
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int splx __P((int));
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int raisespl (int);
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int lowerspl (int);
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int splx (int);
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#ifdef __HAVE_FAST_SOFTINTS
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void _setsoftintr (int si);
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#endif
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extern int current_spl_level;
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@ -1,4 +1,4 @@
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/* $NetBSD: omap_intr.c,v 1.3 2007/12/15 00:39:14 perry Exp $ */
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/* $NetBSD: omap_intr.c,v 1.4 2008/01/06 01:37:54 matt Exp $ */
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||||
|
||||
/*
|
||||
* Based on arch/arm/xscale/pxa2x0_intr.c
|
||||
@ -42,7 +42,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: omap_intr.c,v 1.3 2007/12/15 00:39:14 perry Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: omap_intr.c,v 1.4 2008/01/06 01:37:54 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -72,16 +72,23 @@ uint32_t omap_spl_masks[NIPL][OMAP_NBANKS] =
|
||||
|
||||
uint32_t omap_global_masks[OMAP_NBANKS];
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define SI_SOFTCLOCK 0
|
||||
#define SI_SOFTBIO 1
|
||||
#define SI_SOFTNET 2
|
||||
#define SI_SOFTSERIAL 3
|
||||
/* Array to translate from software interrupt number to priority level. */
|
||||
static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFT, /* SI_SOFT */
|
||||
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
static const int si_to_ipl[] = {
|
||||
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
|
||||
[SI_SOFTBIO] = IPL_SOFTBIO,
|
||||
[SI_SOFTNET] = IPL_SOFTNET,
|
||||
[SI_SOFTSERIAL] = IPL_SOFTSERIAL,
|
||||
};
|
||||
|
||||
static int stray_interrupt(void *);
|
||||
static int soft_interrupt(void *);
|
||||
#endif
|
||||
|
||||
static int stray_interrupt(void *);
|
||||
static void init_interrupt_masks(void);
|
||||
static void omap_update_intr_masks(int, int);
|
||||
static void omapintc_set_name(int, const char *, int);
|
||||
@ -172,10 +179,12 @@ omapintc_attach(struct device *parent, struct device *self, void *args)
|
||||
/* Set all interrupts to be stray and to have event counters. */
|
||||
omapintc_set_name(OMAP_INT_L2_IRQ, "IRQ from L2", false);
|
||||
omapintc_set_name(OMAP_INT_L2_FIQ, "FIQ from L2", false);
|
||||
omapintc_set_name(omap_si_to_irq[SI_SOFT], "SOFT", false);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
omapintc_set_name(omap_si_to_irq[SI_SOFTCLOCK], "SOFTCLOCK", false);
|
||||
omapintc_set_name(omap_si_to_irq[SI_SOFTBIO], "SOFTBIO", false);
|
||||
omapintc_set_name(omap_si_to_irq[SI_SOFTNET], "SOFTNET", false);
|
||||
omapintc_set_name(omap_si_to_irq[SI_SOFTSERIAL], "SOFTSERIAL", false);
|
||||
#endif
|
||||
for(i = 0; i < __arraycount(handler); ++i) {
|
||||
handler[i].func = stray_interrupt;
|
||||
handler[i].cookie = (void *)(intptr_t) i;
|
||||
@ -184,17 +193,17 @@ omapintc_attach(struct device *parent, struct device *self, void *args)
|
||||
if (handler[i].name == NULL)
|
||||
omapintc_set_name(i, handler[i].irq_num_str, false);
|
||||
}
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/* and then set up the software interrupts. */
|
||||
for(i = 0; i < __arraycount(omap_si_to_irq); ++i) {
|
||||
int irq = omap_si_to_irq[i];
|
||||
handler[irq].func = soft_interrupt;
|
||||
/* Cookie value zero means pass interrupt frame instead */
|
||||
handler[irq].cookie = (void *)(intptr_t) (i | 0x80000000);
|
||||
if (i < __arraycount(si_to_ipl))
|
||||
extirq_level[irq] = si_to_ipl[i];
|
||||
else
|
||||
extirq_level[irq] = IPL_SOFT;
|
||||
KASSERT(i < __arraycount(si_to_ipl));
|
||||
extirq_level[irq] = si_to_ipl[i];
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Initialize our table of masks. */
|
||||
init_interrupt_masks();
|
||||
@ -333,6 +342,7 @@ stray_interrupt(void *cookie)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static int
|
||||
soft_interrupt(void *cookie)
|
||||
{
|
||||
@ -342,7 +352,7 @@ soft_interrupt(void *cookie)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static inline void
|
||||
@ -401,26 +411,30 @@ static void
|
||||
init_interrupt_masks(void)
|
||||
{
|
||||
const omap_intr_info_t
|
||||
*soft_inf =&omap_intr_info[omap_si_to_irq[SI_SOFT]],
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
*softclock_inf =&omap_intr_info[omap_si_to_irq[SI_SOFTCLOCK]],
|
||||
*softbio_inf =&omap_intr_info[omap_si_to_irq[SI_SOFTBIO]],
|
||||
*softnet_inf =&omap_intr_info[omap_si_to_irq[SI_SOFTNET]],
|
||||
*softserial_inf=&omap_intr_info[omap_si_to_irq[SI_SOFTSERIAL]],
|
||||
#endif
|
||||
*l2_inf =&omap_intr_info[OMAP_INT_L2_IRQ];
|
||||
int i;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/*
|
||||
* We just blocked all the interrupts in all the masks. Now we just
|
||||
* go through and modify the masks to allow the software interrupts as
|
||||
* documented in the spl(9) man page.
|
||||
*/
|
||||
for (i = IPL_NONE; i < IPL_SOFT; ++i)
|
||||
level_allow_irq(i, soft_inf);
|
||||
for (i = IPL_NONE; i < IPL_SOFTCLOCK; ++i)
|
||||
level_allow_irq(i, softclock_inf);
|
||||
for (i = IPL_NONE; i < IPL_SOFTBIO; ++i)
|
||||
level_allow_irq(i, softbio_inf);
|
||||
for (i = IPL_NONE; i < IPL_SOFTNET; ++i)
|
||||
level_allow_irq(i, softnet_inf);
|
||||
for (i = IPL_NONE; i < IPL_SOFTSERIAL; ++i)
|
||||
level_allow_irq(i, softserial_inf);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We block level 2 interrupts down in the level 2 controller, so we
|
||||
@ -453,6 +467,7 @@ _spllower(int ipl)
|
||||
return omap_spllower(ipl);
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#undef _setsoftintr
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
@ -460,6 +475,7 @@ _setsoftintr(int si)
|
||||
|
||||
return omap_setsoftintr(si);
|
||||
}
|
||||
#endif
|
||||
|
||||
void *
|
||||
omap_intr_establish(int irqno, int level, const char *name,
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: omap_intr.h,v 1.1 2007/01/06 00:29:52 christos Exp $ */
|
||||
/* $NetBSD: omap_intr.h,v 1.2 2008/01/06 01:37:54 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -44,7 +44,6 @@
|
||||
#include <arm/armreg.h>
|
||||
#include <arm/cpufunc.h>
|
||||
#include <machine/atomic.h>
|
||||
#include <arm/softintr.h>
|
||||
|
||||
#define OMAP_IRQ_MIN 0
|
||||
#define OMAP_NIRQ (OMAP_INT_L1_NIRQ + OMAP_INT_L2_NIRQ)
|
||||
@ -118,8 +117,10 @@ extern uint32_t omap_spl_masks[NIPL][OMAP_NBANKS];
|
||||
/* Array of globally-off masks while interrupts processed. */
|
||||
extern uint32_t omap_global_masks[OMAP_NBANKS];
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/* Array to translate from software interrupt numbers to an irq number. */
|
||||
extern int omap_si_to_irq[OMAP_FREE_IRQ_NUM];
|
||||
#endif
|
||||
|
||||
extern volatile int current_spl_level;
|
||||
|
||||
@ -169,6 +170,7 @@ omap_spllower(int ipl)
|
||||
return(old);
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static inline void
|
||||
omap_setsoftintr(int si)
|
||||
{
|
||||
@ -189,18 +191,23 @@ omap_setsoftintr(int si)
|
||||
#endif
|
||||
write_icu(info->bank_base, OMAP_INTB_SISR, info->mask);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#if !defined(EVBARM_SPL_NOINLINE)
|
||||
#define splx(new) omap_splx(new)
|
||||
#define _spllower(ipl) omap_spllower(ipl)
|
||||
#define _splraise(ipl) omap_splraise(ipl)
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define _setsoftintr(si) omap_setsoftintr(si)
|
||||
#endif
|
||||
#endif /* !EVBARM_SPL_NOINTR */
|
||||
|
||||
void omap_irq_handler(void *);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: omap_mputmr.c,v 1.1 2007/01/06 00:29:52 christos Exp $ */
|
||||
/* $NetBSD: omap_mputmr.c,v 1.2 2008/01/06 01:37:55 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Based on i80321_timer.c and arch/arm/sa11x0/sa11x0_ost.c
|
||||
@ -73,7 +73,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: omap_mputmr.c,v 1.1 2007/01/06 00:29:52 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: omap_mputmr.c,v 1.2 2008/01/06 01:37:55 matt Exp $");
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/param.h>
|
||||
@ -323,7 +323,7 @@ cpu_initclocks(void)
|
||||
|
||||
omap_intr_establish(clock_sc->sc_intr, IPL_CLOCK,
|
||||
clock_sc->sc_dev.dv_xname, clockintr, 0);
|
||||
omap_intr_establish(stat_sc->sc_intr, IPL_STATCLOCK,
|
||||
omap_intr_establish(stat_sc->sc_intr, IPL_HIGH,
|
||||
stat_sc->sc_dev.dv_xname, statintr, 0);
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2410_extint.c,v 1.8 2007/12/15 00:39:15 perry Exp $ */
|
||||
/* $NetBSD: s3c2410_extint.c,v 1.9 2008/01/06 01:37:55 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003 Genetec corporation. All rights reserved.
|
||||
@ -39,7 +39,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2410_extint.c,v 1.8 2007/12/15 00:39:15 perry Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2410_extint.c,v 1.9 2008/01/06 01:37:55 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -207,16 +207,7 @@ s3c2410_extint_establish(int extint, int ipl, int type,
|
||||
return s3c24x0_intr_establish(extint, ipl, type, func, arg);
|
||||
}
|
||||
|
||||
#ifdef __GENERIC_SOFT_INTERRUPTS_ALL_LEVELS
|
||||
soft_level = ipl;
|
||||
#else
|
||||
if (ipl >= IPL_SOFTSERIAL)
|
||||
soft_level = IPL_SOFTSERIAL;
|
||||
else if (ipl >= IPL_SOFTNET)
|
||||
soft_level = IPL_SOFTNET;
|
||||
else
|
||||
soft_level = IPL_SOFT;
|
||||
#endif
|
||||
soft_level = SOFTINT_SERIAL;
|
||||
|
||||
idx = extint - EXTINT_CASCADE_MIN;
|
||||
|
||||
@ -226,7 +217,7 @@ s3c2410_extint_establish(int extint, int ipl, int type,
|
||||
ssextio_softc->sc_handler[idx].arg = arg;
|
||||
ssextio_softc->sc_handler[idx].level = ipl;
|
||||
|
||||
ssextio_softc->sc_handler[idx].sh = softintr_establish(soft_level,
|
||||
ssextio_softc->sc_handler[idx].sh = softint_establish(soft_level,
|
||||
ssextio_softintr, &ssextio_softc->sc_handler[idx]);
|
||||
|
||||
s3c2410_setup_extint(extint, type);
|
||||
@ -278,7 +269,7 @@ ssextio_cascaded_intr(void *cookie)
|
||||
if (pending & (1<<i)) {
|
||||
assert(ssextio_softc->sc_handler[i-EXTINT_CASCADE_MIN].sh != NULL);
|
||||
|
||||
softintr_schedule(
|
||||
softint_schedule(
|
||||
ssextio_softc->sc_handler[i-EXTINT_CASCADE_MIN].sh);
|
||||
pending &= ~ (1<<i);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2410_intr.c,v 1.6 2005/12/24 20:06:52 perry Exp $ */
|
||||
/* $NetBSD: s3c2410_intr.c,v 1.7 2008/01/06 01:37:55 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003 Genetec corporation. All rights reserved.
|
||||
@ -35,7 +35,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.6 2005/12/24 20:06:52 perry Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.7 2008/01/06 01:37:55 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -54,31 +54,37 @@ __KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.6 2005/12/24 20:06:52 perry Exp $
|
||||
|
||||
struct s3c2xx0_intr_dispatch handler[ICU_LEN];
|
||||
|
||||
volatile int softint_pending;
|
||||
|
||||
volatile int current_spl_level;
|
||||
volatile int intr_mask;
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
volatile int softint_pending;
|
||||
volatile int soft_intr_mask;
|
||||
#endif
|
||||
volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
|
||||
|
||||
/* interrupt masks for each level */
|
||||
int s3c2xx0_imask[NIPL];
|
||||
int s3c2xx0_ilevel[ICU_LEN];
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
int s3c24x0_soft_imask[NIPL];
|
||||
#endif
|
||||
|
||||
vaddr_t intctl_base; /* interrupt controller registers */
|
||||
#define icreg(offset) \
|
||||
(*(volatile uint32_t *)(intctl_base+(offset)))
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/*
|
||||
* Map a software interrupt queue to an interrupt priority level.
|
||||
*/
|
||||
static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFT, /* SI_SOFT */
|
||||
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
static const int si_to_ipl[] = {
|
||||
[SI_SOFTBIO] = IPL_SOFTBIO,
|
||||
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
|
||||
[SI_SOFTNET] = IPL_SOFTNET,
|
||||
[SI_SOFTSERIAL] = IPL_SOFTSERIAL,
|
||||
};
|
||||
#endif
|
||||
|
||||
#define PENDING_CLEAR_MASK (~0)
|
||||
|
||||
@ -134,10 +140,10 @@ s3c2410_irq_handler(struct clockframe *frame)
|
||||
|
||||
}
|
||||
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
if (get_pending_softint())
|
||||
s3c2xx0_do_pending(1);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
@ -256,6 +262,7 @@ init_interrupt_masks(void)
|
||||
for (i=0; i < NIPL; ++i)
|
||||
s3c2xx0_imask[i] = 0;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
s3c24x0_soft_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
|
||||
SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
|
||||
SI_TO_IRQBIT(SI_SOFT);
|
||||
@ -280,6 +287,7 @@ init_interrupt_masks(void)
|
||||
|
||||
for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
|
||||
s3c24x0_soft_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c24x0_clk.c,v 1.7 2007/01/06 16:18:18 christos Exp $ */
|
||||
/* $NetBSD: s3c24x0_clk.c,v 1.8 2008/01/06 01:37:55 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2003 Genetec corporation. All rights reserved.
|
||||
@ -30,7 +30,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.7 2007/01/06 16:18:18 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.8 2008/01/06 01:37:55 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -287,8 +287,10 @@ cpu_initclocks(void)
|
||||
|
||||
s3c24x0_intr_establish(S3C24X0_INT_TIMER4, IPL_CLOCK,
|
||||
IST_NONE, hardintr, 0);
|
||||
#ifdef IPL_STATCLOCK
|
||||
s3c24x0_intr_establish(S3C24X0_INT_TIMER3, IPL_STATCLOCK,
|
||||
IST_NONE, statintr, 0);
|
||||
#endif
|
||||
|
||||
/* set prescaler1 */
|
||||
reg = bus_space_read_4(iot, ioh, TIMER_TCFG0);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c24x0_intr.h,v 1.6 2005/12/24 20:06:52 perry Exp $ */
|
||||
/* $NetBSD: s3c24x0_intr.h,v 1.7 2008/01/06 01:37:55 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003 Genetec corporation. All rights reserved.
|
||||
@ -34,18 +34,20 @@
|
||||
|
||||
#ifndef _LOCORE
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define SI_TO_IRQBIT(si) (1<<(si))
|
||||
|
||||
#define get_pending_softint() (softint_pending & soft_intr_mask)
|
||||
#define update_softintr_mask() \
|
||||
(soft_intr_mask = s3c24x0_soft_imask[current_spl_level])
|
||||
#define s3c2xx0_update_hw_mask() \
|
||||
(*s3c2xx0_intr_mask_reg = ~(intr_mask & global_intr_mask))
|
||||
|
||||
/* no room for softinterrupts in intr_mask. */
|
||||
extern int volatile soft_intr_mask;
|
||||
extern int s3c24x0_soft_imask[];
|
||||
|
||||
#define get_pending_softint() (softint_pending & soft_intr_mask)
|
||||
#define update_softintr_mask() \
|
||||
(soft_intr_mask = s3c24x0_soft_imask[current_spl_level])
|
||||
#endif
|
||||
|
||||
#define s3c2xx0_update_hw_mask() \
|
||||
(*s3c2xx0_intr_mask_reg = ~(intr_mask & global_intr_mask))
|
||||
|
||||
#include <arm/s3c2xx0/s3c2xx0_intr.h>
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2800_clk.c,v 1.10 2007/01/06 16:18:18 christos Exp $ */
|
||||
/* $NetBSD: s3c2800_clk.c,v 1.11 2008/01/06 01:37:55 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Fujitsu Component Limited
|
||||
@ -34,7 +34,7 @@
|
||||
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2800_clk.c,v 1.10 2007/01/06 16:18:18 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2800_clk.c,v 1.11 2008/01/06 01:37:55 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -290,7 +290,7 @@ cpu_initclocks()
|
||||
|
||||
s3c2800_intr_establish(S3C2800_INT_TIMER0, IPL_CLOCK,
|
||||
IST_NONE, hardintr, 0);
|
||||
s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_STATCLOCK,
|
||||
s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_HIGH,
|
||||
IST_NONE, statintr, 0);
|
||||
|
||||
/* start timers */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2800_intr.c,v 1.9 2005/12/24 20:06:52 perry Exp $ */
|
||||
/* $NetBSD: s3c2800_intr.c,v 1.10 2008/01/06 01:37:56 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Fujitsu Component Limited
|
||||
@ -38,7 +38,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.9 2005/12/24 20:06:52 perry Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.10 2008/01/06 01:37:56 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -57,7 +57,9 @@ __KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.9 2005/12/24 20:06:52 perry Exp $
|
||||
|
||||
struct s3c2xx0_intr_dispatch handler[ICU_LEN];
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
volatile int softint_pending;
|
||||
#endif
|
||||
|
||||
volatile int current_spl_level;
|
||||
volatile int intr_mask; /* XXX: does this need to be volatile? */
|
||||
@ -71,15 +73,17 @@ vaddr_t intctl_base; /* interrupt controller registers */
|
||||
#define icreg(offset) \
|
||||
(*(volatile uint32_t *)(intctl_base+(offset)))
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/*
|
||||
* Map a software interrupt queue to an interrupt priority level.
|
||||
*/
|
||||
static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFT, /* SI_SOFT */
|
||||
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
static const int si_to_ipl[] = {
|
||||
[SI_SOFTBIO] = IPL_SOFTBIO,
|
||||
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
|
||||
[SI_SOFTNET] = IPL_SOFTNET,
|
||||
[SI_SOFTSERIAL] = IPL_SOFTSERIAL,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Clearing interrupt pending bits affects some built-in
|
||||
@ -130,10 +134,10 @@ s3c2800_irq_handler(struct clockframe *frame)
|
||||
s3c2xx0_setipl(saved_spl_level);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
if (softint_pending & intr_mask)
|
||||
s3c2xx0_do_pending(1);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static const u_char s3c2800_ist[] = {
|
||||
@ -195,13 +199,14 @@ s3c2800_intr_establish(int irqno, int level, int type,
|
||||
static void
|
||||
init_interrupt_masks(void)
|
||||
{
|
||||
int i;
|
||||
int i = 0;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
s3c2xx0_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
|
||||
SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
|
||||
SI_TO_IRQBIT(SI_SOFT);
|
||||
SI_TO_IRQBIT(SI_SOFTBIO);
|
||||
|
||||
s3c2xx0_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
|
||||
s3c2xx0_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
|
||||
SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK);
|
||||
|
||||
/*
|
||||
@ -221,6 +226,7 @@ init_interrupt_masks(void)
|
||||
|
||||
for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
|
||||
s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
#endif
|
||||
for (; i < NIPL; ++i)
|
||||
s3c2xx0_imask[i] = 0;
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2800_intr.h,v 1.4 2005/12/11 12:16:51 christos Exp $ */
|
||||
/* $NetBSD: s3c2800_intr.h,v 1.5 2008/01/06 01:37:56 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Fujitsu Component Limited
|
||||
@ -41,6 +41,7 @@
|
||||
|
||||
#include <arm/s3c2xx0/s3c2800reg.h>
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/*
|
||||
* on S3C2800's interrupt controller, interrupt source bits 9, and 29..31 are
|
||||
* reserved. we map software interrupts to those unused bits.
|
||||
@ -49,6 +50,8 @@
|
||||
|
||||
#define get_pending_softint() (softint_pending & intr_mask)
|
||||
#define update_softintr_mask() /* empty */
|
||||
#endif
|
||||
|
||||
#define s3c2xx0_update_hw_mask() \
|
||||
(*s3c2xx0_intr_mask_reg = intr_mask & global_intr_mask)
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2800_pci.c,v 1.12 2007/03/04 05:59:38 christos Exp $ */
|
||||
/* $NetBSD: s3c2800_pci.c,v 1.13 2008/01/06 01:37:56 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Fujitsu Component Limited
|
||||
@ -100,7 +100,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.12 2007/03/04 05:59:38 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.13 2008/01/06 01:37:56 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -258,10 +258,10 @@ sspci_attach(struct device *parent, struct device *self, void *aux)
|
||||
sspci_intr, sc))
|
||||
FAIL("intr_establish");
|
||||
|
||||
sc->sc_softinterrupt = softintr_establish(IPL_SOFT,
|
||||
sc->sc_softinterrupt = softint_establish(SOFTINT_SERIAL,
|
||||
sspci_softintr, sc);
|
||||
if (sc->sc_softinterrupt == NULL)
|
||||
FAIL("softintr_establish");
|
||||
FAIL("softint_establish");
|
||||
|
||||
#if defined(PCI_NETBSD_CONFIGURE)
|
||||
if (sspci_init_controller(sc)) {
|
||||
@ -686,7 +686,7 @@ sspci_intr(void *arg)
|
||||
|
||||
if (interrupts & PCIINT_INA) {
|
||||
s = splhigh();
|
||||
softintr_schedule(sc->sc_softinterrupt);
|
||||
softint_schedule(sc->sc_softinterrupt);
|
||||
|
||||
/* mask INTA itnerrupt until softinterrupt is handled */
|
||||
sc->sc_pciinten &= ~PCIINT_INA;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2xx0_intr.c,v 1.11 2006/11/24 21:20:05 wiz Exp $ */
|
||||
/* $NetBSD: s3c2xx0_intr.c,v 1.12 2008/01/06 01:37:56 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003 Fujitsu Component Limited
|
||||
@ -73,7 +73,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.11 2006/11/24 21:20:05 wiz Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.12 2008/01/06 01:37:56 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -111,7 +111,7 @@ s3c2xx0_update_intr_masks(int irqno, int level)
|
||||
s3c2xx0_imask[i] |= mask; /* Enable interrupt at lower
|
||||
* level */
|
||||
for (; i < NIPL - 1; ++i)
|
||||
s3c2xx0_imask[i] &= ~mask; /* Disable itnerrupt at upper
|
||||
s3c2xx0_imask[i] &= ~mask; /* Disable interrupt at upper
|
||||
* level */
|
||||
|
||||
/*
|
||||
@ -119,42 +119,12 @@ s3c2xx0_update_intr_masks(int irqno, int level)
|
||||
* limited input buffer space/"real-time" requirements) a better
|
||||
* chance at not dropping data.
|
||||
*/
|
||||
s3c2xx0_imask[IPL_BIO] &= s3c2xx0_imask[IPL_SOFTNET];
|
||||
s3c2xx0_imask[IPL_NET] &= s3c2xx0_imask[IPL_BIO];
|
||||
s3c2xx0_imask[IPL_SOFTSERIAL] &= s3c2xx0_imask[IPL_NET];
|
||||
s3c2xx0_imask[IPL_TTY] &= s3c2xx0_imask[IPL_SOFTSERIAL];
|
||||
|
||||
/*
|
||||
* splvm() blocks all interrupts that use the kernel memory
|
||||
* allocation facilities.
|
||||
*/
|
||||
s3c2xx0_imask[IPL_VM] &= s3c2xx0_imask[IPL_TTY];
|
||||
|
||||
/*
|
||||
* Audio devices are not allowed to perform memory allocation
|
||||
* in their interrupt routines, and they have fairly "real-time"
|
||||
* requirements, so give them a high interrupt priority.
|
||||
*/
|
||||
s3c2xx0_imask[IPL_AUDIO] &= s3c2xx0_imask[IPL_VM];
|
||||
|
||||
/*
|
||||
* splclock() must block anything that uses the scheduler.
|
||||
*/
|
||||
s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_AUDIO];
|
||||
|
||||
/*
|
||||
* splhigh() must block "everything".
|
||||
*/
|
||||
s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_STATCLOCK];
|
||||
|
||||
/*
|
||||
* XXX We need serial drivers to run at the absolute highest priority
|
||||
* in order to avoid overruns, so serial > high.
|
||||
*/
|
||||
s3c2xx0_imask[IPL_SERIAL] &= s3c2xx0_imask[IPL_HIGH];
|
||||
|
||||
s3c2xx0_imask[IPL_VM] &= s3c2xx0_imask[IPL_SOFTSERIAL];
|
||||
s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_VM];
|
||||
s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_CLOCK];
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void
|
||||
s3c2xx0_do_pending(int enable_int)
|
||||
{
|
||||
@ -185,14 +155,15 @@ s3c2xx0_do_pending(int enable_int)
|
||||
do {
|
||||
DO_SOFTINT(SI_SOFTSERIAL, IPL_SOFTSERIAL);
|
||||
DO_SOFTINT(SI_SOFTNET, IPL_SOFTNET);
|
||||
DO_SOFTINT(SI_SOFTBIO, IPL_SOFTBIO);
|
||||
DO_SOFTINT(SI_SOFTCLOCK, IPL_SOFTCLOCK);
|
||||
DO_SOFTINT(SI_SOFT, IPL_SOFT);
|
||||
} while (get_pending_softint());
|
||||
|
||||
__cpu_simple_unlock(&processing);
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
#endif /* __HAVE_FAST_SOFTINTS */
|
||||
|
||||
|
||||
static int
|
||||
@ -219,12 +190,12 @@ s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table, int icu_len)
|
||||
for (i = 0; i < icu_len; ++i) {
|
||||
dispatch_table[i].func = stray_interrupt;
|
||||
dispatch_table[i].cookie = (void *) (i);
|
||||
dispatch_table[i].level = IPL_BIO;
|
||||
dispatch_table[i].level = IPL_VM;
|
||||
}
|
||||
|
||||
global_intr_mask = ~0; /* no intr is globally blocked. */
|
||||
|
||||
_splraise(IPL_SERIAL);
|
||||
_splraise(IPL_VM);
|
||||
enable_interrupts(I32_bit);
|
||||
}
|
||||
|
||||
@ -261,9 +232,11 @@ _spllower(int ipl)
|
||||
return s3c2xx0_spllower(ipl);
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#undef _setsoftintr
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
return s3c2xx0_setsoftintr(si);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: s3c2xx0_intr.h,v 1.10 2005/12/24 20:06:52 perry Exp $ */
|
||||
/* $NetBSD: s3c2xx0_intr.h,v 1.11 2008/01/06 01:37:56 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003 Fujitsu Component Limited
|
||||
@ -77,7 +77,6 @@
|
||||
#include <arm/cpufunc.h>
|
||||
#include <machine/atomic.h>
|
||||
#include <machine/intr.h>
|
||||
#include <arm/softintr.h>
|
||||
|
||||
#include <arm/s3c2xx0/s3c2xx0reg.h>
|
||||
|
||||
@ -88,11 +87,15 @@ extern volatile uint32_t *s3c2xx0_intr_mask_reg;
|
||||
extern volatile int current_spl_level;
|
||||
extern volatile int intr_mask;
|
||||
extern volatile int global_intr_mask;
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
extern volatile int softint_pending;
|
||||
#endif
|
||||
extern int s3c2xx0_imask[];
|
||||
extern int s3c2xx0_ilevel[];
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void s3c2xx0_do_pending(int);
|
||||
#endif
|
||||
void s3c2xx0_update_intr_masks( int, int );
|
||||
|
||||
static inline void
|
||||
@ -119,7 +122,9 @@ s3c2xx0_setipl(int new)
|
||||
current_spl_level = new;
|
||||
intr_mask = s3c2xx0_imask[current_spl_level];
|
||||
s3c2xx0_update_hw_mask();
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
update_softintr_mask();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -132,9 +137,11 @@ s3c2xx0_splx(int new)
|
||||
s3c2xx0_setipl(new);
|
||||
restore_interrupts(psw);
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/* If there are software interrupts to process, do it. */
|
||||
if (get_pending_softint())
|
||||
s3c2xx0_do_pending(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -163,6 +170,7 @@ s3c2xx0_spllower(int ipl)
|
||||
return(old);
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static inline void
|
||||
s3c2xx0_setsoftintr(int si)
|
||||
{
|
||||
@ -173,21 +181,25 @@ s3c2xx0_setsoftintr(int si)
|
||||
/* Process unmasked pending soft interrupts. */
|
||||
if (get_pending_softint())
|
||||
s3c2xx0_do_pending(0);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#if !defined(EVBARM_SPL_NOINLINE)
|
||||
|
||||
#define splx(new) s3c2xx0_splx(new)
|
||||
#define _spllower(ipl) s3c2xx0_spllower(ipl)
|
||||
#define _splraise(ipl) s3c2xx0_splraise(ipl)
|
||||
#if 0
|
||||
#define _setsoftintr(si) s3c2xx0_setsoftintr(si)
|
||||
#endif
|
||||
|
||||
#endif /* !EVBARM_SPL_NOINTR */
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: becc_icu.c,v 1.9 2007/12/11 17:12:26 ad Exp $ */
|
||||
/* $NetBSD: becc_icu.c,v 1.10 2008/01/06 01:37:57 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Wasabi Systems, Inc.
|
||||
@ -40,7 +40,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: becc_icu.c,v 1.9 2007/12/11 17:12:26 ad Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: becc_icu.c,v 1.10 2008/01/06 01:37:57 matt Exp $");
|
||||
|
||||
#ifndef EVBARM_SPL_NOINLINE
|
||||
#define EVBARM_SPL_NOINLINE
|
||||
@ -244,6 +244,7 @@ _splraise(int ipl)
|
||||
return (becc_splraise(ipl));
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
@ -251,17 +252,16 @@ _setsoftintr(int si)
|
||||
becc_setsoftintr(si);
|
||||
}
|
||||
|
||||
static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
|
||||
IPL_SOFTBIO, /* SI_SOFTBIO */
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
static const int si_to_ipl[] = {
|
||||
[SI_SOFTBIO] = IPL_SOFTBIO,
|
||||
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
|
||||
[SI_SOFTNET] = IPL_SOFTNET,
|
||||
[SI_SOFTSERIAL] = IPL_SOFTSERIAL,
|
||||
};
|
||||
|
||||
int
|
||||
becc_softint(void *arg)
|
||||
{
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
|
||||
uint32_t new, oldirqstate;
|
||||
|
||||
@ -293,10 +293,10 @@ becc_softint(void *arg)
|
||||
__cpu_simple_unlock(&processing);
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* becc_icu_init:
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: becc_intr.h,v 1.2 2005/12/24 20:06:52 perry Exp $ */
|
||||
/* $NetBSD: becc_intr.h,v 1.3 2008/01/06 01:37:57 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Wasabi Systems, Inc.
|
||||
@ -106,6 +106,7 @@ becc_spllower(int ipl)
|
||||
return (old);
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static inline void __attribute__((__unused__))
|
||||
becc_setsoftintr(int si)
|
||||
{
|
||||
@ -116,20 +117,25 @@ becc_setsoftintr(int si)
|
||||
}
|
||||
|
||||
int becc_softint(void *arg);
|
||||
#endif
|
||||
|
||||
#if !defined(EVBARM_SPL_NOINLINE)
|
||||
|
||||
#define _splraise(ipl) becc_splraise(ipl)
|
||||
#define splx(new) becc_splx(new)
|
||||
#define _spllower(ipl) becc_spllower(ipl)
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define _setsoftintr(si) becc_setsoftintr(si)
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
int _splraise(int);
|
||||
void splx(int);
|
||||
int _spllower(int);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#endif /* ! EVBARM_SPL_NOINLINE */
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: becc_timer.c,v 1.12 2007/12/11 17:03:35 ad Exp $ */
|
||||
/* $NetBSD: becc_timer.c,v 1.13 2008/01/06 01:37:57 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
@ -40,7 +40,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: becc_timer.c,v 1.12 2007/12/11 17:03:35 ad Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: becc_timer.c,v 1.13 2008/01/06 01:37:57 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -162,8 +162,10 @@ cpu_initclocks(void)
|
||||
/* ...and start it in motion. */
|
||||
BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM);
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/* register soft interrupt handler as well */
|
||||
becc_intr_establish(ICU_SOFT, IPL_SOFTCLOCK, becc_softint, NULL);
|
||||
#endif
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: i80321_icu.c,v 1.16 2007/12/11 17:12:27 ad Exp $ */
|
||||
/* $NetBSD: i80321_icu.c,v 1.17 2008/01/06 01:37:57 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002, 2006 Wasabi Systems, Inc.
|
||||
@ -36,7 +36,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: i80321_icu.c,v 1.16 2007/12/11 17:12:27 ad Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: i80321_icu.c,v 1.17 2008/01/06 01:37:57 matt Exp $");
|
||||
|
||||
#ifndef EVBARM_SPL_NOINLINE
|
||||
#define EVBARM_SPL_NOINLINE
|
||||
@ -83,6 +83,7 @@ uint32_t intr_steer;
|
||||
* ICU registers -- XXX will need to revisit this if those bits are
|
||||
* ever used in future steppings).
|
||||
*/
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static const uint32_t si_to_irqbit[4] = {
|
||||
ICU_INT_bit26, /* SI_SOFTCLOCK */
|
||||
ICU_INT_bit22, /* SI_SOFTBIO */
|
||||
@ -101,6 +102,7 @@ static const int si_to_ipl[4] = {
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interrupt bit names.
|
||||
@ -221,10 +223,12 @@ i80321_intr_calculate_masks(void)
|
||||
* limited input buffer space/"real-time" requirements) a better
|
||||
* chance at not dropping data.
|
||||
*/
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
i80321_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
|
||||
i80321_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO);
|
||||
i80321_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
|
||||
i80321_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
#endif
|
||||
|
||||
i80321_imask[IPL_SOFTBIO] |= i80321_imask[IPL_SOFTCLOCK];
|
||||
i80321_imask[IPL_SOFTNET] |= i80321_imask[IPL_SOFTBIO];
|
||||
@ -280,7 +284,7 @@ i80321_do_pending(void)
|
||||
__cpu_simple_unlock(&processing);
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
#endif
|
||||
#endif /* __HAVE_FAST_SOFTINTRS */
|
||||
}
|
||||
|
||||
void
|
||||
@ -304,6 +308,7 @@ _splraise(int ipl)
|
||||
return (i80321_splraise(ipl));
|
||||
}
|
||||
|
||||
#if __HAVE_FAST_SOFTINTRS
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
@ -317,6 +322,7 @@ _setsoftintr(int si)
|
||||
if ((i80321_ipending & INT_SWMASK) & ~current_spl_level)
|
||||
i80321_do_pending();
|
||||
}
|
||||
#endif /* __HAVE_FAST_SOFTINTRS */
|
||||
|
||||
/*
|
||||
* i80321_icu_init:
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: obio.c,v 1.5 2006/12/18 15:32:10 nonaka Exp $ */
|
||||
/* $NetBSD: obio.c,v 1.6 2008/01/06 01:37:57 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003, 2005 Genetec corp. All rights reserved.
|
||||
@ -134,7 +134,7 @@ obio_intr(void *arg)
|
||||
|
||||
if (n > 0) {
|
||||
/* handle it later */
|
||||
softintr_schedule(sc->sc_si);
|
||||
softint_schedule(sc->sc_si);
|
||||
}
|
||||
|
||||
/* GPIO interrupt is edge triggered. make a pulse
|
||||
@ -148,7 +148,7 @@ obio_intr(void *arg)
|
||||
}
|
||||
|
||||
static void
|
||||
obio_softintr(void *arg)
|
||||
obio_softint(void *arg)
|
||||
{
|
||||
struct obio_softc *sc = (struct obio_softc *)arg;
|
||||
int irqno;
|
||||
@ -252,7 +252,7 @@ obio_attach(struct device *parent, struct device *self, void *aux)
|
||||
sc->sc_ipl = IPL_AUDIO;
|
||||
sc->sc_ih = pxa2x0_gpio_intr_establish(0, IST_EDGE_FALLING, sc->sc_ipl,
|
||||
obio_intr, sc);
|
||||
sc->sc_si = softintr_establish(IPL_SOFTNET, obio_softintr, sc);
|
||||
sc->sc_si = softint_establish(SOFTINT_NET, obio_softint, sc);
|
||||
|
||||
reg = bus_space_read_2(iot, sc->sc_obioreg_ioh, G42XXEB_PLDVER);
|
||||
aprint_normal(": board %d version %x\n", reg>>8, reg & 0xff);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ifpga_intr.c,v 1.6 2008/01/05 12:40:34 ad Exp $ */
|
||||
/* $NetBSD: ifpga_intr.c,v 1.7 2008/01/06 01:37:57 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
@ -74,16 +74,17 @@ volatile uint32_t intr_enabled;
|
||||
/* Mask if interrupts steered to FIQs. */
|
||||
uint32_t intr_steer;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/*
|
||||
* Map a software interrupt queue index (to the unused bits in the
|
||||
* ICU registers -- XXX will need to revisit this if those bits are
|
||||
* ever used in future steppings).
|
||||
*/
|
||||
static const uint32_t si_to_irqbit[SI_NQUEUES] = {
|
||||
IFPGA_INTR_bit31, /* SI_SOFTCLOCK */
|
||||
IFPGA_INTR_bit30, /* SI_SOFTBIO */
|
||||
IFPGA_INTR_bit29, /* SI_SOFTNET */
|
||||
IFPGA_INTR_bit28, /* SI_SOFTSERIAL */
|
||||
static const uint32_t si_to_irqbit[] = {
|
||||
[SI_SOFTCLOCK] = IFPGA_INTR_bit31,
|
||||
[SI_SOFTBIO] = IFPGA_INTR_bit30,
|
||||
[SI_SOFTNET] = IFPGA_INTR_bit29,
|
||||
[SI_SOFTSERIAL] = IFPGA_INTR_bit28,
|
||||
};
|
||||
|
||||
#define SI_TO_IRQBIT(si) (si_to_irqbit[(si)])
|
||||
@ -91,17 +92,18 @@ static const uint32_t si_to_irqbit[SI_NQUEUES] = {
|
||||
/*
|
||||
* Map a software interrupt queue to an interrupt priority level.
|
||||
*/
|
||||
static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
|
||||
IPL_SOFTBIO, /* SI_SOFTBIO */
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
static const int si_to_ipl[] = {
|
||||
[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
|
||||
[SI_SOFTBIO] = IPL_SOFTBIO,
|
||||
[SI_SOFTNET] = IPL_SOFTNET,
|
||||
[SI_SOFTSERIAL] = IPL_SOFTSERIAL,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interrupt bit names.
|
||||
*/
|
||||
const char *ifpga_irqnames[] = {
|
||||
const char * const ifpga_irqnames[] = {
|
||||
"soft", /* 0 */
|
||||
"uart 0", /* 1 */
|
||||
"uart 1", /* 2 */
|
||||
@ -194,8 +196,9 @@ ifpga_intr_calculate_masks(void)
|
||||
ifpga_imask[ipl] = irqs;
|
||||
}
|
||||
|
||||
ifpga_imask[IPL_NONE] = 0;
|
||||
KASSERT(ifpga_imask[IPL_NONE] == 0);
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/*
|
||||
* Initialize the soft interrupt masks to block themselves.
|
||||
*/
|
||||
@ -203,6 +206,7 @@ ifpga_intr_calculate_masks(void)
|
||||
ifpga_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO);
|
||||
ifpga_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
|
||||
ifpga_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enforce a hierarchy that gives "slow" device (or devices with
|
||||
@ -232,10 +236,10 @@ ifpga_intr_calculate_masks(void)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void
|
||||
ifpga_do_pending(void)
|
||||
{
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
|
||||
int new, oldirqstate;
|
||||
|
||||
@ -264,8 +268,8 @@ ifpga_do_pending(void)
|
||||
__cpu_simple_unlock(&processing);
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
splx(int new)
|
||||
@ -288,6 +292,7 @@ _splraise(int ipl)
|
||||
return (ifpga_splraise(ipl));
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
@ -301,6 +306,7 @@ _setsoftintr(int si)
|
||||
if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level)
|
||||
ifpga_do_pending();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ifpga_intr_init:
|
||||
@ -449,10 +455,12 @@ ifpga_intr_dispatch(struct clockframe *frame)
|
||||
|
||||
ci->ci_idepth--;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/* Check for pendings soft intrs. */
|
||||
if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level) {
|
||||
oldirqstate = enable_interrupts(I32_bit);
|
||||
ifpga_do_pending();
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ifpga_intr.h,v 1.6 2006/05/16 21:38:14 mrg Exp $ */
|
||||
/* $NetBSD: ifpga_intr.h,v 1.7 2008/01/06 01:37:58 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
@ -48,7 +48,9 @@
|
||||
#include <evbarm/ifpga/ifpgareg.h>
|
||||
#include <evbarm/ifpga/ifpgavar.h>
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void ifpga_do_pending(void);
|
||||
#endif
|
||||
|
||||
static inline void __attribute__((__unused__))
|
||||
ifpga_set_intrmask(void)
|
||||
@ -63,9 +65,11 @@ ifpga_set_intrmask(void)
|
||||
IFPGA_INTR_ENABLESET, mask);
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define INT_SWMASK \
|
||||
(IFPGA_INTR_bit31 | IFPGA_INTR_bit30 | \
|
||||
IFPGA_INTR_bit29 | IFPGA_INTR_bit28)
|
||||
#endif
|
||||
|
||||
static inline void __attribute__((__unused__))
|
||||
ifpga_splx(int new)
|
||||
@ -88,8 +92,10 @@ ifpga_splx(int new)
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
if ((ifpga_ipending & INT_SWMASK) & ~new)
|
||||
ifpga_do_pending();
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline int __attribute__((__unused__))
|
||||
@ -123,14 +129,18 @@ ifpga_spllower(int ipl)
|
||||
#define splx(new) ifpga_splx(new)
|
||||
#define _spllower(ipl) ifpga_spllower(ipl)
|
||||
#define _splraise(ipl) ifpga_splraise(ipl)
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#endif /* ! EVBARM_SPL_NOINLINE */
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: intr.h,v 1.18 2007/12/03 15:33:32 ad Exp $ */
|
||||
/* $NetBSD: intr.h,v 1.19 2008/01/06 01:37:58 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2003 Wasabi Systems, Inc.
|
||||
@ -41,16 +41,29 @@
|
||||
#ifdef _KERNEL
|
||||
|
||||
/* Interrupt priority "levels". */
|
||||
#define IPL_NONE 0 /* nothing */
|
||||
#define IPL_SOFTCLOCK 1 /* clock */
|
||||
#define IPL_SOFTBIO 2 /* block I/O */
|
||||
#define IPL_SOFTNET 3 /* software network interrupt */
|
||||
#define IPL_SOFTSERIAL 4 /* software serial interrupt */
|
||||
#define IPL_VM 5 /* memory allocation */
|
||||
#define IPL_SCHED 6 /* clock interrupt */
|
||||
#define IPL_HIGH 7 /* everything */
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define IPL_NONE 0 /* nothing */
|
||||
#define IPL_SOFTCLOCK 1 /* clock */
|
||||
#define IPL_SOFTBIO 2 /* block I/O */
|
||||
#define IPL_SOFTNET 3 /* software network interrupt */
|
||||
#define IPL_SOFTSERIAL 4 /* software serial interrupt */
|
||||
#define IPL_VM 5 /* memory allocation */
|
||||
#define IPL_SCHED 6 /* clock interrupt */
|
||||
#define IPL_HIGH 7 /* everything */
|
||||
|
||||
#define NIPL 8
|
||||
#else
|
||||
#define IPL_NONE 0 /* nothing */
|
||||
#define IPL_SOFTCLOCK IPL_NONE /* clock */
|
||||
#define IPL_SOFTBIO IPL_NONE /* block I/O */
|
||||
#define IPL_SOFTNET IPL_NONE /* software network interrupt */
|
||||
#define IPL_SOFTSERIAL IPL_NONE /* software serial interrupt */
|
||||
#define IPL_VM 1 /* memory allocation */
|
||||
#define IPL_SCHED 2 /* clock interrupt */
|
||||
#define IPL_HIGH 3 /* everything */
|
||||
|
||||
#define NIPL 4
|
||||
#endif
|
||||
|
||||
/* Interrupt sharing types. */
|
||||
#define IST_NONE 0 /* none */
|
||||
@ -68,12 +81,14 @@
|
||||
|
||||
/* Software interrupt priority levels */
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
#define SOFTIRQ_CLOCK 0
|
||||
#define SOFTIRQ_BIO 1
|
||||
#define SOFTIRQ_NET 2
|
||||
#define SOFTIRQ_SERIAL 3
|
||||
|
||||
#define SOFTIRQ_BIT(x) (1 << x)
|
||||
#endif
|
||||
|
||||
#include <arm/arm32/psl.h>
|
||||
|
||||
@ -91,7 +106,9 @@
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#else /* _LKM */
|
||||
|
||||
@ -105,7 +122,6 @@ void _setsoftintr(int);
|
||||
* int _splraise(int);
|
||||
* int _spllower(int);
|
||||
* void splx(int);
|
||||
* void _setsoftintr(int);
|
||||
*
|
||||
* These may be defined as functions, static inline functions, or macros,
|
||||
* but there must be a _spllower() and splx() defined as functions callable
|
||||
@ -141,8 +157,6 @@ void _setsoftintr(int);
|
||||
|
||||
#endif /* _LKM */
|
||||
|
||||
#define splsoft() _splraise(IPL_SOFT)
|
||||
|
||||
typedef uint8_t ipl_t;
|
||||
typedef struct {
|
||||
ipl_t _ipl;
|
||||
@ -166,9 +180,6 @@ splraiseipl(ipl_cookie_t icookie)
|
||||
|
||||
#include <sys/spl.h>
|
||||
|
||||
/* Use generic software interrupt support. */
|
||||
#include <arm/softintr.h>
|
||||
|
||||
#endif /* ! _LOCORE */
|
||||
|
||||
#endif /* __OLD_INTERRUPT_CODE */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: iq80310_intr.c,v 1.24 2006/11/24 21:20:05 wiz Exp $ */
|
||||
/* $NetBSD: iq80310_intr.c,v 1.25 2008/01/06 01:37:58 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
@ -36,7 +36,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: iq80310_intr.c,v 1.24 2006/11/24 21:20:05 wiz Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: iq80310_intr.c,v 1.25 2008/01/06 01:37:58 matt Exp $");
|
||||
|
||||
#ifndef EVBARM_SPL_NOINLINE
|
||||
#define EVBARM_SPL_NOINLINE
|
||||
@ -79,6 +79,7 @@ volatile int iq80310_ipending;
|
||||
/* Software copy of the IRQs we have enabled. */
|
||||
uint32_t intr_enabled;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTRS
|
||||
/*
|
||||
* Map a software interrupt queue index (at the top of the word, and
|
||||
* highest priority softintr is encountered first in an ffs()).
|
||||
@ -94,6 +95,7 @@ static const int si_to_ipl[SI_NQUEUES] = {
|
||||
IPL_SOFTNET, /* SI_SOFTNET */
|
||||
IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
|
||||
};
|
||||
#endif
|
||||
|
||||
void iq80310_intr_dispatch(struct irqframe *frame);
|
||||
|
||||
@ -173,21 +175,9 @@ iq80310_intr_calculate_masks(void)
|
||||
}
|
||||
|
||||
iq80310_imask[IPL_NONE] = 0;
|
||||
|
||||
/*
|
||||
* Initialize the soft interrupt masks to block themselves.
|
||||
*/
|
||||
iq80310_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
|
||||
iq80310_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
|
||||
iq80310_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
|
||||
iq80310_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
|
||||
|
||||
/*
|
||||
* splsoftclock() is the only interface that users of the
|
||||
* generic software interrupt facility have to block their
|
||||
* soft intrs, so splsoftclock() must also block IPL_SOFT.
|
||||
*/
|
||||
iq80310_imask[IPL_SOFTCLOCK] |= iq80310_imask[IPL_SOFT];
|
||||
iq80310_imask[IPL_SOFTCLOCK] = 0;
|
||||
iq80310_imask[IPL_SOFTNET] = 0;
|
||||
iq80310_imask[IPL_SOFTSERIAL] = 0;
|
||||
|
||||
/*
|
||||
* splsoftnet() must also block splsoftclock(), since we don't
|
||||
@ -227,12 +217,18 @@ iq80310_intr_calculate_masks(void)
|
||||
/*
|
||||
* No separate statclock on the IQ80310.
|
||||
*/
|
||||
#ifdef IPL_STATCLOCK
|
||||
iq80310_imask[IPL_STATCLOCK] |= iq80310_imask[IPL_CLOCK];
|
||||
#endif
|
||||
|
||||
/*
|
||||
* splhigh() must block "everything".
|
||||
*/
|
||||
#ifdef IPL_STATCLOCK
|
||||
iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_STATCLOCK];
|
||||
#else
|
||||
iq80310_imask[IPL_HIGH] |= iq80310_imask[IPL_CLOCK];
|
||||
#endif
|
||||
|
||||
/*
|
||||
* XXX We need serial drivers to run at the absolute highest priority
|
||||
@ -256,6 +252,7 @@ iq80310_intr_calculate_masks(void)
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTRS
|
||||
void
|
||||
iq80310_do_soft(void)
|
||||
{
|
||||
@ -288,6 +285,7 @@ iq80310_do_soft(void)
|
||||
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
#endif /* __HAVE_SOFT_FASTINTRS */
|
||||
|
||||
int
|
||||
_splraise(int ipl)
|
||||
@ -310,6 +308,7 @@ _spllower(int ipl)
|
||||
return (iq80310_spllower(ipl));
|
||||
}
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTRS
|
||||
void
|
||||
_setsoftintr(int si)
|
||||
{
|
||||
@ -323,6 +322,7 @@ _setsoftintr(int si)
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level)
|
||||
iq80310_do_soft();
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
iq80310_intr_init(void)
|
||||
@ -466,12 +466,14 @@ iq80310_intr_dispatch(struct irqframe *frame)
|
||||
printf("Stray external interrupt\n");
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* Check for pendings soft intrs. */
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~current_spl_level) {
|
||||
oldirqstate = enable_interrupts(I32_bit);
|
||||
iq80310_do_soft();
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If no hardware interrupts are masked, re-enable external
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: iq80310_intr.h,v 1.5 2005/12/24 20:06:59 perry Exp $ */
|
||||
/* $NetBSD: iq80310_intr.h,v 1.6 2008/01/06 01:37:58 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
@ -66,7 +66,9 @@
|
||||
#define IRQ_READ_XINT0 1 /* XXX only if board rev >= F */
|
||||
#endif /* list of IQ80310-based designs */
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void iq80310_do_soft(void);
|
||||
#endif
|
||||
|
||||
static inline int __attribute__((__unused__))
|
||||
iq80310_splraise(int ipl)
|
||||
@ -97,9 +99,11 @@ iq80310_splx(int new)
|
||||
old = current_spl_level;
|
||||
current_spl_level = new;
|
||||
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
/* If there are software interrupts to process, do it. */
|
||||
if ((iq80310_ipending & ~IRQ_BITS) & ~new)
|
||||
iq80310_do_soft();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If there are pending hardware interrupts (i.e. the
|
||||
@ -131,14 +135,18 @@ iq80310_spllower(int ipl)
|
||||
#define _splraise(ipl) iq80310_splraise(ipl)
|
||||
#define _spllower(ipl) iq80310_spllower(ipl)
|
||||
#define splx(spl) iq80310_splx(spl)
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
int _splraise(int);
|
||||
int _spllower(int);
|
||||
void splx(int);
|
||||
#ifdef __HAVE_FAST_SOFTINTS
|
||||
void _setsoftintr(int);
|
||||
#endif
|
||||
|
||||
#endif /* ! EVBARM_SPL_NOINLINE */
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: smdk2410_kbd.c,v 1.4 2007/03/04 05:59:45 christos Exp $ */
|
||||
/* $NetBSD: smdk2410_kbd.c,v 1.5 2008/01/06 01:37:58 matt Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Genetec Corporation. All rights reserved.
|
||||
@ -40,7 +40,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: smdk2410_kbd.c,v 1.4 2007/03/04 05:59:45 christos Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: smdk2410_kbd.c,v 1.5 2008/01/06 01:37:58 matt Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -320,8 +320,7 @@ sskbd_attach(struct device *parent, struct device *self, void *aux)
|
||||
sc->spi_ih = s3c24x0_intr_establish(spia->spia_intr, IPL_SERIAL,
|
||||
0, sskbd_spi_intr, sc);
|
||||
|
||||
sc->soft_ih = softintr_establish(IPL_SOFTSERIAL, sskbd_soft_intr,
|
||||
sc);
|
||||
sc->soft_ih = softint_establish(SOFTINT_SERIAL, sskbd_soft_intr, sc);
|
||||
|
||||
if (sc->atn_ih == NULL || sc->spi_ih == NULL)
|
||||
aprint_error("%s: can't establish interrupt handler\n",
|
||||
@ -361,7 +360,7 @@ sskbd_atn_intr(void *arg)
|
||||
|
||||
if (advance_ring_ptr(sc->inptr) == sc->outptr) {
|
||||
/* ring buffer is full. ignore this nATN signale */
|
||||
softintr_schedule(sc->soft_ih);
|
||||
softint_schedule(sc->soft_ih);
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -406,7 +405,7 @@ sskbd_spi_intr(void *arg)
|
||||
sc->ring[sc->inptr] = data;
|
||||
sc->inptr = advance_ring_ptr(sc->inptr);
|
||||
|
||||
softintr_schedule(sc->soft_ih);
|
||||
softint_schedule(sc->soft_ih);
|
||||
}
|
||||
#ifdef KBD_DEBUG
|
||||
else {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user