Update instruction numbers in comments
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skrll
parent
19584ea1f8
commit
2533f55817
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@ -1,4 +1,4 @@
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/* $NetBSD: mipsX_subr.S,v 1.71 2016/07/12 03:34:50 matt Exp $ */
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/* $NetBSD: mipsX_subr.S,v 1.72 2016/07/17 12:56:12 skrll Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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@ -373,30 +373,30 @@ VECTOR(MIPSX(tlb_miss), unknown)
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nop #01: nop
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PTR_SRL k1, k0, 31 #02: clear useg bits
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beqz k1, 1f #03: k1==0 -> useg address
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PTR_SRL k1,k0,2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)+PGSHIFT #05: clear valid bits
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bnez k1, MIPSX(nopagetable) #04: not legal address
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PTR_SRL k0, 2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #05: k0=seg offset (almost)
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bgez k0, 1f #05: k0<0 -> kernel fault
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lui k1, %hi(CPUVAR(PMAP_SEGTAB)) #06: k1=hi of segtab
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PTR_ADDI k1, 1 << PTR_SCALESHIFT #07: kernel segtab entry
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PTR_SRL k1,k0,2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)+PGSHIFT #04: clear valid bits
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bnez k1, MIPSX(nopagetable) #05: not legal address
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PTR_SRL k0, 2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #06: k0=seg offset (almost)
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bgez k0, 1f #07: k0<0 -> kernel fault
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lui k1, %hi(CPUVAR(PMAP_SEGTAB)) #08: k1=hi of segtab
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PTR_ADDI k1, 1 << PTR_SCALESHIFT #09: kernel segtab entry
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1:
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andi k0, NBPG-(1<<PTR_SCALESHIFT) #08: k0=seg offset (mask 0x3)
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PTR_L k1, %lo(CPUVAR(PMAP_SEGTAB))(k1)#09: k1=segment tab
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PTR_ADDU k1, k0 #0a: k1=seg entry address
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dmfc0 k0, MIPS_COP_0_BAD_VADDR #0b: k0=bad address (again)
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PTR_L k1, 0(k1) #0c: k1=seg entry
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b MIPSX(tlb_miss_common) #0d
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PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #0e: k0=seg offset (almost)
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andi k0, NBPG-(1<<PTR_SCALESHIFT) #0a: k0=seg offset (mask 0x3)
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PTR_L k1, %lo(CPUVAR(PMAP_SEGTAB))(k1)#0b: k1=segment tab
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PTR_ADDU k1, k0 #0c: k1=seg entry address
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dmfc0 k0, MIPS_COP_0_BAD_VADDR #0d: k0=bad address (again)
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PTR_L k1, 0(k1) #0e: k1=seg entry
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b MIPSX(tlb_miss_common) #0f
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PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #10: k0=seg offset (almost)
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#endif /* LP64 */
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1: /* handle useg addresses */
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lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #0f: k1=hi of seg0tab
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dsrl k0, 31 #11: clear low 31 bits
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bnez k0, MIPSX(nopagetable) #12: not legal address
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PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#13: k1=segment tab base
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dmfc0 k0, MIPS_COP_0_BAD_VADDR #14: k0=bad address (again)
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nop #15
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b MIPSX(tlb_miss_common) #16
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PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #17: k0=seg offset (almost)
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lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #11: k1=hi of seg0tab
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dsrl k0, 31 #12: clear low 31 bits
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bnez k0, MIPSX(nopagetable) #13: not legal address
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PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#14: k1=segment tab base
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dmfc0 k0, MIPS_COP_0_BAD_VADDR #15: k0=bad address (again)
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nop #16
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b MIPSX(tlb_miss_common) #17
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PTR_SRL k0, 1*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #18: k0=seg offset (almost)
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_VECTOR_END(MIPSX(tlb_miss))
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/* dummy xtlb_miss (also a placeholder for tlb_miss_common) */
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VECTOR(MIPSX(xtlb_miss), unknown)
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@ -431,75 +431,75 @@ VECTOR(MIPSX(tlb_miss), unknown)
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#endif /* !MIPS3_LOONGSON2 */
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MIPSX(tlb_miss_common):
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#ifdef _LP64
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beqz k1, MIPSX(nopagetable) #05: is there a pagetable?
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beqz k1, MIPSX(nopagetable) #06: is there a pagetable?
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#endif
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/* the next instruction might be in a delay slot */
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#ifdef MIPSNNR2
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_INS k1, k0, PTR_SCALESHIFT, SEGLENGTH #06: k1=seg entry address
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_INS k1, k0, PTR_SCALESHIFT, SEGLENGTH #07: k1=seg entry address
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#else
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andi k0, (NSEGPG-1)<<PTR_SCALESHIFT #06: k0=seg offset (mask 0x3)
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PTR_ADDU k1, k0 #07: k1=seg entry address
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andi k0, (NSEGPG-1)<<PTR_SCALESHIFT #07: k0=seg offset (mask 0x3)
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PTR_ADDU k1, k0 #08: k1=seg entry address
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#endif
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PTR_L k1, 0(k1) #08: k1=seg entry
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_MFC0 k0, MIPS_COP_0_BAD_VADDR #09: k0=bad address (again)
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beqz k1, MIPSX(nopagetable) #0a: ==0 -- no page table
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PTR_L k1, 0(k1) #09: k1=seg entry
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_MFC0 k0, MIPS_COP_0_BAD_VADDR #0a: k0=bad address (again)
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beqz k1, MIPSX(nopagetable) #0b: ==0 -- no page table
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# delay slot varies
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#if (PGSHIFT & 1)
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#ifdef MIPSNNR2
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_EXT k0, k0, PGSHIFT, PTPLENGTH #0b: delay slot: page index
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_INS k1, k0, PTPSHIFT, PTPLENGTH #0c: k1=pte address
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_EXT k0, k0, PGSHIFT, PTPLENGTH #0c: delay slot: page index
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_INS k1, k0, PTPSHIFT, PTPLENGTH #0d: k1=pte address
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#else
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PTR_SRL k0, PGSHIFT - PTPSHIFT #0b: k0=VPN (aka va>>10)
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andi k0, (NPTEPG-1) << PTPSHIFT #0c: k0=page table offset
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PTR_ADDU k1, k0 #0d: k1=pte address
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PTR_SRL k0, PGSHIFT - PTPSHIFT #0c: k0=VPN (aka va>>10)
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andi k0, (NPTEPG-1) << PTPSHIFT #0d: k0=page table offset
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PTR_ADDU k1, k0 #0e: k1=pte address
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#endif
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INT_L k0, 0(k1) #0e: k0=lo0 pte
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INT_L k0, 0(k1) #0f: k0=lo0 pte
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#ifdef MIPSNNR2
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_EXT k0, k0, 0, WIRED_POS #0f: chop top 2 bits
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_EXT k0, k0, 0, WIRED_POS #10: chop top 2 bits
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#else
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_SLL k0, WIRED_SHIFT #0f: chop top 2 bits (part 1a)
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_SRL k0, WIRED_SHIFT #10: chop top 2 bits (part 1b)
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#endif
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INT_ADDU k1, k0, MIPS3_PG_NEXT #11: k1=lo1 pte
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#else /* (PGSHIFT & 1) == 0 */
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PTR_SRL k0, PGSHIFT - PTPSHIFT #0b: k0=VPN (aka va>>10) --ds--
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andi k0, (NPTEPG/2-1) << (PTPSHIFT+1)#0c: k0=page table offset
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PTR_ADDU k1, k0 #0d: k1=pte address
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#ifdef USE_64BIT_CP0_FUNCTIONS
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ld k0, 0(k1) #0e: load both ptes
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#ifdef MIPSNNR2
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_EXT k1, k0, 32*_QUAD_HIGHWORD, WIRED_POS #0f: get lo1 pte
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_EXT k0, k0, 32*_QUAD_LOWWORD, WIRED_POS #10: get lo0 pte
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#else
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_SLL k1, k0, WIRED_SHIFT - 32*_QUAD_HIGHWORD #0f: get lo1 pte (1a)
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_SLL k0, k0, WIRED_SHIFT - 32*_QUAD_LOWWORD #10: get lo0 pte (2a)
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_SRL k0, WIRED_SHIFT #11: chopped top 2 bits (1b)
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_SRL k1, WIRED_SHIFT #12: chopped top 2 bits (2b)
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#endif
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#else
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INT_L k0, 0(k1) #0e: k0=lo0 pte
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INT_L k1, 4(k1) #0f: k1=lo1 pte
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_SLL k0, WIRED_SHIFT #10: chop top 2 bits (part 1a)
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_SLL k1, WIRED_SHIFT #11: chop top 2 bits (part 2a)
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_SRL k0, WIRED_SHIFT #12: chop top 2 bits (part 1b)
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_SRL k1, WIRED_SHIFT #13: chop top 2 bits (part 2b)
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_SRL k0, WIRED_SHIFT #11: chop top 2 bits (part 1b)
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#endif
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INT_ADDU k1, k0, MIPS3_PG_NEXT #12: k1=lo1 pte
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#else /* (PGSHIFT & 1) == 0 */
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PTR_SRL k0, PGSHIFT - PTPSHIFT #0c: k0=VPN (aka va>>10) --ds--
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andi k0, (NPTEPG/2-1) << (PTPSHIFT+1)#0d: k0=page table offset
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PTR_ADDU k1, k0 #0e: k1=pte address
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#ifdef USE_64BIT_CP0_FUNCTIONS
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ld k0, 0(k1) #0f: load both ptes
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#ifdef MIPSNNR2
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_EXT k1, k0, 32*_QUAD_HIGHWORD, WIRED_POS #10: get lo1 pte
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_EXT k0, k0, 32*_QUAD_LOWWORD, WIRED_POS #11: get lo0 pte
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#else
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_SLL k1, k0, WIRED_SHIFT - 32*_QUAD_HIGHWORD #10: get lo1 pte (1a)
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_SLL k0, k0, WIRED_SHIFT - 32*_QUAD_LOWWORD #11: get lo0 pte (2a)
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_SRL k0, WIRED_SHIFT #12: chopped top 2 bits (1b)
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_SRL k1, WIRED_SHIFT #13: chopped top 2 bits (2b)
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#endif
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#else
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INT_L k0, 0(k1) #0f: k0=lo0 pte
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INT_L k1, 4(k1) #10: k1=lo1 pte
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_SLL k0, WIRED_SHIFT #11: chop top 2 bits (part 1a)
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_SLL k1, WIRED_SHIFT #12: chop top 2 bits (part 2a)
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_SRL k0, WIRED_SHIFT #13: chop top 2 bits (part 1b)
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_SRL k1, WIRED_SHIFT #14: chop top 2 bits (part 2b)
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#endif
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#endif /* PGSHIFT & 1 */
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_MTC0 k0, MIPS_COP_0_TLB_LO0 #14: lo0 is loaded
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_MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded
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sll $0, $0, 3 #16: standard nop (ehb)
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_MTC0 k0, MIPS_COP_0_TLB_LO0 #15: lo0 is loaded
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_MTC0 k1, MIPS_COP_0_TLB_LO1 #16: lo1 is loaded
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sll $0, $0, 3 #17: standard nop (ehb)
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#ifdef MIPS3
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nop #17: extra nop for QED5230
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nop #18: extra nop for QED5230
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#endif
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tlbwr #18: write to tlb
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sll $0, $0, 3 #19: standard nop (ehb)
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tlbwr #19: write to tlb
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sll $0, $0, 3 #1a: standard nop (ehb)
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#if (MIPS3 + MIPS64 + MIPS64R2) > 0
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lui k1, %hi(CPUVAR(EV_TLBMISSES)) #1a: k1=hi of tlbmisses
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REG_L k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1b
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REG_ADDU k0, 1 #1c
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REG_S k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1d
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lui k1, %hi(CPUVAR(EV_TLBMISSES)) #1b: k1=hi of tlbmisses
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REG_L k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1c
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REG_ADDU k0, 1 #1d
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REG_S k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1e
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#endif
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eret #1e: return from exception
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eret #1f: return from exception
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.set at
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#ifdef MIPS3_LOONGSON2
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_VECTOR_END(MIPSX(xtlb_miss))
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@ -549,20 +549,20 @@ VECTOR(MIPSX(xtlb_miss), unknown)
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lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #02: k1=hi of seg0tab
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bgez k0, 1f #03: k0<0 -> kernel access
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dsra k0, 31 #04: clear low 31 bits
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PTR_ADDU k1, 1 << PTR_SCALESHIFT
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PTR_ADDU k1, 1 << PTR_SCALESHIFT #05
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1:
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PTR_ADDU k0, 1
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sltiu k0, k0, 2
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beqz k0, MIPSX(nopagetable) #04: not legal address
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nop
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dmfc0 k0, MIPS_COP_0_BAD_VADDR #05: k0=bad address (again)
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PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#06: k1=segment tab base
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PTR_ADDU k0, 1 #06
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sltiu k0, k0, 2 #07
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beqz k0, MIPSX(nopagetable) #08: not legal address
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nop #09
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dmfc0 k0, MIPS_COP_0_BAD_VADDR #0a: k0=bad address (again)
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PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#0b: k1=segment tab base
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#endif /* _LP64 */
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b MIPSX(tlb_miss_common) #0e
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b MIPSX(tlb_miss_common) #0e/0c
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#ifdef MIPSNNR2
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_EXT k0, k0, SEGSHIFT, SEGLENGTH #0f: k0=seg index
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_EXT k0, k0, SEGSHIFT, SEGLENGTH #0f/0d: k0=seg index
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#else
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PTR_SRL k0, SEGSHIFT - PTR_SCALESHIFT #0f: k0=seg offset (almost)
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PTR_SRL k0, SEGSHIFT - PTR_SCALESHIFT #0f/0d: k0=seg offset (almost)
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#endif
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.set at
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_VECTOR_END(MIPSX(xtlb_miss))
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@ -576,13 +576,13 @@ _VECTOR_END(MIPSX(xtlb_miss))
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*/
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VECTOR(MIPSX(cache), unknown)
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PTR_LA k0, _C_LABEL(MIPSX(cache_exception)) #00
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li k1, MIPS_PHYS_MASK #02
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and k0, k1 #03
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li k1, MIPS_KSEG1_START #04
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or k0, k1 #05
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lui k1, %hi(CPUVAR(CURLWP)) #06: k1=hi of curlwp
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jr k0 #07
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PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #08: k1=lo of curlwp
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li k1, MIPS_PHYS_MASK #01
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and k0, k1 #02
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li k1, MIPS_KSEG1_START #03
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or k0, k1 #04
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lui k1, %hi(CPUVAR(CURLWP)) #05: k1=hi of curlwp
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jr k0 #06
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PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #07: k1=lo of curlwp
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_VECTOR_END(MIPSX(cache))
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/*
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@ -647,13 +647,13 @@ VECTOR(MIPSX(intr), unknown)
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MFC0_HAZARD #01: stall
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and k1, k1, MIPS3_SR_KSU_USER #02: test for user mode
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PTR_LA k0, MIPSX(user_intr) #03: assume user mode
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bnez k1, 1f #05: yep, do it
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nop #06: branch deay
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PTR_LA k0, MIPSX(kern_intr) #07: nope, kernel intr
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bnez k1, 1f #04: yep, do it
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nop #05: branch deay
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PTR_LA k0, MIPSX(kern_intr) #06: nope, kernel intr
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1:
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lui k1, %hi(CPUVAR(CURLWP)) #09: k1=hi of curlwp
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jr k0 #0a: jump to the function
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PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0b: k1=lo of curlwp
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lui k1, %hi(CPUVAR(CURLWP)) #07: k1=hi of curlwp
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jr k0 #08: jump to the function
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PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #09: k1=lo of curlwp
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.set at
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_VECTOR_END(MIPSX(intr))
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