From 2533f5581756c660aa54f449025ac6b009711cb4 Mon Sep 17 00:00:00 2001 From: skrll Date: Sun, 17 Jul 2016 12:56:12 +0000 Subject: [PATCH] Update instruction numbers in comments --- sys/arch/mips/mips/mipsX_subr.S | 190 ++++++++++++++++---------------- 1 file changed, 95 insertions(+), 95 deletions(-) diff --git a/sys/arch/mips/mips/mipsX_subr.S b/sys/arch/mips/mips/mipsX_subr.S index 0f8841b20d96..91cd6ad2744c 100644 --- a/sys/arch/mips/mips/mipsX_subr.S +++ b/sys/arch/mips/mips/mipsX_subr.S @@ -1,4 +1,4 @@ -/* $NetBSD: mipsX_subr.S,v 1.71 2016/07/12 03:34:50 matt Exp $ */ +/* $NetBSD: mipsX_subr.S,v 1.72 2016/07/17 12:56:12 skrll Exp $ */ /* * Copyright 2002 Wasabi Systems, Inc. @@ -373,30 +373,30 @@ VECTOR(MIPSX(tlb_miss), unknown) nop #01: nop PTR_SRL k1, k0, 31 #02: clear useg bits beqz k1, 1f #03: k1==0 -> useg address - PTR_SRL k1,k0,2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)+PGSHIFT #05: clear valid bits - bnez k1, MIPSX(nopagetable) #04: not legal address - PTR_SRL k0, 2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #05: k0=seg offset (almost) - bgez k0, 1f #05: k0<0 -> kernel fault - lui k1, %hi(CPUVAR(PMAP_SEGTAB)) #06: k1=hi of segtab - PTR_ADDI k1, 1 << PTR_SCALESHIFT #07: kernel segtab entry + PTR_SRL k1,k0,2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2)+PGSHIFT #04: clear valid bits + bnez k1, MIPSX(nopagetable) #05: not legal address + PTR_SRL k0, 2*(PGSHIFT-PTR_SCALESHIFT)+(PGSHIFT-2) #06: k0=seg offset (almost) + bgez k0, 1f #07: k0<0 -> kernel fault + lui k1, %hi(CPUVAR(PMAP_SEGTAB)) #08: k1=hi of segtab + PTR_ADDI k1, 1 << PTR_SCALESHIFT #09: kernel segtab entry 1: - andi k0, NBPG-(1<>10) - andi k0, (NPTEPG-1) << PTPSHIFT #0c: k0=page table offset - PTR_ADDU k1, k0 #0d: k1=pte address + PTR_SRL k0, PGSHIFT - PTPSHIFT #0c: k0=VPN (aka va>>10) + andi k0, (NPTEPG-1) << PTPSHIFT #0d: k0=page table offset + PTR_ADDU k1, k0 #0e: k1=pte address #endif - INT_L k0, 0(k1) #0e: k0=lo0 pte + INT_L k0, 0(k1) #0f: k0=lo0 pte #ifdef MIPSNNR2 - _EXT k0, k0, 0, WIRED_POS #0f: chop top 2 bits + _EXT k0, k0, 0, WIRED_POS #10: chop top 2 bits #else - _SLL k0, WIRED_SHIFT #0f: chop top 2 bits (part 1a) - _SRL k0, WIRED_SHIFT #10: chop top 2 bits (part 1b) -#endif - INT_ADDU k1, k0, MIPS3_PG_NEXT #11: k1=lo1 pte -#else /* (PGSHIFT & 1) == 0 */ - PTR_SRL k0, PGSHIFT - PTPSHIFT #0b: k0=VPN (aka va>>10) --ds-- - andi k0, (NPTEPG/2-1) << (PTPSHIFT+1)#0c: k0=page table offset - PTR_ADDU k1, k0 #0d: k1=pte address -#ifdef USE_64BIT_CP0_FUNCTIONS - ld k0, 0(k1) #0e: load both ptes -#ifdef MIPSNNR2 - _EXT k1, k0, 32*_QUAD_HIGHWORD, WIRED_POS #0f: get lo1 pte - _EXT k0, k0, 32*_QUAD_LOWWORD, WIRED_POS #10: get lo0 pte -#else - _SLL k1, k0, WIRED_SHIFT - 32*_QUAD_HIGHWORD #0f: get lo1 pte (1a) - _SLL k0, k0, WIRED_SHIFT - 32*_QUAD_LOWWORD #10: get lo0 pte (2a) - _SRL k0, WIRED_SHIFT #11: chopped top 2 bits (1b) - _SRL k1, WIRED_SHIFT #12: chopped top 2 bits (2b) -#endif -#else - INT_L k0, 0(k1) #0e: k0=lo0 pte - INT_L k1, 4(k1) #0f: k1=lo1 pte _SLL k0, WIRED_SHIFT #10: chop top 2 bits (part 1a) - _SLL k1, WIRED_SHIFT #11: chop top 2 bits (part 2a) - _SRL k0, WIRED_SHIFT #12: chop top 2 bits (part 1b) - _SRL k1, WIRED_SHIFT #13: chop top 2 bits (part 2b) + _SRL k0, WIRED_SHIFT #11: chop top 2 bits (part 1b) +#endif + INT_ADDU k1, k0, MIPS3_PG_NEXT #12: k1=lo1 pte +#else /* (PGSHIFT & 1) == 0 */ + PTR_SRL k0, PGSHIFT - PTPSHIFT #0c: k0=VPN (aka va>>10) --ds-- + andi k0, (NPTEPG/2-1) << (PTPSHIFT+1)#0d: k0=page table offset + PTR_ADDU k1, k0 #0e: k1=pte address +#ifdef USE_64BIT_CP0_FUNCTIONS + ld k0, 0(k1) #0f: load both ptes +#ifdef MIPSNNR2 + _EXT k1, k0, 32*_QUAD_HIGHWORD, WIRED_POS #10: get lo1 pte + _EXT k0, k0, 32*_QUAD_LOWWORD, WIRED_POS #11: get lo0 pte +#else + _SLL k1, k0, WIRED_SHIFT - 32*_QUAD_HIGHWORD #10: get lo1 pte (1a) + _SLL k0, k0, WIRED_SHIFT - 32*_QUAD_LOWWORD #11: get lo0 pte (2a) + _SRL k0, WIRED_SHIFT #12: chopped top 2 bits (1b) + _SRL k1, WIRED_SHIFT #13: chopped top 2 bits (2b) +#endif +#else + INT_L k0, 0(k1) #0f: k0=lo0 pte + INT_L k1, 4(k1) #10: k1=lo1 pte + _SLL k0, WIRED_SHIFT #11: chop top 2 bits (part 1a) + _SLL k1, WIRED_SHIFT #12: chop top 2 bits (part 2a) + _SRL k0, WIRED_SHIFT #13: chop top 2 bits (part 1b) + _SRL k1, WIRED_SHIFT #14: chop top 2 bits (part 2b) #endif #endif /* PGSHIFT & 1 */ - _MTC0 k0, MIPS_COP_0_TLB_LO0 #14: lo0 is loaded - _MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded - sll $0, $0, 3 #16: standard nop (ehb) + _MTC0 k0, MIPS_COP_0_TLB_LO0 #15: lo0 is loaded + _MTC0 k1, MIPS_COP_0_TLB_LO1 #16: lo1 is loaded + sll $0, $0, 3 #17: standard nop (ehb) #ifdef MIPS3 - nop #17: extra nop for QED5230 + nop #18: extra nop for QED5230 #endif - tlbwr #18: write to tlb - sll $0, $0, 3 #19: standard nop (ehb) + tlbwr #19: write to tlb + sll $0, $0, 3 #1a: standard nop (ehb) #if (MIPS3 + MIPS64 + MIPS64R2) > 0 - lui k1, %hi(CPUVAR(EV_TLBMISSES)) #1a: k1=hi of tlbmisses - REG_L k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1b - REG_ADDU k0, 1 #1c - REG_S k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1d + lui k1, %hi(CPUVAR(EV_TLBMISSES)) #1b: k1=hi of tlbmisses + REG_L k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1c + REG_ADDU k0, 1 #1d + REG_S k0, %lo(CPUVAR(EV_TLBMISSES))(k1) #1e #endif - eret #1e: return from exception + eret #1f: return from exception .set at #ifdef MIPS3_LOONGSON2 _VECTOR_END(MIPSX(xtlb_miss)) @@ -549,20 +549,20 @@ VECTOR(MIPSX(xtlb_miss), unknown) lui k1, %hi(CPUVAR(PMAP_SEG0TAB)) #02: k1=hi of seg0tab bgez k0, 1f #03: k0<0 -> kernel access dsra k0, 31 #04: clear low 31 bits - PTR_ADDU k1, 1 << PTR_SCALESHIFT + PTR_ADDU k1, 1 << PTR_SCALESHIFT #05 1: - PTR_ADDU k0, 1 - sltiu k0, k0, 2 - beqz k0, MIPSX(nopagetable) #04: not legal address - nop - dmfc0 k0, MIPS_COP_0_BAD_VADDR #05: k0=bad address (again) - PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#06: k1=segment tab base + PTR_ADDU k0, 1 #06 + sltiu k0, k0, 2 #07 + beqz k0, MIPSX(nopagetable) #08: not legal address + nop #09 + dmfc0 k0, MIPS_COP_0_BAD_VADDR #0a: k0=bad address (again) + PTR_L k1, %lo(CPUVAR(PMAP_SEG0TAB))(k1)#0b: k1=segment tab base #endif /* _LP64 */ - b MIPSX(tlb_miss_common) #0e + b MIPSX(tlb_miss_common) #0e/0c #ifdef MIPSNNR2 - _EXT k0, k0, SEGSHIFT, SEGLENGTH #0f: k0=seg index + _EXT k0, k0, SEGSHIFT, SEGLENGTH #0f/0d: k0=seg index #else - PTR_SRL k0, SEGSHIFT - PTR_SCALESHIFT #0f: k0=seg offset (almost) + PTR_SRL k0, SEGSHIFT - PTR_SCALESHIFT #0f/0d: k0=seg offset (almost) #endif .set at _VECTOR_END(MIPSX(xtlb_miss)) @@ -576,13 +576,13 @@ _VECTOR_END(MIPSX(xtlb_miss)) */ VECTOR(MIPSX(cache), unknown) PTR_LA k0, _C_LABEL(MIPSX(cache_exception)) #00 - li k1, MIPS_PHYS_MASK #02 - and k0, k1 #03 - li k1, MIPS_KSEG1_START #04 - or k0, k1 #05 - lui k1, %hi(CPUVAR(CURLWP)) #06: k1=hi of curlwp - jr k0 #07 - PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #08: k1=lo of curlwp + li k1, MIPS_PHYS_MASK #01 + and k0, k1 #02 + li k1, MIPS_KSEG1_START #03 + or k0, k1 #04 + lui k1, %hi(CPUVAR(CURLWP)) #05: k1=hi of curlwp + jr k0 #06 + PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #07: k1=lo of curlwp _VECTOR_END(MIPSX(cache)) /* @@ -647,13 +647,13 @@ VECTOR(MIPSX(intr), unknown) MFC0_HAZARD #01: stall and k1, k1, MIPS3_SR_KSU_USER #02: test for user mode PTR_LA k0, MIPSX(user_intr) #03: assume user mode - bnez k1, 1f #05: yep, do it - nop #06: branch deay - PTR_LA k0, MIPSX(kern_intr) #07: nope, kernel intr + bnez k1, 1f #04: yep, do it + nop #05: branch deay + PTR_LA k0, MIPSX(kern_intr) #06: nope, kernel intr 1: - lui k1, %hi(CPUVAR(CURLWP)) #09: k1=hi of curlwp - jr k0 #0a: jump to the function - PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #0b: k1=lo of curlwp + lui k1, %hi(CPUVAR(CURLWP)) #07: k1=hi of curlwp + jr k0 #08: jump to the function + PTR_L k1, %lo(CPUVAR(CURLWP))(k1) #09: k1=lo of curlwp .set at _VECTOR_END(MIPSX(intr))