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Oooops. Back out some of previous my commit.

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This commit is contained in:
msaitoh 2009-04-19 11:17:46 +00:00
parent 4d9e9f6912
commit 2449d3efc1
4 changed files with 8 additions and 33 deletions
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6
sys/dev/mii/files.mii
View File

@ -1,4 +1,4 @@
# $NetBSD: files.mii,v 1.43 2009/04/19 11:10:36 msaitoh Exp $
# $NetBSD: files.mii,v 1.44 2009/04/19 11:17:46 msaitoh Exp $
defflag opt_mii.h MIIVERBOSE
@ -24,10 +24,6 @@ device amhphy: mii_phy
attach amhphy at mii
file dev/mii/amhphy.c amhphy
device bmphy: mii_phy
attach bmphy at mii
file dev/mii/bmphy.c bmphy
device bmtphy: mii_phy
attach bmtphy at mii
file dev/mii/bmtphy.c bmtphy

20
sys/dev/mii/makphy.c
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@ -1,4 +1,4 @@
/* $NetBSD: makphy.c,v 1.30 2009/04/19 11:10:36 msaitoh Exp $ */
/* $NetBSD: makphy.c,v 1.31 2009/04/19 11:17:46 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.30 2009/04/19 11:10:36 msaitoh Exp $");
__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.31 2009/04/19 11:17:46 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -167,24 +167,10 @@ static void
makphy_reset(struct mii_softc *sc)
{
uint16_t pscr;
#if 0
uint16_t reg;
#endif
/* Assert CRS on transmit */
pscr = PHY_READ(sc, MII_MAKPHY_PSCR);
pscr |= PSCR_CRS_ON_TX;
#if 0
pscr &= ~PSCR_MDI_XOVER_MODE(XOVER_MODE_AUTO | XOVER_MODE_MDIX);
#endif
PHY_WRITE(sc, MII_MAKPHY_PSCR, pscr);
#if 0
reg = PHY_READ(sc, MII_MAKPHY_EPSC);
reg &= ~(EPSC_MASTER_DOWNSHIFT_MASK | EPSC_SLABE_DOWNSHIFT_MASK);
reg |= EPSC_MASTER_DOWNSHIFT_1X | EPSC_SLABE_DOWNSHIFT_1X;
reg |= EPSC_TX_CLK_25;
PHY_WRITE(sc, MII_MAKPHY_EPSC, reg);
#endif
PHY_WRITE(sc, MII_MAKPHY_PSCR, pscr | PSCR_CRS_ON_TX);
mii_phy_reset(sc);
}

12
sys/dev/mii/makphyreg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: makphyreg.h,v 1.4 2009/04/19 11:10:36 msaitoh Exp $ */
/* $NetBSD: makphyreg.h,v 1.5 2009/04/19 11:17:46 msaitoh Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -88,14 +88,8 @@
#define MII_MAKPHY_EPSC 0x14 /* extended PHY specific control */
#define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */
#define EPSC_TX_CLK_2_5 0x0060
#define EPSC_TX_CLK_25 0x0070
#define EPSC_TX_CLK_0 0x0000
#define EPSC_MASTER_DOWNSHIFT_MASK 0x0c00
#define EPSC_MASTER_DOWNSHIFT_1X 0x0000
#define EPSC_SLABE_DOWNSHIFT_MASK 0x0300
#define EPSC_SLABE_DOWNSHIFT_1X 0x0100
#define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */
#define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */
#define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */
#define MII_MAKPHY_REC 0x15 /* receive error counter */

3
sys/dev/mii/miidevs
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@ -1,4 +1,4 @@
$NetBSD: miidevs,v 1.86 2009/04/19 11:10:36 msaitoh Exp $
$NetBSD: miidevs,v 1.87 2009/04/19 11:17:46 msaitoh Exp $
/*-
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@ -199,7 +199,6 @@ model yyINTEL I82562ET 0x0033 i82562ET 10/100 media interface
model yyINTEL I82553 0x0035 i82553 10/100 media interface
model yyINTEL I82566 0x0039 i82566 10/100/1000 media interface
model xxMARVELL I82563 0x000a i82563 10/100/1000 media interface
model xxMARVELL I82567 0x000b i82567 10/100/1000 media interface
model yyINTEL IGP01E1000 0x0038 Intel IGP01E1000 Gigabit PHY