Add R10000 cache ops, written by KIYOHARA Takashi and posted on port-sgimips.
Enabled by options ENABLE_MIPS4_CACHE_R10K for now.
This commit is contained in:
tsutsui
parent
5238256a02
commit
14658b124b
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@ -1,4 +1,4 @@
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# $NetBSD: files.mips,v 1.46 2003/03/08 04:43:25 rafal Exp $
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# $NetBSD: files.mips,v 1.47 2003/10/05 11:10:25 tsutsui Exp $
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#
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defflag opt_cputype.h NOFPU
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@ -13,6 +13,7 @@ defflag opt_cputype.h NOFPU
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# ENABLE_MIPS_R3NKK
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defflag opt_mips_cache.h MIPS3_L2CACHE_ABSENT
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MIPS3_NO_PV_UNCACHED
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ENABLE_MIPS4_CACHE_R10K
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file arch/mips/mips/locore_mips1.S mips1
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file arch/mips/mips/locore_mips3.S mips3 | mips4 | mips32 | mips64
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@ -47,6 +48,7 @@ file arch/mips/mips/cache_r4k.c mips3 | mips4
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file arch/mips/mips/cache_r5k.c mips3 | mips4
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file arch/mips/mips/cache_r5k_subr.S mips3 | mips4
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file arch/mips/mips/cache_r5900.c mips3 & mips3_5900
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file arch/mips/mips/cache_r10k.c (mips3|mips4) & enable_mips4_cache_r10k
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file arch/mips/mips/cache_mipsNN.c mips32 | mips64
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file arch/mips/mips/in_cksum.c inet
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@ -0,0 +1,162 @@
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/* $NetBSD: cache_r10k.h,v 1.1 2003/10/05 11:10:25 tsutsui Exp $ */
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/*
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* Copyright (c) 2003 KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Cache definitions/operations for R10000-style caches.
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*/
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#define CACHEOP_R10K_CBARRIER (5 << 2) /* I */
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#define CACHEOP_R10K_IDX_LOAD_DATA (6 << 2) /* I, D, SD */
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#define CACHEOP_R10K_IDX_STORE_DATA (7 << 2) /* SI, SD */
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* cache_r10k_op_8lines_64:
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*
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* Perform the specified cache operation on 8 64-byte cache lines.
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*/
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#define cache_r10k_op_8lines_64(va, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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"cache %1, 0x000(%0); cache %1, 0x040(%0) \n\t" \
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"cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n\t" \
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"cache %1, 0x100(%0); cache %1, 0x140(%0) \n\t" \
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"cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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/*
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* cache_r10k_op_32lines_64:
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*
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* Perform the specified cache operation on 32 64-byte
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* cache lines.
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*/
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#define cache_r10k_op_32lines_64(va, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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"cache %1, 0x000(%0); cache %1, 0x040(%0); \n\t" \
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"cache %1, 0x080(%0); cache %1, 0x0c0(%0); \n\t" \
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"cache %1, 0x100(%0); cache %1, 0x140(%0); \n\t" \
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"cache %1, 0x180(%0); cache %1, 0x1c0(%0); \n\t" \
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"cache %1, 0x200(%0); cache %1, 0x240(%0); \n\t" \
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"cache %1, 0x280(%0); cache %1, 0x2c0(%0); \n\t" \
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"cache %1, 0x300(%0); cache %1, 0x340(%0); \n\t" \
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"cache %1, 0x380(%0); cache %1, 0x3c0(%0); \n\t" \
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"cache %1, 0x400(%0); cache %1, 0x440(%0); \n\t" \
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"cache %1, 0x480(%0); cache %1, 0x4c0(%0); \n\t" \
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"cache %1, 0x500(%0); cache %1, 0x540(%0); \n\t" \
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"cache %1, 0x580(%0); cache %1, 0x5c0(%0); \n\t" \
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"cache %1, 0x600(%0); cache %1, 0x640(%0); \n\t" \
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"cache %1, 0x680(%0); cache %1, 0x6c0(%0); \n\t" \
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"cache %1, 0x700(%0); cache %1, 0x740(%0); \n\t" \
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"cache %1, 0x780(%0); cache %1, 0x7c0(%0); \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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/*
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* cache_r10k_op_16lines_32_2way:
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*
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* Perform the specified cache operation on 16 64-byte
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* cache lines, 2-ways.
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*/
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#define cache_r10k_op_16lines_64_2way(va1, va2, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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"cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
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"cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
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"cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
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"cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
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"cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \
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"cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \
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"cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \
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"cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \
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"cache %2, 0x200(%0); cache %2, 0x200(%1); \n\t" \
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"cache %2, 0x240(%0); cache %2, 0x240(%1); \n\t" \
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"cache %2, 0x280(%0); cache %2, 0x280(%1); \n\t" \
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"cache %2, 0x2c0(%0); cache %2, 0x2c0(%1); \n\t" \
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"cache %2, 0x300(%0); cache %2, 0x300(%1); \n\t" \
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"cache %2, 0x340(%0); cache %2, 0x340(%1); \n\t" \
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"cache %2, 0x380(%0); cache %2, 0x380(%1); \n\t" \
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"cache %2, 0x3c0(%0); cache %2, 0x3c0(%1); \n\t" \
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".set reorder" \
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: \
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: "r" (va1), "r" (va2), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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void r10k_icache_sync_all_64(void);
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void r10k_icache_sync_range_64(vaddr_t, vsize_t);
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void r10k_icache_sync_range_index_64(vaddr_t, vsize_t);
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void r10k_pdcache_wb_range(vaddr_t, vsize_t);
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#endif /* _KERNEL && !_LOCORE */
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@ -1,4 +1,4 @@
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/* $NetBSD: cache.c,v 1.20 2003/07/15 02:43:36 lukem Exp $ */
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/* $NetBSD: cache.c,v 1.21 2003/10/05 11:10:25 tsutsui Exp $ */
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/*
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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@ -68,9 +68,10 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.20 2003/07/15 02:43:36 lukem Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.21 2003/10/05 11:10:25 tsutsui Exp $");
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#include "opt_cputype.h"
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#include "opt_mips_cache.h"
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#include <sys/param.h>
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@ -86,6 +87,9 @@ __KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.20 2003/07/15 02:43:36 lukem Exp $");
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#ifdef MIPS3_PLUS
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#include <mips/cache_r4k.h>
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#include <mips/cache_r5k.h>
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#ifdef ENABLE_MIPS4_CACHE_R10K
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#include <mips/cache_r10k.h>
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#endif
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#endif
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#if defined(MIPS32) || defined(MIPS64)
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@ -164,6 +168,9 @@ void tx39_cache_config_write_through(void);
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#include <mips/cache_r5900.h>
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#endif /* MIPS3_5900 */
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void mips3_get_cache_config(int);
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#ifdef ENABLE_MIPS4_CACHE_R10K
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void mips4_get_cache_config(int);
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#endif /* ENABLE_MIPS4_CACHE_R10K */
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#endif /* MIPS3 || MIPS4 */
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#if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
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@ -600,6 +607,49 @@ primary_cache_is_2way:
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r5900_pdcache_wb_range_64;
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break;
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#endif /* MIPS3_5900 */
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#ifdef ENABLE_MIPS4_CACHE_R10K
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case MIPS_R10000:
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/* cache spec */
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mips_picache_ways = 2;
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mips_pdcache_ways = 2;
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mips_sdcache_ways = 2;
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mips4_get_cache_config(csizebase);
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switch (mips_picache_line_size) {
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case 64: /* 64 Byte */
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mips_cache_ops.mco_icache_sync_all =
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r10k_icache_sync_all_64;
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mips_cache_ops.mco_icache_sync_range =
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r10k_icache_sync_range_64;
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mips_cache_ops.mco_icache_sync_range_index =
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r10k_icache_sync_range_index_64;
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break;
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default:
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panic("r10k picache line size %d",
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mips_picache_line_size);
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}
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switch (mips_pdcache_line_size) {
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case 32: /* 32 Byte */
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mips_cache_ops.mco_pdcache_wbinv_all =
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r5k_pdcache_wbinv_all_32;
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mips_cache_ops.mco_pdcache_wbinv_range =
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r5k_pdcache_wbinv_range_32;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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r5k_pdcache_wbinv_range_index_32;
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mips_cache_ops.mco_pdcache_inv_range =
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r5k_pdcache_inv_range_32;
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mips_cache_ops.mco_pdcache_wb_range =
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r10k_pdcache_wb_range;
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break;
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default:
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panic("r10k pdcache line size %d",
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mips_pdcache_line_size);
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}
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break;
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#endif /* ENABLE_MIPS4_CACHE_R10K */
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#endif /* MIPS3 || MIPS4 */
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default:
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@ -716,6 +766,49 @@ primary_cache_is_2way:
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mips_cache_ops.mco_sdcache_wb_range =
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r5k_sdcache_wb_range;
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break;
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#ifdef ENABLE_MIPS4_CACHE_R10K
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case MIPS_R10000:
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switch (mips_sdcache_ways) {
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case 2:
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switch (mips_sdcache_line_size) {
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case 64:
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mips_cache_ops.mco_sdcache_wbinv_all =
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r4k_sdcache_wbinv_all_generic;
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mips_cache_ops.mco_sdcache_wbinv_range =
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r4k_sdcache_wbinv_range_generic;
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mips_cache_ops.mco_sdcache_wbinv_range_index =
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r4k_sdcache_wbinv_range_index_generic;
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mips_cache_ops.mco_sdcache_inv_range =
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r4k_sdcache_inv_range_generic;
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mips_cache_ops.mco_sdcache_wb_range =
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r4k_sdcache_wb_range_generic;
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break;
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case 128:
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mips_cache_ops.mco_sdcache_wbinv_all =
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r4k_sdcache_wbinv_all_128;
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mips_cache_ops.mco_sdcache_wbinv_range =
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r4k_sdcache_wbinv_range_128;
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mips_cache_ops.mco_sdcache_wbinv_range_index =
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r4k_sdcache_wbinv_range_index_128;
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mips_cache_ops.mco_sdcache_inv_range =
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r4k_sdcache_inv_range_128;
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mips_cache_ops.mco_sdcache_wb_range =
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r4k_sdcache_wb_range_128;
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break;
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default:
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panic("r10k sdcache %d way line size %d",
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mips_sdcache_ways, mips_sdcache_line_size);
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}
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break;
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default:
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panic("r10k sdcache %d way line size %d",
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mips_sdcache_ways, mips_sdcache_line_size);
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}
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break;
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#endif /* ENABLE_MIPS4_CACHE_R10K */
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#endif /* MIPS3 || MIPS4 */
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default:
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@ -858,6 +951,27 @@ mips3_get_cache_config(int csizebase)
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}
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}
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}
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#ifdef ENABLE_MIPS4_CACHE_R10K
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void
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mips4_get_cache_config(int csizebase)
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{
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uint32_t config = mips3_cp0_config_read();
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mips_picache_size = MIPS4_CONFIG_CACHE_SIZE(config,
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MIPS4_CONFIG_IC_MASK, csizebase, MIPS4_CONFIG_IC_SHIFT);
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mips_picache_line_size = 64; /* 64 Byte */
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mips_pdcache_size = MIPS4_CONFIG_CACHE_SIZE(config,
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MIPS4_CONFIG_DC_MASK, csizebase, MIPS4_CONFIG_DC_SHIFT);
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mips_pdcache_line_size = 32; /* 32 Byte */
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mips_cache_alias_mask =
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((mips_pdcache_size / mips_pdcache_ways) - 1) & ~(PAGE_SIZE - 1);
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mips_cache_prefer_mask =
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max(mips_pdcache_size, mips_picache_size) - 1;
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}
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#endif /* ENABLE_MIPS4_CACHE_R10K */
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#endif /* MIPS3 || MIPS4 */
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#endif /* MIPS1 || MIPS3 || MIPS4 */
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@ -0,0 +1,175 @@
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/* $NetBSD: cache_r10k.c,v 1.1 2003/10/05 11:10:25 tsutsui Exp $ */
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/*
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* Copyright (c) 2003 KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright 2001 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
|
||||
#include <sys/param.h>
|
||||
|
||||
#include <mips/cache.h>
|
||||
#include <mips/cache_r4k.h>
|
||||
#include <mips/cache_r5k.h>
|
||||
#include <mips/cache_r10k.h>
|
||||
#include <mips/locore.h>
|
||||
|
||||
/*
|
||||
* Cache operations for R10000-style caches:
|
||||
*
|
||||
* - 2-way set-associative
|
||||
* - Write-back
|
||||
* - Virtually indexed, physically tagged
|
||||
*
|
||||
*/
|
||||
|
||||
#define round_line(x) (((x) + 63) & ~63)
|
||||
#define trunc_line(x) ((x) & ~63)
|
||||
|
||||
__asm(".set mips3");
|
||||
|
||||
void
|
||||
r10k_icache_sync_all_64(void)
|
||||
{
|
||||
vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
|
||||
vaddr_t eva = va + mips_picache_size;
|
||||
|
||||
/*
|
||||
* Since we're hitting the whole thing, we don't have to
|
||||
* worry about the 2 different "ways".
|
||||
*/
|
||||
|
||||
mips_dcache_wbinv_all();
|
||||
|
||||
__asm __volatile("sync");
|
||||
|
||||
while (va < eva) {
|
||||
cache_r10k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
||||
va += (32 * 64);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
r10k_icache_sync_range_64(vaddr_t va, vsize_t size)
|
||||
{
|
||||
vaddr_t eva = round_line(va + size);
|
||||
|
||||
va = trunc_line(va);
|
||||
|
||||
mips_dcache_wb_range(va, (eva - va));
|
||||
|
||||
__asm __volatile("sync");
|
||||
|
||||
while ((eva - va) >= (32 * 64)) {
|
||||
cache_r10k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
|
||||
va += (32 * 64);
|
||||
}
|
||||
|
||||
while (va < eva) {
|
||||
cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
|
||||
va += 64;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
r10k_icache_sync_range_index_64(vaddr_t va, vsize_t size)
|
||||
{
|
||||
vaddr_t w2va, eva, orig_va;
|
||||
|
||||
orig_va = va;
|
||||
|
||||
eva = round_line(va + size);
|
||||
va = trunc_line(va);
|
||||
|
||||
mips_dcache_wbinv_range_index(va, (eva - va));
|
||||
|
||||
__asm __volatile("sync");
|
||||
|
||||
/*
|
||||
* Since we're doing Index ops, we expect to not be able
|
||||
* to access the address we've been given. So, get the
|
||||
* bits that determine the cache index, and make a KSEG0
|
||||
* address out of them.
|
||||
*/
|
||||
va = MIPS_PHYS_TO_KSEG0(orig_va & mips_picache_way_mask);
|
||||
|
||||
eva = round_line(va + size);
|
||||
va = trunc_line(va);
|
||||
w2va = va + mips_picache_way_size;
|
||||
|
||||
while ((eva - va) >= (16 * 64)) {
|
||||
cache_r10k_op_16lines_64_2way(va, w2va,
|
||||
CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
||||
va += (16 * 64);
|
||||
w2va += (16 * 64);
|
||||
}
|
||||
|
||||
while (va < eva) {
|
||||
cache_op_r4k_line( va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
||||
cache_op_r4k_line(w2va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
|
||||
va += 64;
|
||||
w2va += 64;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
r10k_pdcache_wb_range(vaddr_t va, vsize_t size)
|
||||
{
|
||||
/* R10000 processor does not support */
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue