diff --git a/sys/arch/mips/conf/files.mips b/sys/arch/mips/conf/files.mips index 9c3e247ae95e..e519909eb3e2 100644 --- a/sys/arch/mips/conf/files.mips +++ b/sys/arch/mips/conf/files.mips @@ -1,4 +1,4 @@ -# $NetBSD: files.mips,v 1.46 2003/03/08 04:43:25 rafal Exp $ +# $NetBSD: files.mips,v 1.47 2003/10/05 11:10:25 tsutsui Exp $ # defflag opt_cputype.h NOFPU @@ -13,6 +13,7 @@ defflag opt_cputype.h NOFPU # ENABLE_MIPS_R3NKK defflag opt_mips_cache.h MIPS3_L2CACHE_ABSENT MIPS3_NO_PV_UNCACHED + ENABLE_MIPS4_CACHE_R10K file arch/mips/mips/locore_mips1.S mips1 file arch/mips/mips/locore_mips3.S mips3 | mips4 | mips32 | mips64 @@ -47,6 +48,7 @@ file arch/mips/mips/cache_r4k.c mips3 | mips4 file arch/mips/mips/cache_r5k.c mips3 | mips4 file arch/mips/mips/cache_r5k_subr.S mips3 | mips4 file arch/mips/mips/cache_r5900.c mips3 & mips3_5900 +file arch/mips/mips/cache_r10k.c (mips3|mips4) & enable_mips4_cache_r10k file arch/mips/mips/cache_mipsNN.c mips32 | mips64 file arch/mips/mips/in_cksum.c inet diff --git a/sys/arch/mips/include/cache_r10k.h b/sys/arch/mips/include/cache_r10k.h new file mode 100644 index 000000000000..5f8c366c41cf --- /dev/null +++ b/sys/arch/mips/include/cache_r10k.h @@ -0,0 +1,162 @@ +/* $NetBSD: cache_r10k.h,v 1.1 2003/10/05 11:10:25 tsutsui Exp $ */ + +/* + * Copyright (c) 2003 KIYOHARA Takashi + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Cache definitions/operations for R10000-style caches. + */ + +#define CACHEOP_R10K_CBARRIER (5 << 2) /* I */ +#define CACHEOP_R10K_IDX_LOAD_DATA (6 << 2) /* I, D, SD */ +#define CACHEOP_R10K_IDX_STORE_DATA (7 << 2) /* SI, SD */ + +#if defined(_KERNEL) && !defined(_LOCORE) + +/* + * cache_r10k_op_8lines_64: + * + * Perform the specified cache operation on 8 64-byte cache lines. + */ +#define cache_r10k_op_8lines_64(va, op) \ +do { \ + __asm __volatile( \ + ".set noreorder \n\t" \ + "cache %1, 0x000(%0); cache %1, 0x040(%0) \n\t" \ + "cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n\t" \ + "cache %1, 0x100(%0); cache %1, 0x140(%0) \n\t" \ + "cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n\t" \ + ".set reorder" \ + : \ + : "r" (va), "i" (op) \ + : "memory"); \ +} while (/*CONSTCOND*/0) + +/* + * cache_r10k_op_32lines_64: + * + * Perform the specified cache operation on 32 64-byte + * cache lines. + */ +#define cache_r10k_op_32lines_64(va, op) \ +do { \ + __asm __volatile( \ + ".set noreorder \n\t" \ + "cache %1, 0x000(%0); cache %1, 0x040(%0); \n\t" \ + "cache %1, 0x080(%0); cache %1, 0x0c0(%0); \n\t" \ + "cache %1, 0x100(%0); cache %1, 0x140(%0); \n\t" \ + "cache %1, 0x180(%0); cache %1, 0x1c0(%0); \n\t" \ + "cache %1, 0x200(%0); cache %1, 0x240(%0); \n\t" \ + "cache %1, 0x280(%0); cache %1, 0x2c0(%0); \n\t" \ + "cache %1, 0x300(%0); cache %1, 0x340(%0); \n\t" \ + "cache %1, 0x380(%0); cache %1, 0x3c0(%0); \n\t" \ + "cache %1, 0x400(%0); cache %1, 0x440(%0); \n\t" \ + "cache %1, 0x480(%0); cache %1, 0x4c0(%0); \n\t" \ + "cache %1, 0x500(%0); cache %1, 0x540(%0); \n\t" \ + "cache %1, 0x580(%0); cache %1, 0x5c0(%0); \n\t" \ + "cache %1, 0x600(%0); cache %1, 0x640(%0); \n\t" \ + "cache %1, 0x680(%0); cache %1, 0x6c0(%0); \n\t" \ + "cache %1, 0x700(%0); cache %1, 0x740(%0); \n\t" \ + "cache %1, 0x780(%0); cache %1, 0x7c0(%0); \n\t" \ + ".set reorder" \ + : \ + : "r" (va), "i" (op) \ + : "memory"); \ +} while (/*CONSTCOND*/0) + +/* + * cache_r10k_op_16lines_32_2way: + * + * Perform the specified cache operation on 16 64-byte + * cache lines, 2-ways. + */ +#define cache_r10k_op_16lines_64_2way(va1, va2, op) \ +do { \ + __asm __volatile( \ + ".set noreorder \n\t" \ + "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \ + "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \ + "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \ + "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \ + "cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \ + "cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \ + "cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \ + "cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \ + "cache %2, 0x200(%0); cache %2, 0x200(%1); \n\t" \ + "cache %2, 0x240(%0); cache %2, 0x240(%1); \n\t" \ + "cache %2, 0x280(%0); cache %2, 0x280(%1); \n\t" \ + "cache %2, 0x2c0(%0); cache %2, 0x2c0(%1); \n\t" \ + "cache %2, 0x300(%0); cache %2, 0x300(%1); \n\t" \ + "cache %2, 0x340(%0); cache %2, 0x340(%1); \n\t" \ + "cache %2, 0x380(%0); cache %2, 0x380(%1); \n\t" \ + "cache %2, 0x3c0(%0); cache %2, 0x3c0(%1); \n\t" \ + ".set reorder" \ + : \ + : "r" (va1), "r" (va2), "i" (op) \ + : "memory"); \ +} while (/*CONSTCOND*/0) + +void r10k_icache_sync_all_64(void); +void r10k_icache_sync_range_64(vaddr_t, vsize_t); +void r10k_icache_sync_range_index_64(vaddr_t, vsize_t); + +void r10k_pdcache_wb_range(vaddr_t, vsize_t); + +#endif /* _KERNEL && !_LOCORE */ + diff --git a/sys/arch/mips/mips/cache.c b/sys/arch/mips/mips/cache.c index 7ff5a5a90c83..7cbbf65b0cf2 100644 --- a/sys/arch/mips/mips/cache.c +++ b/sys/arch/mips/mips/cache.c @@ -1,4 +1,4 @@ -/* $NetBSD: cache.c,v 1.20 2003/07/15 02:43:36 lukem Exp $ */ +/* $NetBSD: cache.c,v 1.21 2003/10/05 11:10:25 tsutsui Exp $ */ /* * Copyright 2001, 2002 Wasabi Systems, Inc. @@ -68,9 +68,10 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.20 2003/07/15 02:43:36 lukem Exp $"); +__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.21 2003/10/05 11:10:25 tsutsui Exp $"); #include "opt_cputype.h" +#include "opt_mips_cache.h" #include @@ -86,6 +87,9 @@ __KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.20 2003/07/15 02:43:36 lukem Exp $"); #ifdef MIPS3_PLUS #include #include +#ifdef ENABLE_MIPS4_CACHE_R10K +#include +#endif #endif #if defined(MIPS32) || defined(MIPS64) @@ -164,6 +168,9 @@ void tx39_cache_config_write_through(void); #include #endif /* MIPS3_5900 */ void mips3_get_cache_config(int); +#ifdef ENABLE_MIPS4_CACHE_R10K +void mips4_get_cache_config(int); +#endif /* ENABLE_MIPS4_CACHE_R10K */ #endif /* MIPS3 || MIPS4 */ #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4) @@ -600,6 +607,49 @@ primary_cache_is_2way: r5900_pdcache_wb_range_64; break; #endif /* MIPS3_5900 */ +#ifdef ENABLE_MIPS4_CACHE_R10K + case MIPS_R10000: + /* cache spec */ + mips_picache_ways = 2; + mips_pdcache_ways = 2; + mips_sdcache_ways = 2; + + mips4_get_cache_config(csizebase); + + switch (mips_picache_line_size) { + case 64: /* 64 Byte */ + mips_cache_ops.mco_icache_sync_all = + r10k_icache_sync_all_64; + mips_cache_ops.mco_icache_sync_range = + r10k_icache_sync_range_64; + mips_cache_ops.mco_icache_sync_range_index = + r10k_icache_sync_range_index_64; + break; + + default: + panic("r10k picache line size %d", + mips_picache_line_size); + } + switch (mips_pdcache_line_size) { + case 32: /* 32 Byte */ + mips_cache_ops.mco_pdcache_wbinv_all = + r5k_pdcache_wbinv_all_32; + mips_cache_ops.mco_pdcache_wbinv_range = + r5k_pdcache_wbinv_range_32; + mips_cache_ops.mco_pdcache_wbinv_range_index = + r5k_pdcache_wbinv_range_index_32; + mips_cache_ops.mco_pdcache_inv_range = + r5k_pdcache_inv_range_32; + mips_cache_ops.mco_pdcache_wb_range = + r10k_pdcache_wb_range; + break; + + default: + panic("r10k pdcache line size %d", + mips_pdcache_line_size); + } + break; +#endif /* ENABLE_MIPS4_CACHE_R10K */ #endif /* MIPS3 || MIPS4 */ default: @@ -716,6 +766,49 @@ primary_cache_is_2way: mips_cache_ops.mco_sdcache_wb_range = r5k_sdcache_wb_range; break; +#ifdef ENABLE_MIPS4_CACHE_R10K + case MIPS_R10000: + switch (mips_sdcache_ways) { + case 2: + switch (mips_sdcache_line_size) { + case 64: + mips_cache_ops.mco_sdcache_wbinv_all = + r4k_sdcache_wbinv_all_generic; + mips_cache_ops.mco_sdcache_wbinv_range = + r4k_sdcache_wbinv_range_generic; + mips_cache_ops.mco_sdcache_wbinv_range_index = + r4k_sdcache_wbinv_range_index_generic; + mips_cache_ops.mco_sdcache_inv_range = + r4k_sdcache_inv_range_generic; + mips_cache_ops.mco_sdcache_wb_range = + r4k_sdcache_wb_range_generic; + break; + + case 128: + mips_cache_ops.mco_sdcache_wbinv_all = + r4k_sdcache_wbinv_all_128; + mips_cache_ops.mco_sdcache_wbinv_range = + r4k_sdcache_wbinv_range_128; + mips_cache_ops.mco_sdcache_wbinv_range_index = + r4k_sdcache_wbinv_range_index_128; + mips_cache_ops.mco_sdcache_inv_range = + r4k_sdcache_inv_range_128; + mips_cache_ops.mco_sdcache_wb_range = + r4k_sdcache_wb_range_128; + break; + + default: + panic("r10k sdcache %d way line size %d", + mips_sdcache_ways, mips_sdcache_line_size); + } + break; + + default: + panic("r10k sdcache %d way line size %d", + mips_sdcache_ways, mips_sdcache_line_size); + } + break; +#endif /* ENABLE_MIPS4_CACHE_R10K */ #endif /* MIPS3 || MIPS4 */ default: @@ -858,6 +951,27 @@ mips3_get_cache_config(int csizebase) } } } + +#ifdef ENABLE_MIPS4_CACHE_R10K +void +mips4_get_cache_config(int csizebase) +{ + uint32_t config = mips3_cp0_config_read(); + + mips_picache_size = MIPS4_CONFIG_CACHE_SIZE(config, + MIPS4_CONFIG_IC_MASK, csizebase, MIPS4_CONFIG_IC_SHIFT); + mips_picache_line_size = 64; /* 64 Byte */ + + mips_pdcache_size = MIPS4_CONFIG_CACHE_SIZE(config, + MIPS4_CONFIG_DC_MASK, csizebase, MIPS4_CONFIG_DC_SHIFT); + mips_pdcache_line_size = 32; /* 32 Byte */ + + mips_cache_alias_mask = + ((mips_pdcache_size / mips_pdcache_ways) - 1) & ~(PAGE_SIZE - 1); + mips_cache_prefer_mask = + max(mips_pdcache_size, mips_picache_size) - 1; +} +#endif /* ENABLE_MIPS4_CACHE_R10K */ #endif /* MIPS3 || MIPS4 */ #endif /* MIPS1 || MIPS3 || MIPS4 */ diff --git a/sys/arch/mips/mips/cache_r10k.c b/sys/arch/mips/mips/cache_r10k.c new file mode 100644 index 000000000000..d9f6c2e54a77 --- /dev/null +++ b/sys/arch/mips/mips/cache_r10k.c @@ -0,0 +1,175 @@ +/* $NetBSD: cache_r10k.c,v 1.1 2003/10/05 11:10:25 tsutsui Exp $ */ + +/* + * Copyright (c) 2003 KIYOHARA Takashi + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include + +#include +#include +#include +#include +#include + +/* + * Cache operations for R10000-style caches: + * + * - 2-way set-associative + * - Write-back + * - Virtually indexed, physically tagged + * + */ + +#define round_line(x) (((x) + 63) & ~63) +#define trunc_line(x) ((x) & ~63) + +__asm(".set mips3"); + +void +r10k_icache_sync_all_64(void) +{ + vaddr_t va = MIPS_PHYS_TO_KSEG0(0); + vaddr_t eva = va + mips_picache_size; + + /* + * Since we're hitting the whole thing, we don't have to + * worry about the 2 different "ways". + */ + + mips_dcache_wbinv_all(); + + __asm __volatile("sync"); + + while (va < eva) { + cache_r10k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV); + va += (32 * 64); + } +} + +void +r10k_icache_sync_range_64(vaddr_t va, vsize_t size) +{ + vaddr_t eva = round_line(va + size); + + va = trunc_line(va); + + mips_dcache_wb_range(va, (eva - va)); + + __asm __volatile("sync"); + + while ((eva - va) >= (32 * 64)) { + cache_r10k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV); + va += (32 * 64); + } + + while (va < eva) { + cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV); + va += 64; + } +} + +void +r10k_icache_sync_range_index_64(vaddr_t va, vsize_t size) +{ + vaddr_t w2va, eva, orig_va; + + orig_va = va; + + eva = round_line(va + size); + va = trunc_line(va); + + mips_dcache_wbinv_range_index(va, (eva - va)); + + __asm __volatile("sync"); + + /* + * Since we're doing Index ops, we expect to not be able + * to access the address we've been given. So, get the + * bits that determine the cache index, and make a KSEG0 + * address out of them. + */ + va = MIPS_PHYS_TO_KSEG0(orig_va & mips_picache_way_mask); + + eva = round_line(va + size); + va = trunc_line(va); + w2va = va + mips_picache_way_size; + + while ((eva - va) >= (16 * 64)) { + cache_r10k_op_16lines_64_2way(va, w2va, + CACHE_R4K_I|CACHEOP_R4K_INDEX_INV); + va += (16 * 64); + w2va += (16 * 64); + } + + while (va < eva) { + cache_op_r4k_line( va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV); + cache_op_r4k_line(w2va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV); + va += 64; + w2va += 64; + } +} + +void +r10k_pdcache_wb_range(vaddr_t va, vsize_t size) +{ + /* R10000 processor does not support */ +} +