Initial commit of iic and rtc devices.
This commit is contained in:
mark
parent
ab4a325e4c
commit
0b22968311
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@ -0,0 +1,403 @@
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/* $NetBSD: iic.c,v 1.1 1996/04/19 19:49:03 mark Exp $ */
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/*
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
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||||
* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* iic.c
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*
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* Routines to communicate with IIC devices
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*
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* Created : 13/10/94
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*
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* Based of kate/display/iiccontrol.c
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <machine/io.h>
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#include <machine/iomd.h>
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#include <machine/katelib.h>
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#include <machine/cpu.h>
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#include <machine/irqhandler.h>
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#include <machine/iic.h>
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#include <arm32/mainbus/mainbus.h>
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/* Local function prototypes */
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static int iic_getack __P((void));
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static void iic_write_bit __P((int bit));
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static int iic_write_byte __P((u_char value));
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static u_char iic_read_byte __P((void));
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static void iic_start_bit __P((void));
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static void iic_stop_bit __P((void));
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struct iic_softc {
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struct device sc_dev;
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int sc_flags;
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#define IIC_BROKEN 1
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#define IIC_OPEN 2
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#define IIC_BUSY 4
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};
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void iicattach __P((struct device *parent, struct device *self, void *aux));
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int iicmatch __P((struct device *parent, void *match, void *aux));
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/*
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* Main entry to IIC driver.
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*/
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int
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iic_control(address, buffer, count)
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u_char address;
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u_char *buffer;
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int count;
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{
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int loop;
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/* Send the start bit */
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iic_start_bit();
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/* Send the address */
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if (!iic_write_byte(address)) {
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iic_stop_bit();
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return(-1);
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}
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/* Read or write the data as required */
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if ((address & 1) == 0) {
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/* Write bytes */
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for (loop = 0; loop < count; ++loop) {
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if (!iic_write_byte(buffer[loop])) {
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iic_stop_bit();
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return(-1);
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}
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}
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}
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else {
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/* Read bytes */
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for (loop = 0; loop < count; ++loop) {
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buffer[loop] = iic_read_byte();
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/* Send final acknowledge */
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if (loop == (count - 1))
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iic_write_bit(1);
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else
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iic_write_bit(0);
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}
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}
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/* Send stop bit */
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iic_stop_bit();
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return(0);
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}
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static int
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iic_getack()
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{
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u_int oldirqstate;
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int ack;
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iic_set_state(1, 0);
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oldirqstate = disable_interrupts(I32_bit);
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iic_set_state_and_ack(1, 1);
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ack = ReadByte(IOMD_IOCR);
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iic_set_state(1, 0);
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restore_interrupts(oldirqstate);
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return((ack & 1) == 0);
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}
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static void
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iic_write_bit(bit)
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int bit;
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{
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u_int oldirqstate;
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iic_set_state(bit, 0);
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oldirqstate = disable_interrupts(I32_bit);
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iic_set_state_and_ack(bit, 1);
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iic_set_state(bit, 0);
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restore_interrupts(oldirqstate);
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}
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static int
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iic_write_byte(value)
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u_char value;
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{
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int loop;
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int bit;
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for (loop = 0x80; loop != 0; loop = loop >> 1) {
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bit = ((value & loop) != 0);
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iic_write_bit(bit);
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}
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return(iic_getack());
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}
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static u_char
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iic_read_byte()
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{
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int loop;
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u_char byte;
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u_int oldirqstate;
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iic_set_state(1,0);
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byte = 0;
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for (loop = 0; loop < 8; ++loop) {
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oldirqstate = disable_interrupts(I32_bit);
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iic_set_state_and_ack(1, 1);
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byte = (byte << 1) + (ReadByte(IOMD_IOCR) & 1);
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iic_set_state(1, 0);
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restore_interrupts(oldirqstate);
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}
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return(byte);
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}
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static void
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iic_start_bit()
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{
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iic_set_state(1, 1);
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iic_set_state(0, 1);
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iic_delay(10);
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iic_set_state(0, 0);
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}
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static void
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iic_stop_bit()
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{
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iic_set_state(0, 1);
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iic_set_state(1, 1);
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}
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struct cfattach iic_ca = {
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sizeof(struct iic_softc), iicmatch, iicattach
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};
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struct cfdriver iic_cd = {
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NULL, "iic", DV_DULL, 0
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};
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int
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iicmatch(parent, match, aux)
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struct device *parent;
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void *match;
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void *aux;
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{
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int id;
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/* Make sure we have an IOMD we understand */
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id = ReadByte(IOMD_ID0) | (ReadByte(IOMD_ID1) << 8);
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/* So far I only know about this IOMD */
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switch (id) {
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case RPC600_IOMD_ID:
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case RC7500_IOC_ID:
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return(1);
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break;
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default:
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printf("iic: Unknown IOMD id=%04x", id);
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break;
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}
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return(0);
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}
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int
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iicprint(aux, name)
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void *aux;
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char *name;
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{
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struct iicbus_attach_args *ib = aux;
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if (!name) {
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if (ib->ib_addr)
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printf(" addr 0x%02x", ib->ib_addr);
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}
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/* XXXX print flags */
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return (QUIET);
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}
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int
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iicsubmatch(parent, match, aux)
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struct device *parent;
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void *match;
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void *aux;
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{
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struct cfdata *cf = match;
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struct iicbus_attach_args *ib = aux;
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if (cf->cf_fstate == FSTATE_STAR)
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panic("eekkk, I'm stuffed");
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ib->ib_addr = cf->cf_loc[0];
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if (ib->ib_addr == -1)
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return(0);
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return((*cf->cf_attach->ca_match)(parent, match, aux));
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}
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void
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iicattach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct iicbus_attach_args iaa;
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printf("\n");
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while (config_found_sm(self, &iaa, iicprint, iicsubmatch));
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}
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int
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iicopen(dev, flag, mode, p)
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dev_t dev;
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int flag;
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int mode;
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struct proc *p;
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{
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struct iic_softc *sc;
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int unit = minor(dev);
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if (unit >= iic_cd.cd_ndevs)
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return(ENXIO);
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sc = iic_cd.cd_devs[unit];
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if (!sc) return(ENXIO);
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if (sc->sc_flags & IIC_OPEN) return(EBUSY);
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sc->sc_flags |= IIC_OPEN;
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return(0);
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}
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int
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iicclose(dev, flag, mode, p)
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dev_t dev;
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int flag;
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int mode;
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struct proc *p;
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{
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int unit = minor(dev);
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struct iic_softc *sc = iic_cd.cd_devs[unit];
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sc->sc_flags &= ~IIC_OPEN;
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return(0);
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}
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int
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iicread(dev, uio, flag)
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dev_t dev;
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struct uio *uio;
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int flag;
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{
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int unit = minor(dev);
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struct iic_softc *sc = iic_cd.cd_devs[unit];
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return(ENXIO);
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}
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int
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iicwrite(dev, uio, flag)
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dev_t dev;
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struct uio *uio;
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int flag;
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{
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int unit = minor(dev);
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struct iic_softc *sc = iic_cd.cd_devs[unit];
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return(ENXIO);
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}
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int
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iicioctl(dev, cmd, data, flag, p)
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dev_t dev;
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int cmd;
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caddr_t data;
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int flag;
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struct proc *p;
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{
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struct iic_softc *sc = iic_cd.cd_devs[minor(dev)];
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/*
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switch (cmd) {
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case IICIOC_CONTROL:
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if (iiccontrol() != 0) {
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return(EIO);
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}
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return(0);
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}
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*/
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return(EINVAL);
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}
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/* End of iic.c */
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@ -0,0 +1,384 @@
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/* $NetBSD: rtc.c,v 1.1 1996/04/19 19:49:06 mark Exp $ */
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/*
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
|
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*
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* This code is derived from software written for Brini by Mark Brinicombe
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RiscBSD kernel project
|
||||
*
|
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* rtc.c
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*
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* Routines to read and write the RTC and CMOS RAM
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*
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* Created : 13/10/94
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <machine/iic.h>
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#include <machine/rtc.h>
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struct rtc_softc {
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struct device sc_dev;
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int sc_flags;
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#define RTC_BROKEN 1
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#define RTC_OPEN 2
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};
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void rtcattach __P((struct device *parent, struct device *self, void *aux));
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int rtcmatch __P((struct device *parent, void *match, void *aux));
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/* Read a byte from CMOS RAM */
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int
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cmos_read(location)
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int location;
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{
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u_char buff;
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/*
|
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* This commented code dates from when I was translating CMOS address
|
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* from the RISCOS addresses. Now all addresses are specifed as
|
||||
* actual addresses in the CMOS RAM
|
||||
*/
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/*
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if (location > 0xF0)
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return(-1);
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if (location < 0xC0)
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buff = location + 0x40;
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else
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buff = location - 0xB0;
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*/
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buff = location;
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if (iic_control(RTC_Write, &buff, 1))
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return(-1);
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if (iic_control(RTC_Read, &buff, 1))
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return(-1);
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return(buff);
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}
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||||
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/* Write a byte to CMOS RAM */
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int
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cmos_write(location, value)
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int location;
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int value;
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{
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u_char buff[2];
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/*
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* This commented code dates from when I was translating CMOS address
|
||||
* from the RISCOS addresses. Now all addresses are specifed as
|
||||
* actual addresses in the CMOS RAM
|
||||
*/
|
||||
|
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/* if (location > 0xF0)
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return(-1);
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||||
|
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if (location < 0xC0)
|
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buff = location + 0x40;
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else
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buff = location - 0xB0;
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||||
*/
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buff[0] = location;
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buff[1] = value;
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||||
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if (iic_control(RTC_Write, buff, 2))
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return(-1);
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return(0);
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||||
}
|
||||
|
||||
|
||||
/* Hex to BCD and BCD to hex conversion routines */
|
||||
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||||
static inline int
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||||
hexdectodec(n)
|
||||
u_char n;
|
||||
{
|
||||
return(((n >> 4) & 0x0F) * 10 + (n & 0x0F));
|
||||
}
|
||||
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||||
static inline int
|
||||
dectohexdec(n)
|
||||
u_char n;
|
||||
{
|
||||
return(((n / 10) << 4) + (n % 10));
|
||||
}
|
||||
|
||||
|
||||
/* Write the RTC data from an 8 byte buffer */
|
||||
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||||
int
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||||
rtc_write(rtc)
|
||||
rtc_t *rtc;
|
||||
{
|
||||
u_char buff[8];
|
||||
|
||||
buff[0] = 1;
|
||||
|
||||
buff[1] = dectohexdec(rtc->rtc_centi);
|
||||
buff[2] = dectohexdec(rtc->rtc_sec);
|
||||
buff[3] = dectohexdec(rtc->rtc_min);
|
||||
buff[4] = dectohexdec(rtc->rtc_hour) & 0x3f;
|
||||
buff[5] = dectohexdec(rtc->rtc_day);
|
||||
buff[6] = dectohexdec(rtc->rtc_mon);
|
||||
|
||||
if (iic_control(RTC_Write, buff, 7))
|
||||
return(0);
|
||||
|
||||
cmos_write(RTC_ADDR_YEAR, rtc->rtc_year);
|
||||
cmos_write(RTC_ADDR_CENT, rtc->rtc_cen);
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
/* Read the RTC data into a 8 byte buffer */
|
||||
|
||||
int
|
||||
rtc_read(rtc)
|
||||
rtc_t *rtc;
|
||||
{
|
||||
u_char buff[8];
|
||||
int byte;
|
||||
|
||||
buff[0] = 0;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 1))
|
||||
return(0);
|
||||
|
||||
if (iic_control(RTC_Read, buff, 8))
|
||||
return(0);
|
||||
|
||||
rtc->rtc_micro = 0;
|
||||
rtc->rtc_centi = hexdectodec(buff[1] & 0xff);
|
||||
rtc->rtc_sec = hexdectodec(buff[2] & 0x7f);
|
||||
rtc->rtc_min = hexdectodec(buff[3] & 0x7f);
|
||||
rtc->rtc_hour = hexdectodec(buff[4] & 0x3f);
|
||||
|
||||
/* If in 12 hour mode need to look at the AM/PM flag */
|
||||
|
||||
if (buff[4] & 0x80)
|
||||
rtc->rtc_hour += (buff[4] & 0x40) ? 12 : 0;
|
||||
|
||||
rtc->rtc_day = hexdectodec(buff[5] & 0x3f);
|
||||
rtc->rtc_mon = hexdectodec(buff[6] & 0x1f);
|
||||
|
||||
byte = cmos_read(RTC_ADDR_YEAR);
|
||||
if (byte == -1)
|
||||
return(0);
|
||||
rtc->rtc_year = byte;
|
||||
|
||||
byte = cmos_read(RTC_ADDR_CENT);
|
||||
if (byte == -1)
|
||||
return(0);
|
||||
rtc->rtc_cen = byte;
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
struct cfattach rtc_ca = {
|
||||
sizeof(struct rtc_softc), rtcmatch, rtcattach
|
||||
};
|
||||
|
||||
struct cfdriver rtc_cd = {
|
||||
NULL, "rtc", DV_DULL, 0
|
||||
};
|
||||
|
||||
int
|
||||
rtcmatch(parent, match, aux)
|
||||
struct device *parent;
|
||||
void *match;
|
||||
void *aux;
|
||||
{
|
||||
/* struct iicbus_attach_args *ib = aux;*/
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
rtcattach(parent, self, aux)
|
||||
struct device *parent;
|
||||
struct device *self;
|
||||
void *aux;
|
||||
{
|
||||
struct rtc_softc *sc = (struct rtc_softc *)self;
|
||||
struct iicbus_attach_args *ib = aux;
|
||||
u_char buff[1];
|
||||
|
||||
sc->sc_flags |= RTC_BROKEN;
|
||||
if ((ib->ib_addr & IIC_PCF8583_MASK) == IIC_PCF8583_ADDR) {
|
||||
printf(": PCF8583");
|
||||
|
||||
buff[0] = 0;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 1))
|
||||
return;
|
||||
|
||||
if (iic_control(RTC_Read, buff, 1))
|
||||
return;
|
||||
|
||||
printf(" clock base ");
|
||||
switch (buff[0] & 0x30) {
|
||||
case 0x00:
|
||||
printf("32.768KHz");
|
||||
break;
|
||||
case 0x10:
|
||||
printf("50Hz");
|
||||
break;
|
||||
case 0x20:
|
||||
printf("event");
|
||||
break;
|
||||
case 0x30:
|
||||
printf("test mode");
|
||||
break;
|
||||
}
|
||||
|
||||
if (buff[0] & 0x80)
|
||||
printf(" stopped");
|
||||
if (buff[0] & 0x04)
|
||||
printf(" alarm enabled");
|
||||
sc->sc_flags &= ~RTC_BROKEN;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialise the time of day register.
|
||||
* This is normally left to the filing system to do but not all
|
||||
* filing systems call it e.g. cd9660
|
||||
*/
|
||||
|
||||
inittodr(0);
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcopen(dev, flag, mode, p)
|
||||
dev_t dev;
|
||||
int flag;
|
||||
int mode;
|
||||
struct proc *p;
|
||||
{
|
||||
struct rtc_softc *sc;
|
||||
int unit = minor(dev);
|
||||
|
||||
if (unit >= rtc_cd.cd_ndevs)
|
||||
return(ENXIO);
|
||||
|
||||
sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
if (!sc) return(ENXIO);
|
||||
|
||||
if (sc->sc_flags & RTC_OPEN) return(EBUSY);
|
||||
|
||||
sc->sc_flags |= RTC_OPEN;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcclose(dev, flag, mode, p)
|
||||
dev_t dev;
|
||||
int flag;
|
||||
int mode;
|
||||
struct proc *p;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
sc->sc_flags &= ~RTC_OPEN;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcread(dev, uio, flag)
|
||||
dev_t dev;
|
||||
struct uio *uio;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcwrite(dev, uio, flag)
|
||||
dev_t dev;
|
||||
struct uio *uio;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcioctl(dev, cmd, data, flag, p)
|
||||
dev_t dev;
|
||||
int cmd;
|
||||
caddr_t data;
|
||||
int flag;
|
||||
struct proc *p;
|
||||
{
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[minor(dev)];
|
||||
|
||||
/* switch (cmd) {
|
||||
case RTCIOC_READ:
|
||||
return(0);
|
||||
} */
|
||||
|
||||
return(EINVAL);
|
||||
}
|
||||
|
||||
/* End of rtc.c */
|
||||
|
|
@ -0,0 +1,403 @@
|
|||
/* $NetBSD: iic.c,v 1.1 1996/04/19 19:49:03 mark Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1996 Mark Brinicombe.
|
||||
* Copyright (c) 1994 Brini.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software written for Brini by Mark Brinicombe
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Mark Brinicombe.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RiscBSD kernel project
|
||||
*
|
||||
* iic.c
|
||||
*
|
||||
* Routines to communicate with IIC devices
|
||||
*
|
||||
* Created : 13/10/94
|
||||
*
|
||||
* Based of kate/display/iiccontrol.c
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/device.h>
|
||||
|
||||
#include <machine/io.h>
|
||||
#include <machine/iomd.h>
|
||||
#include <machine/katelib.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/irqhandler.h>
|
||||
#include <machine/iic.h>
|
||||
#include <arm32/mainbus/mainbus.h>
|
||||
|
||||
/* Local function prototypes */
|
||||
|
||||
static int iic_getack __P((void));
|
||||
static void iic_write_bit __P((int bit));
|
||||
static int iic_write_byte __P((u_char value));
|
||||
static u_char iic_read_byte __P((void));
|
||||
static void iic_start_bit __P((void));
|
||||
static void iic_stop_bit __P((void));
|
||||
|
||||
struct iic_softc {
|
||||
struct device sc_dev;
|
||||
int sc_flags;
|
||||
#define IIC_BROKEN 1
|
||||
#define IIC_OPEN 2
|
||||
#define IIC_BUSY 4
|
||||
};
|
||||
|
||||
void iicattach __P((struct device *parent, struct device *self, void *aux));
|
||||
int iicmatch __P((struct device *parent, void *match, void *aux));
|
||||
|
||||
/*
|
||||
* Main entry to IIC driver.
|
||||
*/
|
||||
|
||||
int
|
||||
iic_control(address, buffer, count)
|
||||
u_char address;
|
||||
u_char *buffer;
|
||||
int count;
|
||||
{
|
||||
int loop;
|
||||
|
||||
/* Send the start bit */
|
||||
|
||||
iic_start_bit();
|
||||
|
||||
/* Send the address */
|
||||
|
||||
if (!iic_write_byte(address)) {
|
||||
iic_stop_bit();
|
||||
return(-1);
|
||||
}
|
||||
|
||||
/* Read or write the data as required */
|
||||
|
||||
if ((address & 1) == 0) {
|
||||
/* Write bytes */
|
||||
for (loop = 0; loop < count; ++loop) {
|
||||
if (!iic_write_byte(buffer[loop])) {
|
||||
iic_stop_bit();
|
||||
return(-1);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* Read bytes */
|
||||
for (loop = 0; loop < count; ++loop) {
|
||||
buffer[loop] = iic_read_byte();
|
||||
|
||||
/* Send final acknowledge */
|
||||
|
||||
if (loop == (count - 1))
|
||||
iic_write_bit(1);
|
||||
else
|
||||
iic_write_bit(0);
|
||||
}
|
||||
}
|
||||
|
||||
/* Send stop bit */
|
||||
|
||||
iic_stop_bit();
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
iic_getack()
|
||||
{
|
||||
u_int oldirqstate;
|
||||
int ack;
|
||||
|
||||
iic_set_state(1, 0);
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
iic_set_state_and_ack(1, 1);
|
||||
ack = ReadByte(IOMD_IOCR);
|
||||
iic_set_state(1, 0);
|
||||
restore_interrupts(oldirqstate);
|
||||
|
||||
return((ack & 1) == 0);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
iic_write_bit(bit)
|
||||
int bit;
|
||||
{
|
||||
u_int oldirqstate;
|
||||
|
||||
iic_set_state(bit, 0);
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
iic_set_state_and_ack(bit, 1);
|
||||
iic_set_state(bit, 0);
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
iic_write_byte(value)
|
||||
u_char value;
|
||||
{
|
||||
int loop;
|
||||
int bit;
|
||||
|
||||
for (loop = 0x80; loop != 0; loop = loop >> 1) {
|
||||
bit = ((value & loop) != 0);
|
||||
iic_write_bit(bit);
|
||||
}
|
||||
|
||||
return(iic_getack());
|
||||
}
|
||||
|
||||
|
||||
static u_char
|
||||
iic_read_byte()
|
||||
{
|
||||
int loop;
|
||||
u_char byte;
|
||||
u_int oldirqstate;
|
||||
|
||||
iic_set_state(1,0);
|
||||
|
||||
byte = 0;
|
||||
|
||||
for (loop = 0; loop < 8; ++loop) {
|
||||
oldirqstate = disable_interrupts(I32_bit);
|
||||
iic_set_state_and_ack(1, 1);
|
||||
byte = (byte << 1) + (ReadByte(IOMD_IOCR) & 1);
|
||||
iic_set_state(1, 0);
|
||||
restore_interrupts(oldirqstate);
|
||||
}
|
||||
|
||||
return(byte);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
iic_start_bit()
|
||||
{
|
||||
iic_set_state(1, 1);
|
||||
iic_set_state(0, 1);
|
||||
iic_delay(10);
|
||||
iic_set_state(0, 0);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
iic_stop_bit()
|
||||
{
|
||||
iic_set_state(0, 1);
|
||||
iic_set_state(1, 1);
|
||||
}
|
||||
|
||||
|
||||
struct cfattach iic_ca = {
|
||||
sizeof(struct iic_softc), iicmatch, iicattach
|
||||
};
|
||||
|
||||
struct cfdriver iic_cd = {
|
||||
NULL, "iic", DV_DULL, 0
|
||||
};
|
||||
|
||||
int
|
||||
iicmatch(parent, match, aux)
|
||||
struct device *parent;
|
||||
void *match;
|
||||
void *aux;
|
||||
{
|
||||
int id;
|
||||
|
||||
/* Make sure we have an IOMD we understand */
|
||||
|
||||
id = ReadByte(IOMD_ID0) | (ReadByte(IOMD_ID1) << 8);
|
||||
|
||||
/* So far I only know about this IOMD */
|
||||
|
||||
switch (id) {
|
||||
case RPC600_IOMD_ID:
|
||||
case RC7500_IOC_ID:
|
||||
return(1);
|
||||
break;
|
||||
default:
|
||||
printf("iic: Unknown IOMD id=%04x", id);
|
||||
break;
|
||||
}
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int
|
||||
iicprint(aux, name)
|
||||
void *aux;
|
||||
char *name;
|
||||
{
|
||||
struct iicbus_attach_args *ib = aux;
|
||||
|
||||
if (!name) {
|
||||
if (ib->ib_addr)
|
||||
printf(" addr 0x%02x", ib->ib_addr);
|
||||
}
|
||||
|
||||
/* XXXX print flags */
|
||||
return (QUIET);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iicsubmatch(parent, match, aux)
|
||||
struct device *parent;
|
||||
void *match;
|
||||
void *aux;
|
||||
{
|
||||
struct cfdata *cf = match;
|
||||
struct iicbus_attach_args *ib = aux;
|
||||
|
||||
if (cf->cf_fstate == FSTATE_STAR)
|
||||
panic("eekkk, I'm stuffed");
|
||||
|
||||
ib->ib_addr = cf->cf_loc[0];
|
||||
|
||||
if (ib->ib_addr == -1)
|
||||
return(0);
|
||||
|
||||
return((*cf->cf_attach->ca_match)(parent, match, aux));
|
||||
}
|
||||
|
||||
void
|
||||
iicattach(parent, self, aux)
|
||||
struct device *parent;
|
||||
struct device *self;
|
||||
void *aux;
|
||||
{
|
||||
struct iicbus_attach_args iaa;
|
||||
|
||||
printf("\n");
|
||||
|
||||
while (config_found_sm(self, &iaa, iicprint, iicsubmatch));
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iicopen(dev, flag, mode, p)
|
||||
dev_t dev;
|
||||
int flag;
|
||||
int mode;
|
||||
struct proc *p;
|
||||
{
|
||||
struct iic_softc *sc;
|
||||
int unit = minor(dev);
|
||||
|
||||
if (unit >= iic_cd.cd_ndevs)
|
||||
return(ENXIO);
|
||||
|
||||
sc = iic_cd.cd_devs[unit];
|
||||
|
||||
if (!sc) return(ENXIO);
|
||||
|
||||
if (sc->sc_flags & IIC_OPEN) return(EBUSY);
|
||||
|
||||
sc->sc_flags |= IIC_OPEN;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iicclose(dev, flag, mode, p)
|
||||
dev_t dev;
|
||||
int flag;
|
||||
int mode;
|
||||
struct proc *p;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct iic_softc *sc = iic_cd.cd_devs[unit];
|
||||
|
||||
sc->sc_flags &= ~IIC_OPEN;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iicread(dev, uio, flag)
|
||||
dev_t dev;
|
||||
struct uio *uio;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct iic_softc *sc = iic_cd.cd_devs[unit];
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iicwrite(dev, uio, flag)
|
||||
dev_t dev;
|
||||
struct uio *uio;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct iic_softc *sc = iic_cd.cd_devs[unit];
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iicioctl(dev, cmd, data, flag, p)
|
||||
dev_t dev;
|
||||
int cmd;
|
||||
caddr_t data;
|
||||
int flag;
|
||||
struct proc *p;
|
||||
{
|
||||
struct iic_softc *sc = iic_cd.cd_devs[minor(dev)];
|
||||
|
||||
/*
|
||||
switch (cmd) {
|
||||
case IICIOC_CONTROL:
|
||||
if (iiccontrol() != 0) {
|
||||
return(EIO);
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
*/
|
||||
|
||||
return(EINVAL);
|
||||
}
|
||||
|
||||
/* End of iic.c */
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
/* $NetBSD: iic_asm.S,v 1.1 1996/04/19 19:49:04 mark Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1996 Mark Brinicombe.
|
||||
* Copyright (c) 1994 Brini.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software written for Brini by Mark Brinicombe
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Mark Brinicombe.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RiscBSD kernel project
|
||||
*
|
||||
* iic.s
|
||||
*
|
||||
* Low level routines to with IIC devices
|
||||
*
|
||||
* Created : 13/10/94
|
||||
*
|
||||
* Based of kate/display/iic.s
|
||||
*/
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/iomd.h>
|
||||
|
||||
#define IIC_BITDELAY 10
|
||||
|
||||
sp .req r13
|
||||
lr .req r14
|
||||
pc .req r15
|
||||
|
||||
.text
|
||||
|
||||
.global _iic_set_state
|
||||
|
||||
_iic_set_state:
|
||||
/*
|
||||
* Parameters
|
||||
* r0 - IIC data bit
|
||||
* r1 - IIC clock bit
|
||||
*/
|
||||
|
||||
/* Store temporary register */
|
||||
/* stmfd sp!, {r4}*/
|
||||
|
||||
/*
|
||||
* Mask the data and clock bits
|
||||
* Since these routines are only called from iiccontrol.c this is not
|
||||
* really needed
|
||||
*/
|
||||
and r0, r0, #0x00000001
|
||||
and r1, r1, #0x00000001
|
||||
|
||||
/* Get address of IOMD control register */
|
||||
|
||||
mov r2, #(IOMD_BASE)
|
||||
|
||||
/* Get the current CPSR */
|
||||
/* mrs r4, cpsr_all
|
||||
orr r3, r4, #(I32_bit | F32_bit)
|
||||
msr cpsr_all, r3
|
||||
*/
|
||||
|
||||
IRQdisable
|
||||
|
||||
/* Get current value of control register */
|
||||
|
||||
ldrb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
|
||||
|
||||
/* Preserve non-IIC bits */
|
||||
|
||||
bic r3, r3, #0x00000003
|
||||
orr r3, r3, #0x000000c0
|
||||
|
||||
/* Set the IIC clock and data bits */
|
||||
|
||||
orr r3, r3, r0
|
||||
orr r3, r3, r1, lsl #1
|
||||
|
||||
/* Store the new value of control register */
|
||||
|
||||
strb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
|
||||
|
||||
/* Restore CPSR state */
|
||||
/* msr cpsr_all, r4 */
|
||||
|
||||
IRQenable
|
||||
|
||||
/* Restore temporary register */
|
||||
/* ldmfd sp!, {r4} */
|
||||
|
||||
/* Pause a bit */
|
||||
|
||||
mov r0, #(IIC_BITDELAY)
|
||||
|
||||
/* Exit via iic_delay routine */
|
||||
b _iic_delay
|
||||
|
||||
|
||||
.global _iic_set_state_and_ack
|
||||
|
||||
_iic_set_state_and_ack:
|
||||
/*
|
||||
* Parameters
|
||||
* r0 - IIC data bit
|
||||
* r1 - IIC clock bit
|
||||
*/
|
||||
/* Store temporary register */
|
||||
/* stmfd sp!, {r4} */
|
||||
|
||||
/*
|
||||
* Mask the data and clock bits
|
||||
* Since these routines are only called from iiccontrol.c this is not
|
||||
* really needed
|
||||
*/
|
||||
|
||||
and r0, r0, #0x00000001
|
||||
and r1, r1, #0x00000001
|
||||
|
||||
/* Get address of IOMD control register */
|
||||
|
||||
mov r2, #(IOMD_BASE)
|
||||
|
||||
/* Get the current CPSR */
|
||||
/* mrs r4, cpsr_all
|
||||
orr r3, r4, #(I32_bit | F32_bit)
|
||||
msr cpsr_all, r3
|
||||
*/
|
||||
IRQdisable
|
||||
|
||||
/* Get current value of control register */
|
||||
|
||||
ldrb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
|
||||
|
||||
/* Preserve non-IIC bits */
|
||||
|
||||
bic r3, r3, #0x00000003
|
||||
orr r3, r3, #0x000000c0
|
||||
|
||||
/* Set the IIC clock and data bits */
|
||||
|
||||
orr r3, r3, r0
|
||||
orr r3, r3, r1, lsl #1
|
||||
|
||||
/* Store the new value of control register */
|
||||
|
||||
strb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
|
||||
|
||||
iic_set_state_and_ack_loop:
|
||||
ldrb r3, [r2, #(IOMD_IOCR - IOMD_BASE)]
|
||||
tst r3, #0x00000002
|
||||
beq iic_set_state_and_ack_loop
|
||||
|
||||
/* Restore CPSR state */
|
||||
/* msr cpsr_all, r4 */
|
||||
|
||||
IRQenable
|
||||
|
||||
/* Restore temporary register */
|
||||
/* ldmfd sp!, {r4} */
|
||||
|
||||
/* Pause a bit */
|
||||
|
||||
mov r0, #(IIC_BITDELAY)
|
||||
|
||||
/* Exit via iic_delay routine */
|
||||
b _iic_delay
|
||||
|
||||
|
||||
.global _iic_delay
|
||||
|
||||
_iic_delay:
|
||||
/*
|
||||
* Parameters
|
||||
* r0 - time to wait
|
||||
*/
|
||||
|
||||
/* Load address of IOMD */
|
||||
|
||||
mov r2, #(IOMD_BASE)
|
||||
|
||||
/* Latch current value of timer 1 */
|
||||
|
||||
strb r2, [r2, #(IOMD_T0LATCH - IOMD_BASE)]
|
||||
|
||||
/* Get the latched value */
|
||||
|
||||
ldrb r1, [r2, #(IOMD_T0LOW - IOMD_BASE)]
|
||||
|
||||
/* Loop until timer reaches end value */
|
||||
|
||||
iic_delay_loop:
|
||||
|
||||
/* Latch the current value of timer1 */
|
||||
|
||||
strb r2, [r2, #(IOMD_T0LATCH - IOMD_BASE)]
|
||||
|
||||
/* Get the latched value */
|
||||
|
||||
ldrb r3, [r2, #(IOMD_T0LOW - IOMD_BASE)]
|
||||
|
||||
/* Loop until timer reached expected value */
|
||||
|
||||
teq r3, r1
|
||||
movne r1, r3
|
||||
beq iic_delay_loop
|
||||
|
||||
subs r0, r0, #0x00000001
|
||||
bne iic_delay_loop
|
||||
|
||||
/* Exit */
|
||||
mov pc, lr
|
||||
|
||||
/* End of iic_asm.S */
|
||||
|
|
@ -0,0 +1,384 @@
|
|||
/* $NetBSD: rtc.c,v 1.1 1996/04/19 19:49:06 mark Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1996 Mark Brinicombe.
|
||||
* Copyright (c) 1994 Brini.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software written for Brini by Mark Brinicombe
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Brini.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RiscBSD kernel project
|
||||
*
|
||||
* rtc.c
|
||||
*
|
||||
* Routines to read and write the RTC and CMOS RAM
|
||||
*
|
||||
* Created : 13/10/94
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/device.h>
|
||||
#include <machine/iic.h>
|
||||
#include <machine/rtc.h>
|
||||
|
||||
struct rtc_softc {
|
||||
struct device sc_dev;
|
||||
int sc_flags;
|
||||
#define RTC_BROKEN 1
|
||||
#define RTC_OPEN 2
|
||||
};
|
||||
|
||||
void rtcattach __P((struct device *parent, struct device *self, void *aux));
|
||||
int rtcmatch __P((struct device *parent, void *match, void *aux));
|
||||
|
||||
/* Read a byte from CMOS RAM */
|
||||
|
||||
int
|
||||
cmos_read(location)
|
||||
int location;
|
||||
{
|
||||
u_char buff;
|
||||
|
||||
/*
|
||||
* This commented code dates from when I was translating CMOS address
|
||||
* from the RISCOS addresses. Now all addresses are specifed as
|
||||
* actual addresses in the CMOS RAM
|
||||
*/
|
||||
|
||||
/*
|
||||
if (location > 0xF0)
|
||||
return(-1);
|
||||
|
||||
if (location < 0xC0)
|
||||
buff = location + 0x40;
|
||||
else
|
||||
buff = location - 0xB0;
|
||||
*/
|
||||
buff = location;
|
||||
|
||||
if (iic_control(RTC_Write, &buff, 1))
|
||||
return(-1);
|
||||
if (iic_control(RTC_Read, &buff, 1))
|
||||
return(-1);
|
||||
|
||||
return(buff);
|
||||
}
|
||||
|
||||
|
||||
/* Write a byte to CMOS RAM */
|
||||
|
||||
int
|
||||
cmos_write(location, value)
|
||||
int location;
|
||||
int value;
|
||||
{
|
||||
u_char buff[2];
|
||||
|
||||
/*
|
||||
* This commented code dates from when I was translating CMOS address
|
||||
* from the RISCOS addresses. Now all addresses are specifed as
|
||||
* actual addresses in the CMOS RAM
|
||||
*/
|
||||
|
||||
/* if (location > 0xF0)
|
||||
return(-1);
|
||||
|
||||
if (location < 0xC0)
|
||||
buff = location + 0x40;
|
||||
else
|
||||
buff = location - 0xB0;
|
||||
*/
|
||||
buff[0] = location;
|
||||
buff[1] = value;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 2))
|
||||
return(-1);
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
/* Hex to BCD and BCD to hex conversion routines */
|
||||
|
||||
static inline int
|
||||
hexdectodec(n)
|
||||
u_char n;
|
||||
{
|
||||
return(((n >> 4) & 0x0F) * 10 + (n & 0x0F));
|
||||
}
|
||||
|
||||
static inline int
|
||||
dectohexdec(n)
|
||||
u_char n;
|
||||
{
|
||||
return(((n / 10) << 4) + (n % 10));
|
||||
}
|
||||
|
||||
|
||||
/* Write the RTC data from an 8 byte buffer */
|
||||
|
||||
int
|
||||
rtc_write(rtc)
|
||||
rtc_t *rtc;
|
||||
{
|
||||
u_char buff[8];
|
||||
|
||||
buff[0] = 1;
|
||||
|
||||
buff[1] = dectohexdec(rtc->rtc_centi);
|
||||
buff[2] = dectohexdec(rtc->rtc_sec);
|
||||
buff[3] = dectohexdec(rtc->rtc_min);
|
||||
buff[4] = dectohexdec(rtc->rtc_hour) & 0x3f;
|
||||
buff[5] = dectohexdec(rtc->rtc_day);
|
||||
buff[6] = dectohexdec(rtc->rtc_mon);
|
||||
|
||||
if (iic_control(RTC_Write, buff, 7))
|
||||
return(0);
|
||||
|
||||
cmos_write(RTC_ADDR_YEAR, rtc->rtc_year);
|
||||
cmos_write(RTC_ADDR_CENT, rtc->rtc_cen);
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
/* Read the RTC data into a 8 byte buffer */
|
||||
|
||||
int
|
||||
rtc_read(rtc)
|
||||
rtc_t *rtc;
|
||||
{
|
||||
u_char buff[8];
|
||||
int byte;
|
||||
|
||||
buff[0] = 0;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 1))
|
||||
return(0);
|
||||
|
||||
if (iic_control(RTC_Read, buff, 8))
|
||||
return(0);
|
||||
|
||||
rtc->rtc_micro = 0;
|
||||
rtc->rtc_centi = hexdectodec(buff[1] & 0xff);
|
||||
rtc->rtc_sec = hexdectodec(buff[2] & 0x7f);
|
||||
rtc->rtc_min = hexdectodec(buff[3] & 0x7f);
|
||||
rtc->rtc_hour = hexdectodec(buff[4] & 0x3f);
|
||||
|
||||
/* If in 12 hour mode need to look at the AM/PM flag */
|
||||
|
||||
if (buff[4] & 0x80)
|
||||
rtc->rtc_hour += (buff[4] & 0x40) ? 12 : 0;
|
||||
|
||||
rtc->rtc_day = hexdectodec(buff[5] & 0x3f);
|
||||
rtc->rtc_mon = hexdectodec(buff[6] & 0x1f);
|
||||
|
||||
byte = cmos_read(RTC_ADDR_YEAR);
|
||||
if (byte == -1)
|
||||
return(0);
|
||||
rtc->rtc_year = byte;
|
||||
|
||||
byte = cmos_read(RTC_ADDR_CENT);
|
||||
if (byte == -1)
|
||||
return(0);
|
||||
rtc->rtc_cen = byte;
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
struct cfattach rtc_ca = {
|
||||
sizeof(struct rtc_softc), rtcmatch, rtcattach
|
||||
};
|
||||
|
||||
struct cfdriver rtc_cd = {
|
||||
NULL, "rtc", DV_DULL, 0
|
||||
};
|
||||
|
||||
int
|
||||
rtcmatch(parent, match, aux)
|
||||
struct device *parent;
|
||||
void *match;
|
||||
void *aux;
|
||||
{
|
||||
/* struct iicbus_attach_args *ib = aux;*/
|
||||
|
||||
return(1);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
rtcattach(parent, self, aux)
|
||||
struct device *parent;
|
||||
struct device *self;
|
||||
void *aux;
|
||||
{
|
||||
struct rtc_softc *sc = (struct rtc_softc *)self;
|
||||
struct iicbus_attach_args *ib = aux;
|
||||
u_char buff[1];
|
||||
|
||||
sc->sc_flags |= RTC_BROKEN;
|
||||
if ((ib->ib_addr & IIC_PCF8583_MASK) == IIC_PCF8583_ADDR) {
|
||||
printf(": PCF8583");
|
||||
|
||||
buff[0] = 0;
|
||||
|
||||
if (iic_control(RTC_Write, buff, 1))
|
||||
return;
|
||||
|
||||
if (iic_control(RTC_Read, buff, 1))
|
||||
return;
|
||||
|
||||
printf(" clock base ");
|
||||
switch (buff[0] & 0x30) {
|
||||
case 0x00:
|
||||
printf("32.768KHz");
|
||||
break;
|
||||
case 0x10:
|
||||
printf("50Hz");
|
||||
break;
|
||||
case 0x20:
|
||||
printf("event");
|
||||
break;
|
||||
case 0x30:
|
||||
printf("test mode");
|
||||
break;
|
||||
}
|
||||
|
||||
if (buff[0] & 0x80)
|
||||
printf(" stopped");
|
||||
if (buff[0] & 0x04)
|
||||
printf(" alarm enabled");
|
||||
sc->sc_flags &= ~RTC_BROKEN;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialise the time of day register.
|
||||
* This is normally left to the filing system to do but not all
|
||||
* filing systems call it e.g. cd9660
|
||||
*/
|
||||
|
||||
inittodr(0);
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcopen(dev, flag, mode, p)
|
||||
dev_t dev;
|
||||
int flag;
|
||||
int mode;
|
||||
struct proc *p;
|
||||
{
|
||||
struct rtc_softc *sc;
|
||||
int unit = minor(dev);
|
||||
|
||||
if (unit >= rtc_cd.cd_ndevs)
|
||||
return(ENXIO);
|
||||
|
||||
sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
if (!sc) return(ENXIO);
|
||||
|
||||
if (sc->sc_flags & RTC_OPEN) return(EBUSY);
|
||||
|
||||
sc->sc_flags |= RTC_OPEN;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcclose(dev, flag, mode, p)
|
||||
dev_t dev;
|
||||
int flag;
|
||||
int mode;
|
||||
struct proc *p;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
sc->sc_flags &= ~RTC_OPEN;
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcread(dev, uio, flag)
|
||||
dev_t dev;
|
||||
struct uio *uio;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcwrite(dev, uio, flag)
|
||||
dev_t dev;
|
||||
struct uio *uio;
|
||||
int flag;
|
||||
{
|
||||
int unit = minor(dev);
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[unit];
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
rtcioctl(dev, cmd, data, flag, p)
|
||||
dev_t dev;
|
||||
int cmd;
|
||||
caddr_t data;
|
||||
int flag;
|
||||
struct proc *p;
|
||||
{
|
||||
struct rtc_softc *sc = rtc_cd.cd_devs[minor(dev)];
|
||||
|
||||
/* switch (cmd) {
|
||||
case RTCIOC_READ:
|
||||
return(0);
|
||||
} */
|
||||
|
||||
return(EINVAL);
|
||||
}
|
||||
|
||||
/* End of rtc.c */
|
||||
Loading…
Reference in New Issue