Display RDTSCP bit on AMD processors (Read Serialized TSC Pair).
ok by xtraeme
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/* $NetBSD: specialreg.h,v 1.17 2007/07/03 17:07:55 christos Exp $ */
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/* $NetBSD: specialreg.h,v 1.18 2007/07/11 11:56:36 njoly Exp $ */
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/*-
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* Copyright (c) 1991 The Regents of the University of California.
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#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
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#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
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#define CPUID_NOX 0x00100000 /* No Execute Page Protection */
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#define CPUID_NOX 0x00100000 /* No Execute Page Protection */
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#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
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#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
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#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
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#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
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#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
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#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
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#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
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#define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
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#define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
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"\24MPC\25NOX\26B21\27MMXX\30MMX"
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"\24MPC\25NOX\26B21\27MMXX\30MMX"
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#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34B27\35HTT\36LONG" \
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#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34RDTSCP\35HTT" \
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"\0373DNOW2\0403DNOW"
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"\36LONG\0373DNOW2\0403DNOW"
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/*
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/*
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* Centaur Extended Feature flags
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* Centaur Extended Feature flags
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