From 03ccc0759492c3cb2aabc9067d0ad71b4aaa76f7 Mon Sep 17 00:00:00 2001 From: njoly Date: Wed, 11 Jul 2007 11:56:36 +0000 Subject: [PATCH] Display RDTSCP bit on AMD processors (Read Serialized TSC Pair). ok by xtraeme --- sys/arch/x86/include/specialreg.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sys/arch/x86/include/specialreg.h b/sys/arch/x86/include/specialreg.h index f34e073cad1f..44ba3b870a7b 100644 --- a/sys/arch/x86/include/specialreg.h +++ b/sys/arch/x86/include/specialreg.h @@ -1,4 +1,4 @@ -/* $NetBSD: specialreg.h,v 1.17 2007/07/03 17:07:55 christos Exp $ */ +/* $NetBSD: specialreg.h,v 1.18 2007/07/11 11:56:36 njoly Exp $ */ /*- * Copyright (c) 1991 The Regents of the University of California. @@ -146,13 +146,14 @@ #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ #define CPUID_NOX 0x00100000 /* No Execute Page Protection */ #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ +#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */ #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ #define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \ "\24MPC\25NOX\26B21\27MMXX\30MMX" -#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34B27\35HTT\36LONG" \ - "\0373DNOW2\0403DNOW" +#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34RDTSCP\35HTT" \ + "\36LONG\0373DNOW2\0403DNOW" /* * Centaur Extended Feature flags