Added SH7751{,R} integrated PCI controller support.
This commit is contained in:
nonaka
parent
f4372b7c37
commit
02d0ebb277
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# $NetBSD: files.shpcic,v 1.1 2005/08/16 11:32:26 nonaka Exp $
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#
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# SH7751{,R} integrated PCI controller
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#
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device shpcic: pcibus
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attach shpcic at mainbus
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file arch/sh3/dev/shpcic.c sh4 & shpcic
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,187 @@
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/* $NetBSD: shpcicvar.h,v 1.5 2005/08/16 11:32:26 nonaka Exp $ */
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/*-
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* Copyright (c) 2005 NONAKA Kimihiro
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SH3_SHPCICVAR_H_
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#define _SH3_SHPCICVAR_H_
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#include <machine/bus.h>
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bus_space_tag_t shpcic_get_bus_io_tag(void);
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bus_space_tag_t shpcic_get_bus_mem_tag(void);
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bus_dma_tag_t shpcic_get_bus_dma_tag(void);
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int shpcic_bus_maxdevs(void *v, int busno);
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pcitag_t shpcic_make_tag(void *v, int bus, int device, int function);
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void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp);
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pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg);
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void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data);
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int shpcic_set_intr_priority(int intr, int level);
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void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg);
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void shpcic_intr_disestablish(void *ih);
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/*
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* shpcic io/mem bus space
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*/
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int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags,
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bus_space_handle_t *bshp);
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void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size);
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int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
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bus_size_t size, bus_space_handle_t *nbshp);
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int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
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bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
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bus_addr_t *bpap, bus_space_handle_t *bshp);
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void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size);
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/* read single */
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uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
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uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
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uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
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uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
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uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
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uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
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/* read multi */
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void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t *addr, bus_size_t count);
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void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t *addr, bus_size_t count);
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void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t *addr, bus_size_t count);
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void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t *addr, bus_size_t count);
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void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t *addr, bus_size_t count);
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void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t *addr, bus_size_t count);
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/* read region */
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void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t *addr, bus_size_t count);
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void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t *addr, bus_size_t count);
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void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t *addr, bus_size_t count);
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void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t *addr, bus_size_t count);
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void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t *addr, bus_size_t count);
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void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t *addr, bus_size_t count);
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/* write single */
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void shpcic_io_write_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t data);
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void shpcic_io_write_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t data);
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void shpcic_io_write_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t data);
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void shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t data);
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void shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t data);
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void shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t data);
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/* write multi */
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void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint8_t *addr, bus_size_t count);
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void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint16_t *addr, bus_size_t count);
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void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint32_t *addr, bus_size_t count);
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void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint8_t *addr, bus_size_t count);
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void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint16_t *addr, bus_size_t count);
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void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint32_t *addr, bus_size_t count);
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/* write region */
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void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint8_t *addr, bus_size_t count);
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void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint16_t *addr, bus_size_t count);
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void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint32_t *addr, bus_size_t count);
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void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint8_t *addr, bus_size_t count);
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void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint16_t *addr, bus_size_t count);
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void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, const uint32_t *addr, bus_size_t count);
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/* set multi */
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void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t val, bus_size_t count);
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void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t val, bus_size_t count);
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void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t val, bus_size_t count);
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void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t val, bus_size_t count);
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void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t val, bus_size_t count);
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void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t val, bus_size_t count);
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/* set region */
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void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t val, bus_size_t count);
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void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t val, bus_size_t count);
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void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t val, bus_size_t count);
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void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint8_t val, bus_size_t count);
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void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint16_t val, bus_size_t count);
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void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
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bus_size_t offset, uint32_t val, bus_size_t count);
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/* copy region */
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void shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1,
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bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
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bus_size_t count);
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void shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1,
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bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
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bus_size_t count);
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void shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1,
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bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
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bus_size_t count);
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void shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1,
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bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
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bus_size_t count);
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void shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1,
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bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
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bus_size_t count);
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void shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1,
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bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
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bus_size_t count);
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#endif /* _SH3_SHPCICVAR_H_ */
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@ -1,4 +1,4 @@
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/* $NetBSD: intcreg.h,v 1.8 2005/06/29 16:51:20 christos Exp $ */
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/* $NetBSD: intcreg.h,v 1.9 2005/08/16 11:32:26 nonaka Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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@ -104,10 +104,10 @@
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#define IPRB_REF_MASK 0x0f00
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#define IPRB_SCI_MASK 0x00f0
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#define INTPRI00_PCI0_MASK 0x0000000f
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#define INTPRI00_PCI1_MASK 0x000000f0
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#define INTPRI00_TMU3_MASK 0x00000f00
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#define INTPRI00_TMU4_MASK 0x0000f000
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#define INTPRI00_PCI0_MASK 0x0000000f
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#define INTPRI00_PCI1_MASK 0x000000f0
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#define INTPRI00_TMU3_MASK 0x00000f00
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#define INTPRI00_TMU4_MASK 0x0000f000
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/* INTREQ/INTMSK/INTMSKCLR */
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#define INTREQ00_PCISERR 0x00000001
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#define INTREQ00_TUNI3 0x00000100
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#define INTREQ00_TUNI4 0x00000200
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#define INTMSK00_MASK_ALL 0x000003ff
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#endif /* !_SH3_INTCREG_H_ */
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/* $NetBSD: intr.h,v 1.19 2003/11/04 03:13:48 uwe Exp $ */
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/* $NetBSD: intr.h,v 1.20 2005/08/16 11:32:26 nonaka Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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@ -86,6 +86,8 @@ void intc_intr_enable(int);
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void intc_intr_disable(int);
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void intc_intr(int, int, int);
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void intpri_intr_priority(int evtcode, int level);
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/*
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* software simulated interrupt
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*/
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@ -0,0 +1,145 @@
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/* $NetBSD: pcicreg.h,v 1.1 2005/08/16 11:32:26 nonaka Exp $ */
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/*-
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* Copyright (c) 2005 NONAKA Kimihiro
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SH3_PCICREG_H__
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#define _SH3_PCICREG_H__
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#include <sh3/devreg.h>
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/*
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* PCI Controller
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*/
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#define SH4_PCIC 0xfe200000
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#define SH4_PCIC_IO 0xfe240000
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#define SH4_PCIC_IO_SIZE 0x00040000
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#define SH4_PCIC_IO_MASK (SH4_PCIC_IO_SIZE-1)
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#define SH4_PCIC_MEM 0xfd000000
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#define SH4_PCIC_MEM_SIZE 0x01000000
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#define SH4_PCIC_MEM_MASK (SH4_PCIC_MEM_SIZE-1)
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#define SH4_PCICONF (SH4_PCIC+0x000) /* 32bit */
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#define SH4_PCICONF0 (SH4_PCICONF+0x00) /* 32bit */
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#define SH4_PCICONF1 (SH4_PCICONF+0x04) /* 32bit */
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#define SH4_PCICONF2 (SH4_PCICONF+0x08) /* 32bit */
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#define SH4_PCICONF3 (SH4_PCICONF+0x0c) /* 32bit */
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#define SH4_PCICONF4 (SH4_PCICONF+0x10) /* 32bit */
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#define SH4_PCICONF5 (SH4_PCICONF+0x14) /* 32bit */
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#define SH4_PCICONF6 (SH4_PCICONF+0x18) /* 32bit */
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#define SH4_PCICONF7 (SH4_PCICONF+0x1c) /* 32bit */
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#define SH4_PCICONF8 (SH4_PCICONF+0x20) /* 32bit */
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#define SH4_PCICONF9 (SH4_PCICONF+0x24) /* 32bit */
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#define SH4_PCICONF10 (SH4_PCICONF+0x28) /* 32bit */
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#define SH4_PCICONF11 (SH4_PCICONF+0x2c) /* 32bit */
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#define SH4_PCICONF12 (SH4_PCICONF+0x30) /* 32bit */
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#define SH4_PCICONF13 (SH4_PCICONF+0x34) /* 32bit */
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#define SH4_PCICONF14 (SH4_PCICONF+0x38) /* 32bit */
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#define SH4_PCICONF15 (SH4_PCICONF+0x3c) /* 32bit */
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#define SH4_PCICONF16 (SH4_PCICONF+0x40) /* 32bit */
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#define SH4_PCICONF17 (SH4_PCICONF+0x44) /* 32bit */
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#define SH4_PCICR (SH4_PCIC+0x100) /* 32bit */
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#define SH4_PCILSR0 (SH4_PCIC+0x104) /* 32bit */
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#define SH4_PCILSR1 (SH4_PCIC+0x108) /* 32bit */
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#define SH4_PCILAR0 (SH4_PCIC+0x10c) /* 32bit */
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#define SH4_PCILAR1 (SH4_PCIC+0x110) /* 32bit */
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#define SH4_PCIINT (SH4_PCIC+0x114) /* 32bit */
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#define SH4_PCIINTM (SH4_PCIC+0x118) /* 32bit */
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#define SH4_PCIALR (SH4_PCIC+0x11c) /* 32bit */
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#define SH4_PCICLR (SH4_PCIC+0x120) /* 32bit */
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#define SH4_PCIAINT (SH4_PCIC+0x130) /* 32bit */
|
||||
#define SH4_PCIAINTM (SH4_PCIC+0x134) /* 32bit */
|
||||
#define SH4_PCIDMABT (SH4_PCIC+0x140) /* 32bit */
|
||||
#define SH4_PCIDPA0 (SH4_PCIC+0x180) /* 32bit */
|
||||
#define SH4_PCIDLA0 (SH4_PCIC+0x184) /* 32bit */
|
||||
#define SH4_PCIDTC0 (SH4_PCIC+0x188) /* 32bit */
|
||||
#define SH4_PCIDCR0 (SH4_PCIC+0x18c) /* 32bit */
|
||||
#define SH4_PCIDPA1 (SH4_PCIC+0x190) /* 32bit */
|
||||
#define SH4_PCIDLA1 (SH4_PCIC+0x194) /* 32bit */
|
||||
#define SH4_PCIDTC1 (SH4_PCIC+0x198) /* 32bit */
|
||||
#define SH4_PCIDCR1 (SH4_PCIC+0x19c) /* 32bit */
|
||||
#define SH4_PCIDPA2 (SH4_PCIC+0x1a0) /* 32bit */
|
||||
#define SH4_PCIDLA2 (SH4_PCIC+0x1a4) /* 32bit */
|
||||
#define SH4_PCIDTC2 (SH4_PCIC+0x1a8) /* 32bit */
|
||||
#define SH4_PCIDCR2 (SH4_PCIC+0x1ac) /* 32bit */
|
||||
#define SH4_PCIDPA3 (SH4_PCIC+0x1b0) /* 32bit */
|
||||
#define SH4_PCIDLA3 (SH4_PCIC+0x1b4) /* 32bit */
|
||||
#define SH4_PCIDTC3 (SH4_PCIC+0x1b8) /* 32bit */
|
||||
#define SH4_PCIDCR3 (SH4_PCIC+0x1bc) /* 32bit */
|
||||
#define SH4_PCIPAR (SH4_PCIC+0x1c0) /* 32bit */
|
||||
#define SH4_PCIMBR (SH4_PCIC+0x1c4) /* 32bit */
|
||||
#define SH4_PCIIOBR (SH4_PCIC+0x1c8) /* 32bit */
|
||||
#define SH4_PCIPINT (SH4_PCIC+0x1cc) /* 32bit */
|
||||
#define SH4_PCIPINTM (SH4_PCIC+0x1d0) /* 32bit */
|
||||
#define SH4_PCICLKR (SH4_PCIC+0x1d4) /* 32bit */
|
||||
#define SH4_PCIBCR1 (SH4_PCIC+0x1e0) /* 32bit */
|
||||
#define SH4_PCIBCR2 (SH4_PCIC+0x1e4) /* 32bit */
|
||||
#define SH4_PCIWCR1 (SH4_PCIC+0x1e8) /* 32bit */
|
||||
#define SH4_PCIWCR2 (SH4_PCIC+0x1ec) /* 32bit */
|
||||
#define SH4_PCIWCR3 (SH4_PCIC+0x1f0) /* 32bit */
|
||||
#define SH4_PCIMCR (SH4_PCIC+0x1f4) /* 32bit */
|
||||
#define SH4_PCIBCR3 (SH4_PCIC+0x1f8) /* 32bit: SH7751R */
|
||||
#define SH4_PCIPCTR (SH4_PCIC+0x200) /* 32bit */
|
||||
#define SH4_PCIPDTR (SH4_PCIC+0x204) /* 32bit */
|
||||
#define SH4_PCIPDR (SH4_PCIC+0x220) /* 32bit */
|
||||
|
||||
#define PCICR_BASE 0xa5000000
|
||||
#define PCICR_TRDSGL 0x00000200
|
||||
#define PCICR_BYTESWAP 0x00000100
|
||||
#define PCICR_PCIPUP 0x00000080
|
||||
#define PCICR_BMABT 0x00000040
|
||||
#define PCICR_MD10 0x00000020
|
||||
#define PCICR_MD9 0x00000010
|
||||
#define PCICR_SERR 0x00000008
|
||||
#define PCICR_INTA 0x00000004
|
||||
#define PCICR_RSTCTL 0x00000002
|
||||
#define PCICR_CFINIT 0x00000001
|
||||
|
||||
#define PCIINT_M_LOCKON 0x00008000
|
||||
#define PCIINT_T_TGT_ABORT 0x00004000
|
||||
#define PCIINT_TGT_RETRY 0x00000200
|
||||
#define PCIINT_MST_DIS 0x00000100
|
||||
#define PCIINT_ADRPERR 0x00000080
|
||||
#define PCIINT_SERR_DET 0x00000040
|
||||
#define PCIINT_T_DPERR_WT 0x00000020
|
||||
#define PCIINT_T_PERR_DET 0x00000010
|
||||
#define PCIINT_M_TGT_ABORT 0x00000008
|
||||
#define PCIINT_M_MST_ABORT 0x00000004
|
||||
#define PCIINT_M_DPERR_WT 0x00000002
|
||||
#define PCIINT_M_DPERR_RD 0x00000001
|
||||
#define PCIINT_ALL 0x0000c3ff
|
||||
#define PCIINT_CLEAR_ALL PCIINT_ALL
|
||||
|
||||
#define PCIINTM_MASK_ALL 0x00000000
|
||||
#define PCIINTM_UNMASK_ALL PCIINT_ALL
|
||||
|
||||
#define PCIMBR_MASK 0xff000000
|
||||
|
||||
#define PCIIOBR_MASK 0xffc00000
|
||||
|
||||
#endif /* _SH3_PCICREG_H__ */
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: interrupt.c,v 1.15 2005/07/03 17:59:10 uwe Exp $ */
|
||||
/* $NetBSD: interrupt.c,v 1.16 2005/08/16 11:32:26 nonaka Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2002 The NetBSD Foundation, Inc.
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.15 2005/07/03 17:59:10 uwe Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.16 2005/08/16 11:32:26 nonaka Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/malloc.h>
|
||||
|
|
@ -56,6 +56,8 @@ void intc_intr_priority(int, int);
|
|||
struct intc_intrhand *intc_alloc_ih(void);
|
||||
void intc_free_ih(struct intc_intrhand *);
|
||||
int intc_unknown_intr(void *);
|
||||
void intpri_intr_enable(int);
|
||||
void intpri_intr_disable(int);
|
||||
void netintr(void);
|
||||
void tmu1_oneshot(void);
|
||||
int tmu1_intr(void *);
|
||||
|
|
@ -64,9 +66,9 @@ int tmu2_intr(void *);
|
|||
|
||||
/*
|
||||
* EVTCODE to intc_intrhand mapper.
|
||||
* max #60 is SH7709_INTEVT2_ADC_ADI (0x980)
|
||||
* max #76 is SH4_INTEVT_TMU4 (0xb80)
|
||||
*/
|
||||
int8_t __intc_evtcode_to_ih[64];
|
||||
int8_t __intc_evtcode_to_ih[128];
|
||||
|
||||
struct intc_intrhand __intc_intrhand[_INTR_N + 1] = {
|
||||
/* Place holder interrupt handler for unregistered interrupt. */
|
||||
|
|
@ -96,10 +98,14 @@ intc_init()
|
|||
_reg_write_2(SH3_IPRA, 0);
|
||||
_reg_write_2(SH3_IPRB, 0);
|
||||
break;
|
||||
case CPU_PRODUCT_7750S:
|
||||
case CPU_PRODUCT_7750R:
|
||||
|
||||
case CPU_PRODUCT_7751:
|
||||
case CPU_PRODUCT_7751R:
|
||||
_reg_write_4(SH4_INTPRI00, 0);
|
||||
_reg_write_4(SH4_INTMSK00, INTMSK00_MASK_ALL);
|
||||
/* FALLTHROUGH */
|
||||
case CPU_PRODUCT_7750S:
|
||||
case CPU_PRODUCT_7750R:
|
||||
_reg_write_2(SH4_IPRD, 0);
|
||||
/* FALLTHROUGH */
|
||||
case CPU_PRODUCT_7750:
|
||||
|
|
@ -157,7 +163,24 @@ intc_intr_disable(int evtcode)
|
|||
|
||||
s = _cpu_intr_suspend();
|
||||
KASSERT(EVTCODE_TO_IH_INDEX(evtcode) != 0); /* there is a handler */
|
||||
intc_intr_priority(evtcode, 0);
|
||||
switch (evtcode) {
|
||||
default:
|
||||
intc_intr_priority(evtcode, 0);
|
||||
break;
|
||||
|
||||
#if defined(SH4)
|
||||
case SH4_INTEVT_PCISERR:
|
||||
case SH4_INTEVT_PCIDMA3:
|
||||
case SH4_INTEVT_PCIDMA2:
|
||||
case SH4_INTEVT_PCIDMA1:
|
||||
case SH4_INTEVT_PCIDMA0:
|
||||
case SH4_INTEVT_PCIPWON:
|
||||
case SH4_INTEVT_PCIPWDWN:
|
||||
case SH4_INTEVT_PCIERR:
|
||||
intpri_intr_disable(evtcode);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
_cpu_intr_resume(s);
|
||||
}
|
||||
|
||||
|
|
@ -169,9 +192,26 @@ intc_intr_enable(int evtcode)
|
|||
|
||||
s = _cpu_intr_suspend();
|
||||
KASSERT(EVTCODE_TO_IH_INDEX(evtcode) != 0); /* there is a handler */
|
||||
ih = EVTCODE_IH(evtcode);
|
||||
/* ih_level is in the SR.IMASK format */
|
||||
intc_intr_priority(evtcode, (ih->ih_level >> 4));
|
||||
switch (evtcode) {
|
||||
default:
|
||||
ih = EVTCODE_IH(evtcode);
|
||||
/* ih_level is in the SR.IMASK format */
|
||||
intc_intr_priority(evtcode, (ih->ih_level >> 4));
|
||||
break;
|
||||
|
||||
#if defined(SH4)
|
||||
case SH4_INTEVT_PCISERR:
|
||||
case SH4_INTEVT_PCIDMA3:
|
||||
case SH4_INTEVT_PCIDMA2:
|
||||
case SH4_INTEVT_PCIDMA1:
|
||||
case SH4_INTEVT_PCIDMA0:
|
||||
case SH4_INTEVT_PCIPWON:
|
||||
case SH4_INTEVT_PCIPWDWN:
|
||||
case SH4_INTEVT_PCIERR:
|
||||
intpri_intr_enable(evtcode);
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
_cpu_intr_resume(s);
|
||||
}
|
||||
|
||||
|
|
@ -231,7 +271,7 @@ intc_intr_priority(int evtcode, int level)
|
|||
break;
|
||||
}
|
||||
|
||||
if (CPU_IS_SH3)
|
||||
if (CPU_IS_SH3) {
|
||||
switch (evtcode) {
|
||||
case SH7709_INTEVT2_IRQ3:
|
||||
SH7709_IPR(C, 12);
|
||||
|
|
@ -279,7 +319,7 @@ intc_intr_priority(int evtcode, int level)
|
|||
SH7709_IPR(E, 0);
|
||||
break;
|
||||
}
|
||||
else
|
||||
} else {
|
||||
switch (evtcode) {
|
||||
case SH4_INTEVT_SCIF_ERI:
|
||||
case SH4_INTEVT_SCIF_RXI:
|
||||
|
|
@ -287,7 +327,23 @@ intc_intr_priority(int evtcode, int level)
|
|||
case SH4_INTEVT_SCIF_TXI:
|
||||
SH4_IPR(C, 4);
|
||||
break;
|
||||
|
||||
#if 0
|
||||
case SH4_INTEVT_PCISERR:
|
||||
case SH4_INTEVT_PCIDMA3:
|
||||
case SH4_INTEVT_PCIDMA2:
|
||||
case SH4_INTEVT_PCIDMA1:
|
||||
case SH4_INTEVT_PCIDMA0:
|
||||
case SH4_INTEVT_PCIPWON:
|
||||
case SH4_INTEVT_PCIPWDWN:
|
||||
case SH4_INTEVT_PCIERR:
|
||||
#endif
|
||||
case SH4_INTEVT_TMU3:
|
||||
case SH4_INTEVT_TMU4:
|
||||
intpri_intr_priority(evtcode, level);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX: This function gets called even for interrupts that
|
||||
|
|
@ -343,6 +399,162 @@ intc_unknown_intr(void *arg)
|
|||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* INTPRIxx
|
||||
*/
|
||||
void
|
||||
intpri_intr_priority(int evtcode, int level)
|
||||
{
|
||||
volatile uint32_t *iprreg;
|
||||
uint32_t r;
|
||||
int pos;
|
||||
|
||||
if (!CPU_IS_SH4)
|
||||
return;
|
||||
|
||||
switch (cpu_product) {
|
||||
default:
|
||||
return;
|
||||
|
||||
case CPU_PRODUCT_7751:
|
||||
case CPU_PRODUCT_7751R:
|
||||
break;
|
||||
}
|
||||
|
||||
iprreg = (volatile uint32_t *)SH4_INTPRI00;
|
||||
pos = -1;
|
||||
|
||||
switch (evtcode) {
|
||||
case SH4_INTEVT_PCIDMA3:
|
||||
case SH4_INTEVT_PCIDMA2:
|
||||
case SH4_INTEVT_PCIDMA1:
|
||||
case SH4_INTEVT_PCIDMA0:
|
||||
case SH4_INTEVT_PCIPWDWN:
|
||||
case SH4_INTEVT_PCIPWON:
|
||||
case SH4_INTEVT_PCIERR:
|
||||
pos = 0;
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_PCISERR:
|
||||
pos = 4;
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_TMU3:
|
||||
pos = 8;
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_TMU4:
|
||||
pos = 12;
|
||||
break;
|
||||
}
|
||||
|
||||
if (pos < 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
r = _reg_read_4(iprreg);
|
||||
r = (r & ~(0xf << pos)) | (level << pos);
|
||||
_reg_write_4(iprreg, r);
|
||||
}
|
||||
|
||||
void
|
||||
intpri_intr_enable(int evtcode)
|
||||
{
|
||||
volatile uint32_t *iprreg;
|
||||
uint32_t bit;
|
||||
|
||||
if (!CPU_IS_SH4)
|
||||
return;
|
||||
|
||||
switch (cpu_product) {
|
||||
default:
|
||||
return;
|
||||
|
||||
case CPU_PRODUCT_7751:
|
||||
case CPU_PRODUCT_7751R:
|
||||
break;
|
||||
}
|
||||
|
||||
iprreg = (volatile uint32_t *)SH4_INTMSKCLR00;
|
||||
bit = 0;
|
||||
|
||||
switch (evtcode) {
|
||||
case SH4_INTEVT_PCISERR:
|
||||
case SH4_INTEVT_PCIDMA3:
|
||||
case SH4_INTEVT_PCIDMA2:
|
||||
case SH4_INTEVT_PCIDMA1:
|
||||
case SH4_INTEVT_PCIDMA0:
|
||||
case SH4_INTEVT_PCIPWON:
|
||||
case SH4_INTEVT_PCIPWDWN:
|
||||
case SH4_INTEVT_PCIERR:
|
||||
bit = (1 << ((evtcode - SH4_INTEVT_PCISERR) >> 5));
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_TMU3:
|
||||
bit = INTREQ00_TUNI3;
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_TMU4:
|
||||
bit = INTREQ00_TUNI4;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((bit == 0) || (iprreg == NULL)) {
|
||||
return;
|
||||
}
|
||||
|
||||
_reg_write_4(iprreg, bit);
|
||||
}
|
||||
|
||||
void
|
||||
intpri_intr_disable(int evtcode)
|
||||
{
|
||||
volatile uint32_t *iprreg;
|
||||
uint32_t bit;
|
||||
|
||||
if (!CPU_IS_SH4)
|
||||
return;
|
||||
|
||||
switch (cpu_product) {
|
||||
default:
|
||||
return;
|
||||
|
||||
case CPU_PRODUCT_7751:
|
||||
case CPU_PRODUCT_7751R:
|
||||
break;
|
||||
}
|
||||
|
||||
iprreg = (volatile uint32_t *)SH4_INTMSK00;
|
||||
bit = 0;
|
||||
|
||||
switch (evtcode) {
|
||||
case SH4_INTEVT_PCISERR:
|
||||
case SH4_INTEVT_PCIDMA3:
|
||||
case SH4_INTEVT_PCIDMA2:
|
||||
case SH4_INTEVT_PCIDMA1:
|
||||
case SH4_INTEVT_PCIDMA0:
|
||||
case SH4_INTEVT_PCIPWON:
|
||||
case SH4_INTEVT_PCIPWDWN:
|
||||
case SH4_INTEVT_PCIERR:
|
||||
bit = (1 << ((evtcode - SH4_INTEVT_PCISERR) >> 5));
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_TMU3:
|
||||
bit = INTREQ00_TUNI3;
|
||||
break;
|
||||
|
||||
case SH4_INTEVT_TMU4:
|
||||
bit = INTREQ00_TUNI4;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((bit == 0) || (iprreg == NULL)) {
|
||||
return;
|
||||
}
|
||||
|
||||
_reg_write_4(iprreg, bit);
|
||||
}
|
||||
|
||||
/*
|
||||
* Software interrupt support
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue