1994-10-26 10:48:18 +03:00
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* $NetBSD: x_unfl.sa,v 1.3 1994/10/26 07:50:30 cgd Exp $
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1994-07-05 21:50:24 +04:00
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* MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
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* M68000 Hi-Performance Microprocessor Division
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* M68040 Software Package
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*
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* M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc.
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* All rights reserved.
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*
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* THE SOFTWARE is provided on an "AS IS" basis and without warranty.
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* To the maximum extent permitted by applicable law,
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* MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
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* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
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* PARTICULAR PURPOSE and any warranty against infringement with
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* regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
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* and any accompanying written materials.
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*
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* To the maximum extent permitted by applicable law,
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* IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
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* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
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* PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
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* OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
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* SOFTWARE. Motorola assumes no responsibility for the maintenance
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* and support of the SOFTWARE.
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*
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* You are hereby granted a copyright license to use, modify, and
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* distribute the SOFTWARE so long as this entire notice is retained
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* without alteration in any modified and/or redistributed versions,
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* and that such modified versions are clearly identified as such.
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* No licenses are granted by implication, estoppel or otherwise
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* under any patents or trademarks of Motorola, Inc.
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*
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* x_unfl.sa 3.4 7/1/91
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*
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* fpsp_unfl --- FPSP handler for underflow exception
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*
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* Trap disabled results
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* For 881/2 compatibility, sw must denormalize the intermediate
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* result, then store the result. Denormalization is accomplished
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* by taking the intermediate result (which is always normalized) and
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* shifting the mantissa right while incrementing the exponent until
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* it is equal to the denormalized exponent for the destination
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* format. After denormalizatoin, the result is rounded to the
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* destination format.
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*
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* Trap enabled results
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* All trap disabled code applies. In addition the exceptional
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* operand needs to made available to the user with a bias of $6000
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* added to the exponent.
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*
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X_UNFL IDNT 2,1 Motorola 040 Floating Point Software Package
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section 8
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include fpsp.h
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xref denorm
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xref round
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xref store
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xref g_rndpr
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xref g_opcls
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xref g_dfmtou
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xref real_unfl
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xref real_inex
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xref fpsp_done
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xref b1238_fix
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xdef fpsp_unfl
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fpsp_unfl:
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link a6,#-LOCAL_SIZE
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fsave -(a7)
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movem.l d0-d1/a0-a1,USER_DA(a6)
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fmovem.x fp0-fp3,USER_FP0(a6)
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fmovem.l fpcr/fpsr/fpiar,USER_FPCR(a6)
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*
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bsr.l unf_res ;denormalize, round & store interm op
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*
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* If underflow exceptions are not enabled, check for inexact
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* exception
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*
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btst.b #unfl_bit,FPCR_ENABLE(a6)
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beq.b ck_inex
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btst.b #E3,E_BYTE(a6)
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beq.b no_e3_1
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*
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* Clear dirty bit on dest resister in the frame before branching
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* to b1238_fix.
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*
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bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no
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bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
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bsr.l b1238_fix ;test for bug1238 case
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move.l USER_FPSR(a6),FPSR_SHADOW(a6)
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or.l #sx_mask,E_BYTE(a6)
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no_e3_1:
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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frestore (a7)+
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unlk a6
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bra.l real_unfl
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*
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* It is possible to have either inex2 or inex1 exceptions with the
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* unfl. If the inex enable bit is set in the FPCR, and either
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* inex2 or inex1 occured, we must clean up and branch to the
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* real inex handler.
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*
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ck_inex:
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move.b FPCR_ENABLE(a6),d0
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and.b FPSR_EXCEPT(a6),d0
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andi.b #$3,d0
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beq.b unfl_done
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*
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* Inexact enabled and reported, and we must take an inexact exception
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*
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take_inex:
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btst.b #E3,E_BYTE(a6)
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beq.b no_e3_2
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*
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* Clear dirty bit on dest resister in the frame before branching
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* to b1238_fix.
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*
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bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no
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bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
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bsr.l b1238_fix ;test for bug1238 case
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move.l USER_FPSR(a6),FPSR_SHADOW(a6)
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or.l #sx_mask,E_BYTE(a6)
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no_e3_2:
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move.b #INEX_VEC,EXC_VEC+1(a6)
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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frestore (a7)+
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unlk a6
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bra.l real_inex
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unfl_done:
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bclr.b #E3,E_BYTE(a6)
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beq.b e1_set ;if set then branch
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*
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* Clear dirty bit on dest resister in the frame before branching
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* to b1238_fix.
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*
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bfextu CMDREG3B(a6){6:3},d0 ;get dest reg no
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bclr.b d0,FPR_DIRTY_BITS(a6) ;clr dest dirty bit
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bsr.l b1238_fix ;test for bug1238 case
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move.l USER_FPSR(a6),FPSR_SHADOW(a6)
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or.l #sx_mask,E_BYTE(a6)
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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frestore (a7)+
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unlk a6
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bra.l fpsp_done
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e1_set:
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movem.l USER_DA(a6),d0-d1/a0-a1
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fmovem.x USER_FP0(a6),fp0-fp3
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fmovem.l USER_FPCR(a6),fpcr/fpsr/fpiar
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unlk a6
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bra.l fpsp_done
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*
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* unf_res --- underflow result calculation
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*
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unf_res:
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bsr.l g_rndpr ;returns RND_PREC in d0 0=ext,
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* ;1=sgl, 2=dbl
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* ;we need the RND_PREC in the
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* ;upper word for round
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1994-07-05 21:56:52 +04:00
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clr.w -(a7)
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1994-07-05 21:50:24 +04:00
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move.w d0,-(a7) ;copy RND_PREC to stack
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*
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*
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* If the exception bit set is E3, the exceptional operand from the
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* fpu is in WBTEMP; else it is in FPTEMP.
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*
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btst.b #E3,E_BYTE(a6)
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beq.b unf_E1
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unf_E3:
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lea WBTEMP(a6),a0 ;a0 now points to operand
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*
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* Test for fsgldiv and fsglmul. If the inst was one of these, then
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* force the precision to extended for the denorm routine. Use
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* the user's precision for the round routine.
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*
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move.w CMDREG3B(a6),d1 ;check for fsgldiv or fsglmul
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andi.w #$7f,d1
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cmpi.w #$30,d1 ;check for sgldiv
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beq.b unf_sgl
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cmpi.w #$33,d1 ;check for sglmul
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bne.b unf_cont ;if not, use fpcr prec in round
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unf_sgl:
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clr.l d0
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move.w #$1,(a7) ;override g_rndpr precision
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* ;force single
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bra.b unf_cont
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unf_E1:
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lea FPTEMP(a6),a0 ;a0 now points to operand
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unf_cont:
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bclr.b #sign_bit,LOCAL_EX(a0) ;clear sign bit
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sne LOCAL_SGN(a0) ;store sign
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bsr.l denorm ;returns denorm, a0 points to it
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*
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* WARNING:
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* ;d0 has guard,round sticky bit
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* ;make sure that it is not corrupted
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* ;before it reaches the round subroutine
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* ;also ensure that a0 isn't corrupted
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*
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* Set up d1 for round subroutine d1 contains the PREC/MODE
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* information respectively on upper/lower register halves.
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*
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bfextu FPCR_MODE(a6){2:2},d1 ;get mode from FPCR
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* ;mode in lower d1
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add.l (a7)+,d1 ;merge PREC/MODE
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*
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* WARNING: a0 and d0 are assumed to be intact between the denorm and
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* round subroutines. All code between these two subroutines
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* must not corrupt a0 and d0.
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*
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*
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* Perform Round
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* Input: a0 points to input operand
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* d0{31:29} has guard, round, sticky
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* d1{01:00} has rounding mode
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* d1{17:16} has rounding precision
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* Output: a0 points to rounded operand
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*
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bsr.l round ;returns rounded denorm at (a0)
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*
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* Differentiate between store to memory vs. store to register
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*
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unf_store:
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bsr.l g_opcls ;returns opclass in d0{2:0}
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cmpi.b #$3,d0
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bne.b not_opc011
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*
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* At this point, a store to memory is pending
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*
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opc011:
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bsr.l g_dfmtou
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tst.b d0
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beq.b ext_opc011 ;If extended, do not subtract
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* ;If destination format is sgl/dbl,
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tst.b LOCAL_HI(a0) ;If rounded result is normal,don't
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* ;subtract
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bmi.b ext_opc011
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subq.w #1,LOCAL_EX(a0) ;account for denorm bias vs.
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* ;normalized bias
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* ; normalized denormalized
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* ;single $7f $7e
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* ;double $3ff $3fe
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*
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ext_opc011:
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bsr.l store ;stores to memory
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bra.b unf_done ;finish up
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*
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* At this point, a store to a float register is pending
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*
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not_opc011:
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bsr.l store ;stores to float register
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* ;a0 is not corrupted on a store to a
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* ;float register.
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*
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* Set the condition codes according to result
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*
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tst.l LOCAL_HI(a0) ;check upper mantissa
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bne.b ck_sgn
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tst.l LOCAL_LO(a0) ;check lower mantissa
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bne.b ck_sgn
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bset.b #z_bit,FPSR_CC(a6) ;set condition codes if zero
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ck_sgn:
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btst.b #sign_bit,LOCAL_EX(a0) ;check the sign bit
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beq.b unf_done
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bset.b #neg_bit,FPSR_CC(a6)
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*
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* Finish.
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*
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unf_done:
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btst.b #inex2_bit,FPSR_EXCEPT(a6)
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beq.b no_aunfl
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bset.b #aunfl_bit,FPSR_AEXCEPT(a6)
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no_aunfl:
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rts
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end
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