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NetBSD/usr.sbin/cpuctl/cpuctl.h

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Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors. - If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors can take TSC/core crystal clock ratio but core crystal clock frequency can't be taken. Intel SDM give us the values for some processors. - It also required to change lapic_per_second to make LAPIC timer correctly. - Add new file x86/x86/identcpu_subr.c to share common subroutines between kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c will be moved to this file in future. - Add comment to clarify.
2020-04-21 05:56:36 +03:00
/* $NetBSD: cpuctl.h,v 1.7 2020/04/21 02:56:37 msaitoh Exp $ */
PR port-amd64/37461 x86 cpu dmesg output is noisy Port identifycpu() to userspace. The kernel lies and reports on cpuN while actually using the values from cpu0, but this attempts to bind itself to the requested CPU if running as root. That doesn't work properly yet due to kern/38588, but will do once that's fixed.
2008-05-05 21:54:14 +04:00
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors. - If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors can take TSC/core crystal clock ratio but core crystal clock frequency can't be taken. Intel SDM give us the values for some processors. - It also required to change lapic_per_second to make LAPIC timer correctly. - Add new file x86/x86/identcpu_subr.c to share common subroutines between kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c will be moved to this file in future. - Add comment to clarify.
2020-04-21 05:56:36 +03:00
#include <sys/cpuio.h>
Add __printflike attribution to use vprintf and friends with an argument as format string.
2012-03-15 06:02:20 +04:00
int aprint_normal(const char *, ...) __printflike(1, 2);
int aprint_verbose(const char *, ...) __printflike(1, 2);
int aprint_error(const char *, ...) __printflike(1, 2);
int aprint_normal_dev(const char *, const char *, ...) __printflike(2, 3);
int aprint_verbose_dev(const char *, const char *, ...) __printflike(2, 3);
int aprint_error_dev(const char *, const char *, ...) __printflike(2, 3);
Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors. - If the max CPUID leaf is >= 0x15, take TSC value from CPUID. Some processors can take TSC/core crystal clock ratio but core crystal clock frequency can't be taken. Intel SDM give us the values for some processors. - It also required to change lapic_per_second to make LAPIC timer correctly. - Add new file x86/x86/identcpu_subr.c to share common subroutines between kernel and userland. Some code in x86/x86/identcpu.c and cpuctl/arch/i386.c will be moved to this file in future. - Add comment to clarify.
2020-04-21 05:56:36 +03:00
int aprint_debug_dev(const char *, const char *, ...) __printflike(2, 3);
PR port-amd64/37461 x86 cpu dmesg output is noisy Port identifycpu() to userspace. The kernel lies and reports on cpuN while actually using the values from cpu0, but this attempts to bind itself to the requested CPU if running as root. That doesn't work properly yet due to kern/38588, but will do once that's fixed.
2008-05-05 21:54:14 +04:00
Extend the CPU microcode update framework to support Intel x86 CPUs. Contrary to the AMD implementation, it doesn't use xcalls to distribute the update to all CPUs but relies on cpuctl(8) to bind itself to the right CPU -- to keep it simple and avoid possible problems with hyperthreading. Also, it doesn't parse the vendor supplied file to pick the right part for the present CPU model but relies on userland to prepare files with specific filenames. I'll commit a pkg for this in a minute (pkgsrc/sysutils/intel-microcode). The ioctl interface changed; compatibility is provided (should be limited to COMPAT_NETBSD6 as soon as this is available).
2012-08-29 21:13:21 +04:00
void identifycpu(int, const char *);
implement cpuctl identify for sparc and sparc64. sparc: - move enum vactype and struct cacheinfo into cpu.h - move the cache flags from cpuinfo.flags into CACHEINFO.c_flags (this allows the new cache_printf_backend() to see them.) remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA. - align xmpsg to 64 bytes - move cache_print() into cache_print.h so it can be shared with cpuctl. it only depends upon a working printf(). - if found, store the CPU node's "name" into cpu_longname. this changes the default output to show the local CPU not the generic CPU family. eg: cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU vs the generic "RT620/625" previously shown. - for each CPU export these things: - name - fpuname - mid - cloc - freq - psr impl and version - mmu impl, version, and number of contexts - cacheinfo structure (which changed for the first time ever with this commit.) sparc64: - add a minimal "cacheinfo" structure to export the i/d/e-cache size and linesize. - store %ver, cpu node "name" and cacheinfo in cpu_info. - set cpu_info ver, name and cacheinfo in cpu_attach(), and export them via sysctl, as well as CPU ID and clock freq cpuctl: - add identifycpu_bind() that returns false on !x86 as their identify routines do not need to run on a particular CPU to obtain its information, and use it to avoid trying to set affinity when not needed. - add sparc and sparc64 cpu identify support using the newly exported values.
2018-01-16 11:23:17 +03:00
bool identifycpu_bind(void);
Extend the CPU microcode update framework to support Intel x86 CPUs. Contrary to the AMD implementation, it doesn't use xcalls to distribute the update to all CPUs but relies on cpuctl(8) to bind itself to the right CPU -- to keep it simple and avoid possible problems with hyperthreading. Also, it doesn't parse the vendor supplied file to pick the right part for the present CPU model but relies on userland to prepare files with specific filenames. I'll commit a pkg for this in a minute (pkgsrc/sysutils/intel-microcode). The ioctl interface changed; compatibility is provided (should be limited to COMPAT_NETBSD6 as soon as this is available).
2012-08-29 21:13:21 +04:00
int ucodeupdate_check(int, struct cpu_ucode *);
Add verbose flag. On x86 cpu, cpuctl -v identify dumps the return values of the cpuid functions. The max levels are taken from CPUID 0 and CPUID 8000_0000. It's useful for the future CPU.
2013-12-23 16:35:33 +04:00
extern int verbose;
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