1996-09-01 04:54:34 +04:00
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/* $NetBSD: ahbreg.h,v 1.2 1996/09/01 00:54:34 mycroft Exp $ */
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/*
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* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Originally written by Julian Elischer (julian@tfs.com)
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* for TRW Financial Systems for use under the MACH(2.5) operating system.
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*
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* TRW Financial Systems, in accordance with their agreement with Carnegie
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* Mellon University, makes this software available to CMU to distribute
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* or use in any manner that they see fit as long as this message is kept with
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* the software. For this reason TFS also grants any other persons or
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* organisations permission to use or modify this software.
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*
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* TFS supplies this software to be publicly redistributed
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* on the understanding that TFS is not responsible for the correct
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* functioning of this software in any circumstances.
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*/
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1996-09-01 04:49:48 +04:00
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typedef u_long physaddr;
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typedef u_long physlen;
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/*
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* AHA1740 EISA board mode registers (Offset from slot base)
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*/
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#define PORTADDR 0xCC0
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#define PORTADDR_ENHANCED 0x80
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#define BIOSADDR 0xCC1
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#define INTDEF 0xCC2
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#define SCSIDEF 0xCC3
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#define BUSDEF 0xCC4
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#define RESV0 0xCC5
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#define RESV1 0xCC6
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#define RESV2 0xCC7
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/**** bit definitions for INTDEF ****/
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#define INT9 0x00
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#define INT10 0x01
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#define INT11 0x02
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#define INT12 0x03
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#define INT14 0x05
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#define INT15 0x06
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#define INTHIGH 0x08 /* int high=ACTIVE (else edge) */
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#define INTEN 0x10
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/**** bit definitions for SCSIDEF ****/
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#define HSCSIID 0x0F /* our SCSI ID */
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#define RSTPWR 0x10 /* reset scsi bus on power up or reset */
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/**** bit definitions for BUSDEF ****/
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#define B0uS 0x00 /* give up bus immediatly */
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#define B4uS 0x01 /* delay 4uSec. */
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#define B8uS 0x02
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/*
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* AHA1740 ENHANCED mode mailbox control regs (Offset from slot base)
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*/
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#define MBOXOUT0 0xCD0
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#define MBOXOUT1 0xCD1
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#define MBOXOUT2 0xCD2
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#define MBOXOUT3 0xCD3
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#define ATTN 0xCD4
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#define G2CNTRL 0xCD5
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#define G2INTST 0xCD6
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#define G2STAT 0xCD7
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#define MBOXIN0 0xCD8
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#define MBOXIN1 0xCD9
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#define MBOXIN2 0xCDA
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#define MBOXIN3 0xCDB
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#define G2STAT2 0xCDC
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/*
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* Bit definitions for the 5 control/status registers
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*/
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#define ATTN_TARGET 0x0F
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#define ATTN_OPCODE 0xF0
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#define OP_IMMED 0x10
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#define AHB_TARG_RESET 0x80
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#define OP_START_ECB 0x40
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#define OP_ABORT_ECB 0x50
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#define G2CNTRL_SET_HOST_READY 0x20
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#define G2CNTRL_CLEAR_EISA_INT 0x40
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#define G2CNTRL_HARD_RESET 0x80
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#define G2INTST_TARGET 0x0F
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#define G2INTST_INT_STAT 0xF0
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#define AHB_ECB_OK 0x10
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#define AHB_ECB_RECOVERED 0x50
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#define AHB_HW_ERR 0x70
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#define AHB_IMMED_OK 0xA0
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#define AHB_ECB_ERR 0xC0
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#define AHB_ASN 0xD0 /* for target mode */
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#define AHB_IMMED_ERR 0xE0
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#define G2STAT_BUSY 0x01
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#define G2STAT_INT_PEND 0x02
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#define G2STAT_MBOX_EMPTY 0x04
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#define G2STAT2_HOST_READY 0x01
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#define AHB_NSEG 33 /* number of dma segments supported */
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struct ahb_dma_seg {
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physaddr seg_addr;
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physlen seg_len;
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};
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struct ahb_ecb_status {
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u_short status;
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#define ST_DON 0x0001
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#define ST_DU 0x0002
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#define ST_QF 0x0008
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#define ST_SC 0x0010
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#define ST_DO 0x0020
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#define ST_CH 0x0040
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#define ST_INT 0x0080
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#define ST_ASA 0x0100
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#define ST_SNS 0x0200
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#define ST_INI 0x0800
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#define ST_ME 0x1000
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#define ST_ECA 0x4000
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u_char host_stat;
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#define HS_OK 0x00
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#define HS_CMD_ABORTED_HOST 0x04
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#define HS_CMD_ABORTED_ADAPTER 0x05
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#define HS_TIMED_OUT 0x11
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#define HS_HARDWARE_ERR 0x20
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#define HS_SCSI_RESET_ADAPTER 0x22
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#define HS_SCSI_RESET_INCOMING 0x23
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u_char target_stat;
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u_long resid_count;
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u_long resid_addr;
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u_short addit_status;
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u_char sense_len;
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u_char unused[9];
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u_char cdb[6];
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};
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struct ahb_ecb {
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u_char opcode;
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#define ECB_SCSI_OP 0x01
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u_char:4;
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u_char options:3;
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u_char:1;
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short opt1;
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#define ECB_CNE 0x0001
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#define ECB_DI 0x0080
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#define ECB_SES 0x0400
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#define ECB_S_G 0x1000
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#define ECB_DSB 0x4000
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#define ECB_ARS 0x8000
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short opt2;
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#define ECB_LUN 0x0007
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#define ECB_TAG 0x0008
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#define ECB_TT 0x0030
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#define ECB_ND 0x0040
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#define ECB_DAT 0x0100
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#define ECB_DIR 0x0200
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#define ECB_ST 0x0400
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#define ECB_CHK 0x0800
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#define ECB_REC 0x4000
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#define ECB_NRB 0x8000
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u_short unused1;
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physaddr data_addr;
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physlen data_length;
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physaddr status;
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physaddr link_addr;
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short unused2;
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short unused3;
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physaddr sense_ptr;
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u_char req_sense_length;
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u_char scsi_cmd_length;
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short cksum;
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struct scsi_generic scsi_cmd;
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struct ahb_dma_seg ahb_dma[AHB_NSEG];
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struct ahb_ecb_status ecb_status;
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struct scsi_sense_data ecb_sense;
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/*-----------------end of hardware supported fields----------------*/
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TAILQ_ENTRY(ahb_ecb) chain;
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struct ahb_ecb *nexthash;
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long hashkey;
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struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
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int flags;
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#define ECB_ALLOC 0x01
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#define ECB_ABORT 0x02
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#define ECB_IMMED 0x04
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#define ECB_IMMED_FAIL 0x08
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int timeout;
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};
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