1996-10-16 06:10:33 +04:00
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/* $NetBSD: dc.c,v 1.30 1996/10/16 02:10:33 jonathan Exp $ */
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1994-10-27 00:08:38 +03:00
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1993-10-12 06:22:19 +03:00
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/*-
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1994-05-27 12:39:00 +04:00
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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1993-10-12 06:22:19 +03:00
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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1996-09-11 10:41:19 +04:00
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* @(#)dc.c 8.5 (Berkeley) 6/2/95
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1993-10-12 06:22:19 +03:00
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*/
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/*
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* devDC7085.c --
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*
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* This file contains machine-dependent routines that handle the
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* output queue for the serial lines.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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1994-05-27 12:39:00 +04:00
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* from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/devDC7085.c,
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* v 1.4 89/08/29 11:55:30 nelson Exp SPRITE (DECWRL)";
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1993-10-12 06:22:19 +03:00
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*/
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/*
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* DC7085 (DZ-11 look alike) Driver
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*/
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1996-09-17 23:34:40 +04:00
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1993-10-12 06:22:19 +03:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/proc.h>
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#include <sys/map.h>
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#include <sys/buf.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/uio.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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1996-05-19 04:58:03 +04:00
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#include <machine/conf.h>
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1995-08-04 04:26:35 +04:00
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#include <sys/device.h>
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#include <machine/autoconf.h>
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1996-05-29 10:15:40 +04:00
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#include <dev/tc/tcvar.h>
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#include <dev/tc/ioasicvar.h>
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1995-08-04 04:26:35 +04:00
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1993-10-12 06:22:19 +03:00
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#include <machine/dc7085cons.h>
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#include <machine/pmioctl.h>
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#include <pmax/pmax/pmaxtype.h>
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#include <pmax/pmax/cons.h>
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1995-09-12 01:29:23 +04:00
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#include <pmax/dev/lk201.h>
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1993-10-12 06:22:19 +03:00
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1996-09-26 00:48:51 +04:00
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/*
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* XXX in dcvar.h or not?
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* #include <pmax/dev/pdma.h>
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*/
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1995-08-04 04:26:35 +04:00
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#include "dcvar.h"
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1996-09-26 00:48:51 +04:00
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1996-05-29 10:15:40 +04:00
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#include "tc.h"
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1995-08-04 04:26:35 +04:00
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1996-05-19 04:58:03 +04:00
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#include <pmax/dev/lk201var.h> /* XXX KbdReset band friends */
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1996-09-26 00:48:51 +04:00
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#include <pmax/dev/dcvar.h>
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#include <pmax/dev/dc_cons.h>
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1993-10-12 06:22:19 +03:00
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1996-09-26 00:48:51 +04:00
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extern struct cfdriver mainbus_cd;
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1996-01-30 01:52:15 +03:00
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1996-09-17 23:34:40 +04:00
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#define DCUNIT(dev) (minor(dev) >> 2)
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#define DCLINE(dev) (minor(dev) & 3)
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1993-10-12 06:22:19 +03:00
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/*
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1996-01-30 01:52:15 +03:00
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* Autoconfiguration data for config.
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*
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1995-08-04 04:26:35 +04:00
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* Use the statically-allocated softc until old autoconfig code and
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* config.old are completely gone.
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*/
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1996-09-26 00:48:51 +04:00
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int old_dcmatch __P((struct device * parent, void *cfdata, void *aux));
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void old_dcattach __P((struct device *parent, struct device *self, void *aux));
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1995-08-04 04:26:35 +04:00
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1996-03-17 04:38:52 +03:00
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extern struct cfdriver dc_cd;
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struct cfdriver dc_cd = {
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NULL, "dc", DV_TTY
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1995-08-04 04:26:35 +04:00
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};
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1993-10-12 06:22:19 +03:00
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1996-09-17 23:34:40 +04:00
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/*
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* Forward declarations
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*/
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struct tty *dctty __P((dev_t dev));
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1993-10-12 06:22:19 +03:00
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void dcstart __P((struct tty *));
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1996-09-17 23:34:40 +04:00
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void dcrint __P((struct dc_softc *sc));
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1993-10-12 06:22:19 +03:00
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void dcxint __P((struct tty *));
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1996-09-17 23:34:40 +04:00
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int dcmctl __P((dev_t dev, int bits, int how));
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1993-10-12 06:22:19 +03:00
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void dcscan __P((void *));
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1996-10-13 16:25:50 +04:00
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int dcparam __P((struct tty *tp, struct termios *t));
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static int cold_dcparam __P((struct tty *tp, struct termios *t,
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dcregs *dcaddr, int allow_19200));
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1996-09-17 23:34:40 +04:00
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extern void ttrstrt __P((void *));
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1996-09-26 00:48:51 +04:00
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void dc_reset __P ((dcregs *dcaddr));
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1996-09-17 23:34:40 +04:00
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/* console I/O */
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int dcGetc __P((dev_t));
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void dcPutc __P((dev_t, int));
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void dcPollc __P((dev_t, int));
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void dc_consinit __P((dev_t dev, dcregs *dcaddr));
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1993-10-12 06:22:19 +03:00
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1996-09-17 23:34:40 +04:00
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/* QVSS-compatible in-kernel X input event parser, pointer tracker */
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void (*dcDivertXInput) __P((int cc)); /* X windows keyboard input routine */
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void (*dcMouseEvent) __P((int)); /* X windows mouse motion event routine */
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void (*dcMouseButtons) __P((int)); /* X windows mouse buttons event routine */
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1993-10-12 06:22:19 +03:00
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#ifdef DEBUG
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int debugChar;
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#endif
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/*
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* The DC7085 doesn't interrupt on carrier transitions, so
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* we have to use a timer to watch it.
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*/
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int dc_timer; /* true if timer started */
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/*
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* Pdma structures for fast output code
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*/
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struct speedtab dcspeedtab[] = {
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1996-05-19 04:58:03 +04:00
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{ 0, 0, },
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{ 50, LPR_B50 },
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{ 75, LPR_B75 },
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{ 110, LPR_B110 },
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{ 134, LPR_B134 },
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{ 150, LPR_B150 },
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{ 300, LPR_B300 },
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{ 600, LPR_B600 },
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{ 1200, LPR_B1200 },
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{ 1800, LPR_B1800 },
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{ 2400, LPR_B2400 },
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{ 4800, LPR_B4800 },
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{ 9600, LPR_B9600 },
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{ 19200,LPR_B19200 },
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1996-09-17 23:34:40 +04:00
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#ifdef notyet
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{ 19200,LPR_B38400 }, /* Overloaded with 19200, per chip. */
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#endif
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1996-05-19 04:58:03 +04:00
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{ -1, -1 }
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1993-10-12 06:22:19 +03:00
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};
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#ifndef PORTSELECTOR
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#define ISPEED TTYDEF_SPEED
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#define LFLAG TTYDEF_LFLAG
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#else
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#define ISPEED B4800
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#define LFLAG (TTYDEF_LFLAG & ~ECHO)
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#endif
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1995-08-04 04:26:35 +04:00
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/*
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1996-09-26 00:48:51 +04:00
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* Console line variables, for use when cold
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1995-08-04 04:26:35 +04:00
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*/
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1996-09-26 00:48:51 +04:00
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extern int cold;
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dcregs *dc_cons_addr = 0;
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1995-08-04 04:26:35 +04:00
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1995-09-12 01:29:23 +04:00
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/*
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* Is there a framebuffer console device using this serial driver?
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* XXX used for ugly special-cased console input that should be redone
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* more cleanly.
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*/
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1996-05-19 04:58:03 +04:00
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static inline int raster_console __P((void));
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1995-09-12 01:29:23 +04:00
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static inline int
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raster_console()
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{
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return (cn_tab->cn_pri == CN_INTERNAL ||
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cn_tab->cn_pri == CN_NORMAL);
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}
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1995-08-04 04:26:35 +04:00
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1996-09-26 00:48:51 +04:00
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/* XXX move back into dc_consinit when debugged */
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static struct consdev dccons = {
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NULL, NULL, dcGetc, dcPutc, dcPollc, NODEV, CN_REMOTE
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};
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1996-09-17 23:34:40 +04:00
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/*
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* Special-case code to attach a console.
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* We were using PROM callbacks for console I/O,
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* and we just reset the chip under the console.
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* wire up this driver as console ASAP.
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*
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* Must be called at spltty() or higher.
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*/
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void
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dc_consinit(dev, dcaddr)
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dev_t dev;
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register dcregs *dcaddr;
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{
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struct termios cterm;
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struct tty ctty;
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1996-09-26 00:48:51 +04:00
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/* save address in case we're cold */
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if (cold && dc_cons_addr == 0)
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dc_cons_addr = dcaddr;
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/* reset chip */
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dc_reset(dcaddr);
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1996-09-17 23:34:40 +04:00
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dcaddr->dc_lpr = LPR_RXENAB | LPR_8_BIT_CHAR |
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LPR_B9600 | DCLINE(dev);
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wbflush();
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DELAY(10);
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bzero(&cterm, sizeof(cterm));
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bzero(&ctty, sizeof(ctty));
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ctty.t_dev = dev;
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dccons.cn_dev = dev;
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cterm.c_cflag |= CLOCAL;
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1996-10-13 16:25:50 +04:00
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cterm.c_cflag = CS8;
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cterm.c_ospeed = 9600;
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1996-09-26 00:48:51 +04:00
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*cn_tab = dccons;
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1996-10-13 16:25:50 +04:00
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cold_dcparam(&ctty, &cterm, dcaddr, 0); /* XXX untested */
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1996-09-17 23:34:40 +04:00
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}
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1996-01-30 01:52:15 +03:00
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/*
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1996-09-26 00:48:51 +04:00
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* Attach DC7085 (dz-11) device.
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1996-01-30 01:52:15 +03:00
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*/
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int
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1996-09-26 00:48:51 +04:00
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dcattach(sc, addr, dtr_mask, rtscts_mask, speed,
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1996-09-17 23:34:40 +04:00
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console_line)
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register struct dc_softc *sc;
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1995-08-04 04:26:35 +04:00
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void *addr;
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1996-09-17 23:34:40 +04:00
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int dtr_mask, rtscts_mask, speed, console_line;
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1993-10-12 06:22:19 +03:00
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{
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register dcregs *dcaddr;
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register struct pdma *pdp;
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register struct tty *tp;
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1996-09-17 23:34:40 +04:00
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register int line;
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1993-10-12 06:22:19 +03:00
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int s;
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1996-09-17 23:34:40 +04:00
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1996-09-26 00:48:51 +04:00
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dcaddr = (dcregs *)addr;
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1995-08-04 04:26:35 +04:00
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1993-10-12 06:22:19 +03:00
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/*
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* For a remote console, wait a while for previous output to
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* complete.
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1996-09-17 23:34:40 +04:00
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* XXX both cn_dev == 0 and cn_pri == CN_DEAD are bug workarounds.
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* The interface between ttys and cpu_cons.c should be reworked.
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1993-10-12 06:22:19 +03:00
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*/
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1996-09-17 23:34:40 +04:00
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if (sc->sc_dv.dv_unit == 0 && /* XXX why only unit 0? */
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(major(cn_tab->cn_dev) == DCDEV || major(cn_tab->cn_dev) == 0) &&
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1996-09-26 00:48:51 +04:00
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(cn_tab->cn_pri == CN_REMOTE || (cn_tab->cn_pri == CN_DEAD))) {
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1993-10-12 06:22:19 +03:00
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DELAY(10000);
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1996-09-26 00:48:51 +04:00
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}
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/* reset chip and enable interrupts */
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dc_reset(dcaddr);
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dcaddr->dc_csr |= (CSR_MSE | CSR_TIE | CSR_RIE);
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1993-10-12 06:22:19 +03:00
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/* init pseudo DMA structures */
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1996-09-17 23:34:40 +04:00
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pdp = &sc->dc_pdma[0];
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for (line = 0; line < 4; line++) {
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1993-10-12 06:22:19 +03:00
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pdp->p_addr = (void *)dcaddr;
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1996-09-17 23:34:40 +04:00
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tp = sc->dc_tty[line] = ttymalloc();
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if (line != DCKBD_PORT && line != DCMOUSE_PORT)
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1996-06-16 20:50:56 +04:00
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tty_attach(tp);
|
1996-09-17 23:34:40 +04:00
|
|
|
tp->t_dev = makedev(DCDEV, 4 * sc->sc_dv.dv_unit + line);
|
1994-06-02 10:14:56 +04:00
|
|
|
pdp->p_arg = (int) tp;
|
1993-10-12 06:22:19 +03:00
|
|
|
pdp->p_fcn = dcxint;
|
1994-06-02 10:14:56 +04:00
|
|
|
pdp++;
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
sc->dcsoftCAR = sc->sc_dv.dv_cfdata->cf_flags | 0xB;
|
1993-10-12 06:22:19 +03:00
|
|
|
|
|
|
|
if (dc_timer == 0) {
|
|
|
|
dc_timer = 1;
|
|
|
|
timeout(dcscan, (void *)0, hz);
|
|
|
|
}
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
sc->dc_19200 = speed;
|
|
|
|
sc->dc_modem = dtr_mask;
|
|
|
|
sc->dc_rtscts = rtscts_mask;
|
|
|
|
|
|
|
|
|
1993-10-12 06:22:19 +03:00
|
|
|
/*
|
|
|
|
* Special handling for consoles.
|
|
|
|
*/
|
1996-09-17 23:34:40 +04:00
|
|
|
if (sc->sc_dv.dv_unit == 0) {
|
|
|
|
if (raster_console()) {
|
1993-10-12 06:22:19 +03:00
|
|
|
s = spltty();
|
|
|
|
dcaddr->dc_lpr = LPR_RXENAB | LPR_8_BIT_CHAR |
|
|
|
|
LPR_B4800 | DCKBD_PORT;
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
dcaddr->dc_lpr = LPR_RXENAB | LPR_B4800 | LPR_OPAR |
|
|
|
|
LPR_PARENB | LPR_8_BIT_CHAR | DCMOUSE_PORT;
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(1000);
|
|
|
|
KBDReset(makedev(DCDEV, DCKBD_PORT), dcPutc);
|
|
|
|
MouseInit(makedev(DCDEV, DCMOUSE_PORT), dcPutc, dcGetc);
|
|
|
|
splx(s);
|
1996-09-26 00:48:51 +04:00
|
|
|
}
|
|
|
|
else if (major(cn_tab->cn_dev) == DCDEV) {
|
1993-10-12 06:22:19 +03:00
|
|
|
s = spltty();
|
1996-09-17 23:34:40 +04:00
|
|
|
dc_consinit(cn_tab->cn_dev, dcaddr);
|
1996-09-26 00:48:51 +04:00
|
|
|
dcaddr->dc_csr |= (CSR_MSE | CSR_TIE | CSR_RIE);
|
1996-09-17 23:34:40 +04:00
|
|
|
splx(s);
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
1996-09-26 00:48:51 +04:00
|
|
|
}
|
|
|
|
return (1);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
|
|
|
|
|
1996-09-26 00:48:51 +04:00
|
|
|
/*
|
|
|
|
* Reset chip. Does not change modem control output bits
|
|
|
|
* or modem state register.
|
|
|
|
* Does not enable interrupts; caller must explicitly or
|
|
|
|
* TIE and RIE on if desired (XXX not true yet)
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
dc_reset(dcaddr)
|
|
|
|
register dcregs *dcaddr;
|
|
|
|
{
|
|
|
|
/* Reset CSR and wait until cleared. */
|
|
|
|
dcaddr->dc_csr = CSR_CLR;
|
|
|
|
wbflush();
|
|
|
|
DELAY(10);
|
|
|
|
while (dcaddr->dc_csr & CSR_CLR)
|
|
|
|
;
|
1995-08-10 08:21:35 +04:00
|
|
|
|
1996-09-26 00:48:51 +04:00
|
|
|
/* Enable scanner. */
|
|
|
|
dcaddr->dc_csr = CSR_MSE;
|
|
|
|
wbflush();
|
|
|
|
DELAY(10);
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
|
|
|
|
1996-09-26 00:48:51 +04:00
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1993-10-12 06:22:19 +03:00
|
|
|
dcopen(dev, flag, mode, p)
|
|
|
|
dev_t dev;
|
|
|
|
int flag, mode;
|
|
|
|
struct proc *p;
|
|
|
|
{
|
|
|
|
register struct tty *tp;
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
|
|
|
register int unit, line;
|
1993-10-12 06:22:19 +03:00
|
|
|
int s, error = 0;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
unit = DCUNIT(dev);
|
|
|
|
line = DCLINE(dev);
|
|
|
|
if (unit >= dc_cd.cd_ndevs || line > 4)
|
1993-10-12 06:22:19 +03:00
|
|
|
return (ENXIO);
|
1996-09-17 23:34:40 +04:00
|
|
|
|
|
|
|
sc = dc_cd.cd_devs[unit];
|
|
|
|
if (sc->dc_pdma[line].p_addr == (void *)0)
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
tp = sc->dc_tty[line];
|
1996-06-16 20:50:56 +04:00
|
|
|
if (tp == NULL) {
|
1996-09-17 23:34:40 +04:00
|
|
|
tp = sc->dc_tty[line] = ttymalloc();
|
1996-06-16 20:50:56 +04:00
|
|
|
tty_attach(tp);
|
|
|
|
}
|
1993-10-12 06:22:19 +03:00
|
|
|
tp->t_oproc = dcstart;
|
|
|
|
tp->t_param = dcparam;
|
|
|
|
tp->t_dev = dev;
|
|
|
|
if ((tp->t_state & TS_ISOPEN) == 0) {
|
|
|
|
tp->t_state |= TS_WOPEN;
|
|
|
|
ttychars(tp);
|
|
|
|
#ifndef PORTSELECTOR
|
|
|
|
if (tp->t_ispeed == 0) {
|
|
|
|
#endif
|
|
|
|
tp->t_iflag = TTYDEF_IFLAG;
|
|
|
|
tp->t_oflag = TTYDEF_OFLAG;
|
|
|
|
tp->t_cflag = TTYDEF_CFLAG;
|
|
|
|
tp->t_lflag = LFLAG;
|
|
|
|
tp->t_ispeed = tp->t_ospeed = ISPEED;
|
|
|
|
#ifdef PORTSELECTOR
|
|
|
|
tp->t_cflag |= HUPCL;
|
|
|
|
#else
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
(void) dcparam(tp, &tp->t_termios);
|
|
|
|
ttsetwater(tp);
|
|
|
|
} else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0)
|
|
|
|
return (EBUSY);
|
1996-09-17 23:34:40 +04:00
|
|
|
#ifdef HW_FLOW_CONTROL
|
1996-09-11 10:41:19 +04:00
|
|
|
(void) dcmctl(dev, DML_DTR | DML_RTS, DMSET);
|
1996-09-17 23:34:40 +04:00
|
|
|
#else
|
|
|
|
(void) dcmctl(dev, DML_DTR, DMSET);
|
|
|
|
#endif
|
|
|
|
if ((sc->dcsoftCAR & (1 << line)) ||
|
1996-09-11 10:41:19 +04:00
|
|
|
(dcmctl(dev, 0, DMGET) & DML_CAR))
|
|
|
|
tp->t_state |= TS_CARR_ON;
|
1993-10-12 06:22:19 +03:00
|
|
|
s = spltty();
|
|
|
|
while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
|
|
|
|
!(tp->t_state & TS_CARR_ON)) {
|
|
|
|
tp->t_state |= TS_WOPEN;
|
1996-05-19 04:58:03 +04:00
|
|
|
if ((error = ttysleep(tp, (caddr_t)&tp->t_rawq,
|
|
|
|
TTIPRI | PCATCH, ttopen, 0)) != 0)
|
1993-10-12 06:22:19 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
splx(s);
|
|
|
|
if (error)
|
|
|
|
return (error);
|
|
|
|
return ((*linesw[tp->t_line].l_open)(dev, tp));
|
|
|
|
}
|
|
|
|
|
|
|
|
/*ARGSUSED*/
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1993-10-12 06:22:19 +03:00
|
|
|
dcclose(dev, flag, mode, p)
|
|
|
|
dev_t dev;
|
|
|
|
int flag, mode;
|
|
|
|
struct proc *p;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct tty *tp;
|
1996-09-17 23:34:40 +04:00
|
|
|
register int line, bit;
|
1996-09-11 10:41:19 +04:00
|
|
|
int s;
|
1993-10-12 06:22:19 +03:00
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
line = DCLINE(dev);
|
|
|
|
tp = sc->dc_tty[line];
|
|
|
|
bit = 1 << (line + 8);
|
1996-09-11 10:41:19 +04:00
|
|
|
s = spltty();
|
|
|
|
/* turn off the break bit if it is set */
|
1996-09-17 23:34:40 +04:00
|
|
|
if (sc->dc_brk & bit) {
|
|
|
|
sc->dc_brk &= ~bit;
|
1993-10-12 06:22:19 +03:00
|
|
|
ttyoutput(0, tp);
|
|
|
|
}
|
1996-09-11 10:41:19 +04:00
|
|
|
splx(s);
|
1993-10-12 06:22:19 +03:00
|
|
|
(*linesw[tp->t_line].l_close)(tp, flag);
|
|
|
|
if ((tp->t_cflag & HUPCL) || (tp->t_state & TS_WOPEN) ||
|
|
|
|
!(tp->t_state & TS_ISOPEN))
|
|
|
|
(void) dcmctl(dev, 0, DMSET);
|
|
|
|
return (ttyclose(tp));
|
|
|
|
}
|
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1993-10-12 06:22:19 +03:00
|
|
|
dcread(dev, uio, flag)
|
|
|
|
dev_t dev;
|
|
|
|
struct uio *uio;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct tty *tp;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
tp = sc->dc_tty[DCLINE(dev)];
|
|
|
|
|
|
|
|
#ifdef HW_FLOW_CONTROL
|
1996-09-11 10:41:19 +04:00
|
|
|
if ((tp->t_cflag & CRTS_IFLOW) && (tp->t_state & TS_TBLOCK) &&
|
|
|
|
tp->t_rawq.c_cc < TTYHOG/5) {
|
|
|
|
tp->t_state &= ~TS_TBLOCK;
|
|
|
|
(void) dcmctl(dev, DML_RTS, DMBIS);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif /* HW_FLOW_CONTROL */
|
|
|
|
|
1993-10-12 06:22:19 +03:00
|
|
|
return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
|
|
|
|
}
|
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1993-10-12 06:22:19 +03:00
|
|
|
dcwrite(dev, uio, flag)
|
|
|
|
dev_t dev;
|
|
|
|
struct uio *uio;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct tty *tp;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
tp = sc->dc_tty[DCLINE(dev)];
|
1993-10-12 06:22:19 +03:00
|
|
|
return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
|
|
|
|
}
|
|
|
|
|
1995-04-21 05:24:26 +04:00
|
|
|
struct tty *
|
|
|
|
dctty(dev)
|
|
|
|
dev_t dev;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
|
|
|
register struct tty *tp;
|
|
|
|
|
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
tp = sc->dc_tty[DCLINE(dev)];
|
1995-04-21 05:24:26 +04:00
|
|
|
return (tp);
|
|
|
|
}
|
|
|
|
|
1993-10-12 06:22:19 +03:00
|
|
|
/*ARGSUSED*/
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1994-05-27 12:39:00 +04:00
|
|
|
dcioctl(dev, cmd, data, flag, p)
|
1993-10-12 06:22:19 +03:00
|
|
|
dev_t dev;
|
1996-05-19 04:58:03 +04:00
|
|
|
u_long cmd;
|
1993-10-12 06:22:19 +03:00
|
|
|
caddr_t data;
|
|
|
|
int flag;
|
1994-05-27 12:39:00 +04:00
|
|
|
struct proc *p;
|
1993-10-12 06:22:19 +03:00
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct tty *tp;
|
1996-09-17 23:34:40 +04:00
|
|
|
register int unit;
|
|
|
|
register int line;
|
1993-10-12 06:22:19 +03:00
|
|
|
int error;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
|
|
|
|
unit = DCUNIT(dev);
|
|
|
|
line = DCLINE(dev);
|
|
|
|
sc = dc_cd.cd_devs[unit];
|
|
|
|
tp = sc->dc_tty[line];
|
|
|
|
|
1994-05-27 12:39:00 +04:00
|
|
|
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
|
1993-10-12 06:22:19 +03:00
|
|
|
if (error >= 0)
|
|
|
|
return (error);
|
1994-05-27 12:57:32 +04:00
|
|
|
error = ttioctl(tp, cmd, data, flag, p);
|
1993-10-12 06:22:19 +03:00
|
|
|
if (error >= 0)
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
|
|
|
|
case TIOCSBRK:
|
1996-09-17 23:34:40 +04:00
|
|
|
sc->dc_brk |= 1 << (line + 8);
|
1993-10-12 06:22:19 +03:00
|
|
|
ttyoutput(0, tp);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCCBRK:
|
1996-09-17 23:34:40 +04:00
|
|
|
sc->dc_brk &= ~(1 << (line + 8));
|
1993-10-12 06:22:19 +03:00
|
|
|
ttyoutput(0, tp);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCSDTR:
|
|
|
|
(void) dcmctl(dev, DML_DTR|DML_RTS, DMBIS);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCCDTR:
|
|
|
|
(void) dcmctl(dev, DML_DTR|DML_RTS, DMBIC);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCMSET:
|
|
|
|
(void) dcmctl(dev, *(int *)data, DMSET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCMBIS:
|
|
|
|
(void) dcmctl(dev, *(int *)data, DMBIS);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCMBIC:
|
|
|
|
(void) dcmctl(dev, *(int *)data, DMBIC);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TIOCMGET:
|
|
|
|
*(int *)data = dcmctl(dev, 0, DMGET);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return (ENOTTY);
|
|
|
|
}
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
1996-10-13 16:25:50 +04:00
|
|
|
/*
|
|
|
|
* Set line parameters
|
|
|
|
*/
|
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1993-10-12 06:22:19 +03:00
|
|
|
dcparam(tp, t)
|
|
|
|
register struct tty *tp;
|
|
|
|
register struct termios *t;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register dcregs *dcaddr;
|
1996-10-13 16:25:50 +04:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Extract softc data, and pass entire request onto
|
|
|
|
* cold_dcparam() for argument checking and execution.
|
|
|
|
*/
|
|
|
|
sc = dc_cd.cd_devs[DCUNIT(tp->t_dev)];
|
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[0].p_addr;
|
|
|
|
return (cold_dcparam(tp, t, dcaddr, sc->dc_19200));
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
cold_dcparam(tp, t, dcaddr, allow_19200)
|
|
|
|
register struct tty *tp;
|
|
|
|
register struct termios *t;
|
|
|
|
register dcregs *dcaddr;
|
|
|
|
int allow_19200;
|
|
|
|
{
|
1993-10-12 06:22:19 +03:00
|
|
|
register int lpr;
|
|
|
|
register int cflag = t->c_cflag;
|
|
|
|
int unit = minor(tp->t_dev);
|
|
|
|
int ospeed = ttspeedtab(t->c_ospeed, dcspeedtab);
|
1996-09-11 10:41:19 +04:00
|
|
|
int s;
|
1996-09-17 23:34:40 +04:00
|
|
|
int line;
|
|
|
|
|
|
|
|
line = DCLINE(tp->t_dev);
|
1993-10-12 06:22:19 +03:00
|
|
|
|
|
|
|
/* check requested parameters */
|
|
|
|
if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed) ||
|
|
|
|
(cflag & CSIZE) == CS5 || (cflag & CSIZE) == CS6 ||
|
1996-10-13 16:25:50 +04:00
|
|
|
(t->c_ospeed >= 19200 && allow_19200 != 1))
|
1993-10-12 06:22:19 +03:00
|
|
|
return (EINVAL);
|
|
|
|
/* and copy to tty */
|
|
|
|
tp->t_ispeed = t->c_ispeed;
|
|
|
|
tp->t_ospeed = t->c_ospeed;
|
|
|
|
tp->t_cflag = cflag;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Handle console cases specially.
|
|
|
|
*/
|
1995-09-12 01:29:23 +04:00
|
|
|
if (raster_console()) {
|
1993-10-12 06:22:19 +03:00
|
|
|
if (unit == DCKBD_PORT) {
|
1996-09-11 10:41:19 +04:00
|
|
|
lpr = LPR_RXENAB | LPR_8_BIT_CHAR |
|
1993-10-12 06:22:19 +03:00
|
|
|
LPR_B4800 | DCKBD_PORT;
|
1996-09-11 10:41:19 +04:00
|
|
|
goto out;
|
1993-10-12 06:22:19 +03:00
|
|
|
} else if (unit == DCMOUSE_PORT) {
|
1996-09-11 10:41:19 +04:00
|
|
|
lpr = LPR_RXENAB | LPR_B4800 | LPR_OPAR |
|
1993-10-12 06:22:19 +03:00
|
|
|
LPR_PARENB | LPR_8_BIT_CHAR | DCMOUSE_PORT;
|
1996-09-11 10:41:19 +04:00
|
|
|
goto out;
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
1995-09-12 01:29:23 +04:00
|
|
|
} else if (tp->t_dev == cn_tab->cn_dev) {
|
1996-09-17 23:34:40 +04:00
|
|
|
lpr = LPR_RXENAB | LPR_8_BIT_CHAR | LPR_B9600 | line;
|
1996-09-11 10:41:19 +04:00
|
|
|
goto out;
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
|
|
|
if (ospeed == 0) {
|
|
|
|
(void) dcmctl(unit, 0, DMSET); /* hang up line */
|
|
|
|
return (0);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
lpr = LPR_RXENAB | ospeed | line;
|
1993-10-12 06:22:19 +03:00
|
|
|
if ((cflag & CSIZE) == CS7)
|
|
|
|
lpr |= LPR_7_BIT_CHAR;
|
|
|
|
else
|
|
|
|
lpr |= LPR_8_BIT_CHAR;
|
|
|
|
if (cflag & PARENB)
|
|
|
|
lpr |= LPR_PARENB;
|
|
|
|
if (cflag & PARODD)
|
|
|
|
lpr |= LPR_OPAR;
|
|
|
|
if (cflag & CSTOPB)
|
|
|
|
lpr |= LPR_2_STOP;
|
1996-09-11 10:41:19 +04:00
|
|
|
out:
|
|
|
|
s = spltty();
|
1993-10-12 06:22:19 +03:00
|
|
|
dcaddr->dc_lpr = lpr;
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1996-09-11 10:41:19 +04:00
|
|
|
splx(s);
|
1994-05-27 12:39:00 +04:00
|
|
|
DELAY(10);
|
1993-10-12 06:22:19 +03:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
1996-10-13 16:25:50 +04:00
|
|
|
|
1993-10-12 06:22:19 +03:00
|
|
|
/*
|
|
|
|
* Check for interrupts from all devices.
|
|
|
|
*/
|
1995-09-12 01:29:23 +04:00
|
|
|
int
|
|
|
|
dcintr(xxxunit)
|
|
|
|
void *xxxunit;
|
1993-10-12 06:22:19 +03:00
|
|
|
{
|
1996-01-30 01:52:15 +03:00
|
|
|
register struct dc_softc *sc = xxxunit;
|
1993-10-12 06:22:19 +03:00
|
|
|
register dcregs *dcaddr;
|
|
|
|
register unsigned csr;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[0].p_addr;
|
1993-10-12 06:22:19 +03:00
|
|
|
while ((csr = dcaddr->dc_csr) & (CSR_RDONE | CSR_TRDY)) {
|
|
|
|
if (csr & CSR_RDONE)
|
1996-09-17 23:34:40 +04:00
|
|
|
dcrint(sc);
|
1993-10-12 06:22:19 +03:00
|
|
|
if (csr & CSR_TRDY)
|
1996-09-17 23:34:40 +04:00
|
|
|
dcxint(sc->dc_tty[((csr >> 8) & 03)]);
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
1995-09-12 01:29:23 +04:00
|
|
|
/* XXX check for spurious interrupts */
|
|
|
|
return 0;
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
void
|
1996-09-17 23:34:40 +04:00
|
|
|
dcrint(sc)
|
|
|
|
register struct dc_softc * sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
{
|
|
|
|
register dcregs *dcaddr;
|
|
|
|
register struct tty *tp;
|
|
|
|
register int c, cc;
|
|
|
|
int overrun = 0;
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct tty **dc_tty;
|
|
|
|
|
|
|
|
dc_tty = ((struct dc_softc*)dc_cd.cd_devs[0])->dc_tty; /* XXX */
|
1993-10-12 06:22:19 +03:00
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[0].p_addr; /*XXX*/
|
1993-10-12 06:22:19 +03:00
|
|
|
while ((c = dcaddr->dc_rbuf) < 0) { /* char present */
|
|
|
|
cc = c & 0xff;
|
1996-09-17 23:34:40 +04:00
|
|
|
tp = sc->dc_tty[((c >> 8) & 03)];
|
|
|
|
|
1993-10-12 06:22:19 +03:00
|
|
|
if ((c & RBUF_OERR) && overrun == 0) {
|
1996-09-17 23:34:40 +04:00
|
|
|
log(LOG_WARNING, "%s,%d: silo overflow\n",
|
|
|
|
sc->sc_dv.dv_xname,
|
1993-10-12 06:22:19 +03:00
|
|
|
(c >> 8) & 03);
|
|
|
|
overrun = 1;
|
|
|
|
}
|
|
|
|
/* the keyboard requires special translation */
|
1996-09-17 23:34:40 +04:00
|
|
|
if (raster_console() && tp == dc_tty[DCKBD_PORT]) {
|
1993-10-12 06:22:19 +03:00
|
|
|
#ifdef KADB
|
|
|
|
if (cc == LK_DO) {
|
|
|
|
spl0();
|
|
|
|
kdbpanic();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef DEBUG
|
|
|
|
debugChar = cc;
|
|
|
|
#endif
|
|
|
|
if (dcDivertXInput) {
|
|
|
|
(*dcDivertXInput)(cc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if ((cc = kbdMapChar(cc)) < 0)
|
|
|
|
return;
|
1994-05-27 12:57:32 +04:00
|
|
|
} else if (tp == dc_tty[DCMOUSE_PORT] && dcMouseButtons) {
|
1995-09-12 01:29:23 +04:00
|
|
|
mouseInput(cc);
|
1993-10-12 06:22:19 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (!(tp->t_state & TS_ISOPEN)) {
|
|
|
|
wakeup((caddr_t)&tp->t_rawq);
|
|
|
|
#ifdef PORTSELECTOR
|
|
|
|
if (!(tp->t_state & TS_WOPEN))
|
|
|
|
#endif
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (c & RBUF_FERR)
|
|
|
|
cc |= TTY_FE;
|
|
|
|
if (c & RBUF_PERR)
|
|
|
|
cc |= TTY_PE;
|
1996-09-17 23:34:40 +04:00
|
|
|
#ifdef HW_FLOW_CONTROL
|
1996-09-11 10:41:19 +04:00
|
|
|
if ((tp->t_cflag & CRTS_IFLOW) && !(tp->t_state & TS_TBLOCK) &&
|
|
|
|
tp->t_rawq.c_cc + tp->t_canq.c_cc >= TTYHOG) {
|
|
|
|
tp->t_state &= ~TS_TBLOCK;
|
|
|
|
(void) dcmctl(tp->t_dev, DML_RTS, DMBIC);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif /* HWW_FLOW_CONTROL */
|
1993-10-12 06:22:19 +03:00
|
|
|
(*linesw[tp->t_line].l_rint)(cc, tp);
|
|
|
|
}
|
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
dcxint(tp)
|
|
|
|
register struct tty *tp;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct pdma *dp;
|
|
|
|
register dcregs *dcaddr;
|
1996-09-17 23:34:40 +04:00
|
|
|
int line, linemask;
|
|
|
|
|
|
|
|
sc = dc_cd.cd_devs[DCUNIT(tp->t_dev)]; /* XXX */
|
1993-10-12 06:22:19 +03:00
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
line = DCLINE(tp->t_dev);
|
|
|
|
linemask = 1 << line;
|
|
|
|
|
|
|
|
dp = &sc->dc_pdma[line];
|
1993-10-12 06:22:19 +03:00
|
|
|
if (dp->p_mem < dp->p_end) {
|
|
|
|
dcaddr = (dcregs *)dp->p_addr;
|
1996-09-17 23:34:40 +04:00
|
|
|
|
|
|
|
#ifdef HW_FLOW_CONTROL
|
1996-09-11 10:41:19 +04:00
|
|
|
/* check for hardware flow control of output */
|
1996-09-17 23:34:40 +04:00
|
|
|
if ((tp->t_cflag & CCTS_OFLOW) && (sc->dc_rtscts & linemask)) {
|
|
|
|
switch (line) {
|
|
|
|
case 2:
|
1996-09-11 10:41:19 +04:00
|
|
|
if (dcaddr->dc_msr & MSR_CTS2)
|
|
|
|
break;
|
|
|
|
goto stop;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
case 3:
|
1996-09-11 10:41:19 +04:00
|
|
|
if (dcaddr->dc_msr & MSR_CTS3)
|
|
|
|
break;
|
|
|
|
stop:
|
|
|
|
tp->t_state &= ~TS_BUSY;
|
|
|
|
tp->t_state |= TS_TTSTOP;
|
|
|
|
ndflush(&tp->t_outq, dp->p_mem -
|
|
|
|
(caddr_t)tp->t_outq.c_cf);
|
|
|
|
dp->p_end = dp->p_mem = tp->t_outq.c_cf;
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr->dc_tcr &= ~(1 << line);
|
1996-09-11 10:41:19 +04:00
|
|
|
wbflush();
|
|
|
|
DELAY(10);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif /* HW_FLOW_CONTROL */
|
|
|
|
dcaddr->dc_tdr = sc->dc_brk | *(u_char *)dp->p_mem;
|
1996-09-11 10:41:19 +04:00
|
|
|
dp->p_mem++;
|
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
tp->t_state &= ~TS_BUSY;
|
|
|
|
if (tp->t_state & TS_FLUSH)
|
|
|
|
tp->t_state &= ~TS_FLUSH;
|
|
|
|
else {
|
1994-05-30 10:12:07 +04:00
|
|
|
ndflush(&tp->t_outq, dp->p_mem - (caddr_t) tp->t_outq.c_cf);
|
1993-10-12 06:22:19 +03:00
|
|
|
dp->p_end = dp->p_mem = tp->t_outq.c_cf;
|
|
|
|
}
|
|
|
|
if (tp->t_line)
|
|
|
|
(*linesw[tp->t_line].l_start)(tp);
|
|
|
|
else
|
|
|
|
dcstart(tp);
|
|
|
|
if (tp->t_outq.c_cc == 0 || !(tp->t_state & TS_BUSY)) {
|
1994-05-27 12:39:00 +04:00
|
|
|
dcaddr = (dcregs *)dp->p_addr;
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr->dc_tcr &= ~(1 << line);
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
dcstart(tp)
|
|
|
|
register struct tty *tp;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct pdma *dp;
|
|
|
|
register dcregs *dcaddr;
|
|
|
|
register int cc;
|
1996-09-17 23:34:40 +04:00
|
|
|
int line, s;
|
1993-10-12 06:22:19 +03:00
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
sc = dc_cd.cd_devs[DCUNIT(tp->t_dev)];
|
|
|
|
line = DCLINE(tp->t_dev);
|
|
|
|
dp = &sc->dc_pdma[line];
|
1993-10-12 06:22:19 +03:00
|
|
|
dcaddr = (dcregs *)dp->p_addr;
|
|
|
|
s = spltty();
|
|
|
|
if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
|
|
|
|
goto out;
|
|
|
|
if (tp->t_outq.c_cc <= tp->t_lowat) {
|
|
|
|
if (tp->t_state & TS_ASLEEP) {
|
|
|
|
tp->t_state &= ~TS_ASLEEP;
|
|
|
|
wakeup((caddr_t)&tp->t_outq);
|
|
|
|
}
|
|
|
|
selwakeup(&tp->t_wsel);
|
|
|
|
}
|
|
|
|
if (tp->t_outq.c_cc == 0)
|
|
|
|
goto out;
|
|
|
|
/* handle console specially */
|
1996-09-17 23:34:40 +04:00
|
|
|
if (raster_console() && tp == sc->dc_tty[DCKBD_PORT]) {
|
1993-10-12 06:22:19 +03:00
|
|
|
while (tp->t_outq.c_cc > 0) {
|
|
|
|
cc = getc(&tp->t_outq) & 0x7f;
|
|
|
|
cnputc(cc);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* After we flush the output queue we may need to wake
|
|
|
|
* up the process that made the output.
|
|
|
|
*/
|
|
|
|
if (tp->t_outq.c_cc <= tp->t_lowat) {
|
|
|
|
if (tp->t_state & TS_ASLEEP) {
|
|
|
|
tp->t_state &= ~TS_ASLEEP;
|
|
|
|
wakeup((caddr_t)&tp->t_outq);
|
|
|
|
}
|
|
|
|
selwakeup(&tp->t_wsel);
|
|
|
|
}
|
|
|
|
goto out;
|
|
|
|
}
|
1996-09-11 10:41:19 +04:00
|
|
|
cc = ndqb(&tp->t_outq, 0);
|
1996-09-17 23:34:40 +04:00
|
|
|
if (cc == 0)
|
|
|
|
goto out;
|
1993-10-12 06:22:19 +03:00
|
|
|
tp->t_state |= TS_BUSY;
|
|
|
|
dp->p_end = dp->p_mem = tp->t_outq.c_cf;
|
|
|
|
dp->p_end += cc;
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr->dc_tcr |= 1 << line;
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
out:
|
|
|
|
splx(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop output on a line.
|
|
|
|
*/
|
|
|
|
/*ARGSUSED*/
|
1996-10-13 03:41:35 +04:00
|
|
|
void
|
1993-10-12 06:22:19 +03:00
|
|
|
dcstop(tp, flag)
|
|
|
|
register struct tty *tp;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register struct pdma *dp;
|
|
|
|
register int s;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
sc = dc_cd.cd_devs[DCUNIT(tp->t_dev)];
|
|
|
|
dp = &sc->dc_pdma[DCLINE(tp->t_dev)];
|
1993-10-12 06:22:19 +03:00
|
|
|
s = spltty();
|
|
|
|
if (tp->t_state & TS_BUSY) {
|
|
|
|
dp->p_end = dp->p_mem;
|
|
|
|
if (!(tp->t_state & TS_TTSTOP))
|
|
|
|
tp->t_state |= TS_FLUSH;
|
|
|
|
}
|
|
|
|
splx(s);
|
|
|
|
}
|
|
|
|
|
1996-05-19 04:58:03 +04:00
|
|
|
int
|
1993-10-12 06:22:19 +03:00
|
|
|
dcmctl(dev, bits, how)
|
|
|
|
dev_t dev;
|
|
|
|
int bits, how;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc;
|
1993-10-12 06:22:19 +03:00
|
|
|
register dcregs *dcaddr;
|
1996-09-17 23:34:40 +04:00
|
|
|
register int line, mbits;
|
1993-10-12 06:22:19 +03:00
|
|
|
int b, s;
|
1996-09-11 10:41:19 +04:00
|
|
|
register int tcr, msr;
|
1993-10-12 06:22:19 +03:00
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
line = DCLINE(dev);
|
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
b = 1 << line;
|
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[line].p_addr;
|
1993-10-12 06:22:19 +03:00
|
|
|
s = spltty();
|
1996-09-11 10:41:19 +04:00
|
|
|
/* only channel 2 has modem control on a DECstation 2100/3100 */
|
1996-09-17 23:34:40 +04:00
|
|
|
mbits = DML_DTR | DML_DSR | DML_CAR;
|
|
|
|
#ifdef HW_FLOW_CONTROL
|
|
|
|
mbits != DML_RTS;
|
|
|
|
#endif /* HW_FLOW_CONTROL */
|
|
|
|
switch (line) {
|
|
|
|
case 2: /* pmax partial-modem comms port, full-modem port on 3max */
|
1993-10-12 06:22:19 +03:00
|
|
|
mbits = 0;
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr = dcaddr->dc_tcr;
|
|
|
|
if (tcr & TCR_DTR2)
|
1993-10-12 06:22:19 +03:00
|
|
|
mbits |= DML_DTR;
|
1996-09-17 23:34:40 +04:00
|
|
|
if ((sc->dc_rtscts & (1<<line)) && (tcr & TCR_RTS2))
|
1996-09-11 10:41:19 +04:00
|
|
|
mbits |= DML_RTS;
|
1993-10-12 06:22:19 +03:00
|
|
|
msr = dcaddr->dc_msr;
|
|
|
|
if (msr & MSR_CD2)
|
|
|
|
mbits |= DML_CAR;
|
|
|
|
if (msr & MSR_DSR2) {
|
1996-09-17 23:34:40 +04:00
|
|
|
/*
|
|
|
|
* XXX really tests for DS_PMAX instead of DS_3MAX
|
|
|
|
* but close enough for now. Vaxes?
|
|
|
|
*/
|
|
|
|
if ((sc->dc_rtscts & (1 << line )) == 0 &&
|
|
|
|
(sc->dc_modem & (1 << line )))
|
1993-10-12 06:22:19 +03:00
|
|
|
mbits |= DML_CAR | DML_DSR;
|
|
|
|
else
|
|
|
|
mbits |= DML_DSR;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
case 3: /* no modem control on pmax, console port on 3max */
|
|
|
|
/*
|
|
|
|
* XXX really tests for DS_3MAX instead of DS_PMAX
|
|
|
|
* but close enough for now. Vaxes?
|
|
|
|
*/
|
|
|
|
if ( sc->dc_modem & (1 << line )) {
|
1993-10-12 06:22:19 +03:00
|
|
|
mbits = 0;
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr = dcaddr->dc_tcr;
|
|
|
|
if (tcr & TCR_DTR3)
|
1993-10-12 06:22:19 +03:00
|
|
|
mbits |= DML_DTR;
|
1996-09-17 23:34:40 +04:00
|
|
|
#ifdef HW_FLOW_CONTROL
|
|
|
|
/* XXX OK for get, but not for set? */
|
|
|
|
/*if ( sc->dc_rtscts & (1 << line ))*/
|
1996-09-11 10:41:19 +04:00
|
|
|
if (tcr & TCR_RTS3)
|
|
|
|
mbits |= DML_RTS;
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif /*HW_FLOW_CONTROL*/
|
1993-10-12 06:22:19 +03:00
|
|
|
msr = dcaddr->dc_msr;
|
|
|
|
if (msr & MSR_CD3)
|
|
|
|
mbits |= DML_CAR;
|
|
|
|
if (msr & MSR_DSR3)
|
|
|
|
mbits |= DML_DSR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
switch (how) {
|
|
|
|
case DMSET:
|
|
|
|
mbits = bits;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMBIS:
|
|
|
|
mbits |= bits;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMBIC:
|
|
|
|
mbits &= ~bits;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DMGET:
|
|
|
|
(void) splx(s);
|
|
|
|
return (mbits);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
switch (line) {
|
|
|
|
case 2: /* 2 */
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr = dcaddr->dc_tcr;
|
1993-10-12 06:22:19 +03:00
|
|
|
if (mbits & DML_DTR)
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr |= TCR_DTR2;
|
1993-10-12 06:22:19 +03:00
|
|
|
else
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr &= ~TCR_DTR2;
|
1996-09-17 23:34:40 +04:00
|
|
|
/*if (pmax_boardtype != DS_PMAX)*/
|
|
|
|
if (sc->dc_rtscts & (1 << line)) {
|
1996-09-11 10:41:19 +04:00
|
|
|
if (mbits & DML_RTS)
|
|
|
|
tcr |= TCR_RTS2;
|
|
|
|
else
|
|
|
|
tcr &= ~TCR_RTS2;
|
|
|
|
}
|
|
|
|
dcaddr->dc_tcr = tcr;
|
1993-10-12 06:22:19 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 3:
|
1996-09-17 23:34:40 +04:00
|
|
|
/* XXX DTR not supported on this line on 2100/3100 */
|
|
|
|
/*if (pmax_boardtype != DS_PMAX)*/
|
|
|
|
if (sc->dc_modem & (1 << line)) {
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr = dcaddr->dc_tcr;
|
1993-10-12 06:22:19 +03:00
|
|
|
if (mbits & DML_DTR)
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr |= TCR_DTR3;
|
1993-10-12 06:22:19 +03:00
|
|
|
else
|
1996-09-11 10:41:19 +04:00
|
|
|
tcr &= ~TCR_DTR3;
|
1996-09-17 23:34:40 +04:00
|
|
|
#ifdef HW_FLOW_CONTROL
|
|
|
|
/*if (sc->dc_rtscts & (1 << line))*/
|
1996-09-11 10:41:19 +04:00
|
|
|
if (mbits & DML_RTS)
|
|
|
|
tcr |= TCR_RTS3;
|
|
|
|
else
|
|
|
|
tcr &= ~TCR_RTS3;
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif /* HW_FLOW_CONTROL */
|
1996-09-11 10:41:19 +04:00
|
|
|
dcaddr->dc_tcr = tcr;
|
1993-10-12 06:22:19 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
(void) splx(s);
|
|
|
|
return (mbits);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called by timeout() periodically.
|
|
|
|
* Check to see if modem status bits have changed.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
dcscan(arg)
|
|
|
|
void *arg;
|
|
|
|
{
|
1996-09-17 23:34:40 +04:00
|
|
|
register struct dc_softc *sc = dc_cd.cd_devs[0]; /* XXX */
|
1993-10-12 06:22:19 +03:00
|
|
|
register dcregs *dcaddr;
|
|
|
|
register struct tty *tp;
|
1996-09-11 10:41:19 +04:00
|
|
|
register int unit, limit, dtr, dsr;
|
1993-10-12 06:22:19 +03:00
|
|
|
int s;
|
|
|
|
|
1996-09-11 10:41:19 +04:00
|
|
|
/* only channel 2 has modem control on a DECstation 2100/3100 */
|
|
|
|
dtr = TCR_DTR2;
|
|
|
|
dsr = MSR_DSR2;
|
1996-09-17 23:34:40 +04:00
|
|
|
#ifdef HW_FLOW_CONTROL
|
1996-09-26 00:48:51 +04:00
|
|
|
/*limit = (pmax_boardtype == DS_PMAX) ? 2 : 3;*/
|
|
|
|
limit = (sc->dc_rtscts & (1 << 3)) :3 : 2; /*XXX*/
|
1996-09-17 23:34:40 +04:00
|
|
|
#else
|
|
|
|
limit = 2;
|
|
|
|
#endif
|
1993-10-12 06:22:19 +03:00
|
|
|
s = spltty();
|
1996-09-11 10:41:19 +04:00
|
|
|
for (unit = 2; unit <= limit; unit++, dtr >>= 2, dsr >>= 8) {
|
1996-09-17 23:34:40 +04:00
|
|
|
tp = sc->dc_tty[unit];
|
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[unit].p_addr;
|
|
|
|
if ((dcaddr->dc_msr & dsr) || (sc->dcsoftCAR & (1 << unit))) {
|
1996-09-11 10:41:19 +04:00
|
|
|
/* carrier present */
|
|
|
|
if (!(tp->t_state & TS_CARR_ON))
|
|
|
|
(void)(*linesw[tp->t_line].l_modem)(tp, 1);
|
|
|
|
} else if ((tp->t_state & TS_CARR_ON) &&
|
|
|
|
(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
|
|
|
|
dcaddr->dc_tcr &= ~dtr;
|
1996-09-17 23:34:40 +04:00
|
|
|
#ifdef HW_FLOW_CONTROL
|
1996-09-11 10:41:19 +04:00
|
|
|
/*
|
|
|
|
* If we are using hardware flow control and output is stopped,
|
|
|
|
* then resume transmit.
|
|
|
|
*/
|
|
|
|
if ((tp->t_cflag & CCTS_OFLOW) && (tp->t_state & TS_TTSTOP) &&
|
1996-09-17 23:34:40 +04:00
|
|
|
/*pmax_boardtype != DS_PMAX*/
|
|
|
|
(sc->dc_rtscts & (1 << unit)) ) {
|
1996-09-11 10:41:19 +04:00
|
|
|
switch (unit) {
|
1996-09-17 23:34:40 +04:00
|
|
|
case 2:
|
1996-09-11 10:41:19 +04:00
|
|
|
if (dcaddr->dc_msr & MSR_CTS2)
|
|
|
|
break;
|
|
|
|
continue;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
case 3:
|
1996-09-11 10:41:19 +04:00
|
|
|
if (dcaddr->dc_msr & MSR_CTS3)
|
|
|
|
break;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
tp->t_state &= ~TS_TTSTOP;
|
|
|
|
dcstart(tp);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif /* HW_FLOW_CONTROL */
|
1996-09-11 10:41:19 +04:00
|
|
|
}
|
1993-10-12 06:22:19 +03:00
|
|
|
splx(s);
|
|
|
|
timeout(dcscan, (void *)0, hz);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ----------------------------------------------------------------------------
|
|
|
|
*
|
|
|
|
* dcGetc --
|
|
|
|
*
|
|
|
|
* Read a character from a serial line.
|
|
|
|
*
|
|
|
|
* Results:
|
|
|
|
* A character read from the serial port.
|
|
|
|
*
|
|
|
|
* Side effects:
|
|
|
|
* None.
|
|
|
|
*
|
|
|
|
* ----------------------------------------------------------------------------
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
dcGetc(dev)
|
|
|
|
dev_t dev;
|
|
|
|
{
|
|
|
|
register dcregs *dcaddr;
|
|
|
|
register int c;
|
1996-09-17 23:34:40 +04:00
|
|
|
register int line;
|
1993-10-12 06:22:19 +03:00
|
|
|
int s;
|
|
|
|
|
1996-09-17 23:34:40 +04:00
|
|
|
line = DCLINE(dev);
|
1996-10-16 06:10:33 +04:00
|
|
|
if (cold && dc_cons_addr) {
|
1996-09-26 00:48:51 +04:00
|
|
|
dcaddr = dc_cons_addr;
|
|
|
|
} else {
|
|
|
|
struct dc_softc *sc;
|
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[line].p_addr;
|
|
|
|
}
|
1993-10-12 06:22:19 +03:00
|
|
|
if (!dcaddr)
|
|
|
|
return (0);
|
|
|
|
s = spltty();
|
|
|
|
for (;;) {
|
|
|
|
if (!(dcaddr->dc_csr & CSR_RDONE))
|
|
|
|
continue;
|
|
|
|
c = dcaddr->dc_rbuf;
|
|
|
|
DELAY(10);
|
1996-09-17 23:34:40 +04:00
|
|
|
if (((c >> 8) & 03) == line)
|
1993-10-12 06:22:19 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
splx(s);
|
|
|
|
return (c & 0xff);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Send a char on a port, non interrupt driven.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
dcPutc(dev, c)
|
|
|
|
dev_t dev;
|
|
|
|
int c;
|
|
|
|
{
|
|
|
|
register dcregs *dcaddr;
|
|
|
|
register u_short tcr;
|
|
|
|
register int timeout;
|
1996-09-17 23:34:40 +04:00
|
|
|
int s, out_line, activeline;
|
1996-09-26 00:48:51 +04:00
|
|
|
int brk;
|
1993-10-12 06:22:19 +03:00
|
|
|
|
|
|
|
s = spltty();
|
1996-09-17 23:34:40 +04:00
|
|
|
out_line = DCLINE(dev);
|
1996-10-16 06:10:33 +04:00
|
|
|
if (cold && dc_cons_addr) {
|
1996-09-26 00:48:51 +04:00
|
|
|
brk = 0;
|
|
|
|
dcaddr = dc_cons_addr;
|
|
|
|
} else {
|
|
|
|
struct dc_softc *sc;
|
|
|
|
|
|
|
|
sc = dc_cd.cd_devs[DCUNIT(dev)];
|
|
|
|
dcaddr = (dcregs *)sc->dc_pdma[out_line].p_addr;
|
|
|
|
brk = sc->dc_brk;
|
|
|
|
}
|
1993-10-12 06:22:19 +03:00
|
|
|
tcr = dcaddr->dc_tcr;
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr->dc_tcr = tcr | (1 << out_line);
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
while (1) {
|
|
|
|
/*
|
|
|
|
* Wait for transmitter to be not busy.
|
|
|
|
*/
|
|
|
|
timeout = 1000000;
|
|
|
|
while (!(dcaddr->dc_csr & CSR_TRDY) && timeout > 0)
|
|
|
|
timeout--;
|
|
|
|
if (timeout == 0) {
|
1996-10-13 07:39:27 +04:00
|
|
|
printf("dcPutc: timeout waiting for CSR_TRDY\n");
|
1993-10-12 06:22:19 +03:00
|
|
|
break;
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
activeline = (dcaddr->dc_csr >> 8) & 3;
|
1993-10-12 06:22:19 +03:00
|
|
|
/*
|
|
|
|
* Check to be sure its the right port.
|
|
|
|
*/
|
1996-09-17 23:34:40 +04:00
|
|
|
if (activeline != out_line) {
|
|
|
|
tcr |= 1 << activeline;
|
|
|
|
dcaddr->dc_tcr &= ~(1 << out_line);
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Start sending the character.
|
|
|
|
*/
|
1996-09-26 00:48:51 +04:00
|
|
|
dcaddr->dc_tdr = brk | (c & 0xff);
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
/*
|
|
|
|
* Wait for character to be sent.
|
|
|
|
*/
|
|
|
|
while (1) {
|
|
|
|
/*
|
|
|
|
* cc -O bug: this code produces and infinite loop!
|
|
|
|
* while (!(dcaddr->dc_csr & CSR_TRDY))
|
|
|
|
* ;
|
|
|
|
*/
|
|
|
|
timeout = 1000000;
|
|
|
|
while (!(dcaddr->dc_csr & CSR_TRDY) && timeout > 0)
|
|
|
|
timeout--;
|
1996-09-17 23:34:40 +04:00
|
|
|
activeline = (dcaddr->dc_csr >> 8) & 3;
|
|
|
|
if (activeline != out_line) {
|
|
|
|
tcr |= 1 << activeline;
|
|
|
|
dcaddr->dc_tcr &= ~(1 << activeline);
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
continue;
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
dcaddr->dc_tcr &= ~(1 << out_line);
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Enable interrupts for other lines which became ready.
|
|
|
|
*/
|
|
|
|
if (tcr & 0xF) {
|
|
|
|
dcaddr->dc_tcr = tcr;
|
1996-05-19 04:58:03 +04:00
|
|
|
wbflush();
|
1993-10-12 06:22:19 +03:00
|
|
|
DELAY(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
splx(s);
|
|
|
|
}
|
1996-09-17 23:34:40 +04:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable/disable polling mode
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
dcPollc(dev, on)
|
|
|
|
dev_t dev;
|
|
|
|
int on;
|
|
|
|
{
|
|
|
|
#if defined(DIAGNOSTIC) || defined(DEBUG)
|
1996-10-13 07:39:27 +04:00
|
|
|
printf("dc_Pollc(%d, %d): not implemented\n", minor(dev), on);
|
1996-09-17 23:34:40 +04:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|