Merge in 4.4BSD-Lite -> 4.4BSD-Lite2 changes. (untested).
The Lite2 changes include:
* Remove the last vestiges of high-bit-set-means-delay for output chars.
* Handle the 2100/3100 having partial modem control on line 2 only,
whereas the 5000/200 has modem control signals on lines 2 and 3.
* Add RTS/CTS support for lines 2 and 3 on a 5000/200.
* Add more s = spltty(); splx(s); where needed but not present.
This commit is contained in:
jonathan
parent
5d76f7cbac
commit
2bc8c4e5c2
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@ -1,4 +1,4 @@
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/* $NetBSD: dc.c,v 1.21 1996/09/02 06:44:00 mycroft Exp $ */
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/* $NetBSD: dc.c,v 1.22 1996/09/11 06:41:19 jonathan Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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@ -35,7 +35,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dc.c 8.2 (Berkeley) 11/30/93
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* @(#)dc.c 8.5 (Berkeley) 6/2/95
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*/
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/*
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@ -421,7 +421,10 @@ dcopen(dev, flag, mode, p)
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ttsetwater(tp);
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} else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0)
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return (EBUSY);
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(void) dcmctl(dev, DML_DTR, DMSET);
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(void) dcmctl(dev, DML_DTR | DML_RTS, DMSET);
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if ((dcsoftCAR[unit >> 2] & (1 << (unit & 03))) ||
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(dcmctl(dev, 0, DMGET) & DML_CAR))
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tp->t_state |= TS_CARR_ON;
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s = spltty();
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while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
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!(tp->t_state & TS_CARR_ON)) {
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@ -445,14 +448,18 @@ dcclose(dev, flag, mode, p)
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{
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register struct tty *tp;
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register int unit, bit;
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int s;
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unit = minor(dev);
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tp = dc_tty[unit];
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bit = 1 << ((unit & 03) + 8);
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s = spltty();
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/* turn off the break bit if it is set */
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if (dc_brk[unit >> 2] & bit) {
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dc_brk[unit >> 2] &= ~bit;
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ttyoutput(0, tp);
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}
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splx(s);
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(*linesw[tp->t_line].l_close)(tp, flag);
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if ((tp->t_cflag & HUPCL) || (tp->t_state & TS_WOPEN) ||
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!(tp->t_state & TS_ISOPEN))
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@ -468,6 +475,11 @@ dcread(dev, uio, flag)
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register struct tty *tp;
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tp = dc_tty[minor(dev)];
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if ((tp->t_cflag & CRTS_IFLOW) && (tp->t_state & TS_TBLOCK) &&
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tp->t_rawq.c_cc < TTYHOG/5) {
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tp->t_state &= ~TS_TBLOCK;
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(void) dcmctl(dev, DML_RTS, DMBIS);
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}
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return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
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}
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@ -564,6 +576,7 @@ dcparam(tp, t)
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register int cflag = t->c_cflag;
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int unit = minor(tp->t_dev);
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int ospeed = ttspeedtab(t->c_ospeed, dcspeedtab);
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int s;
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/* check requested parameters */
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if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed) ||
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@ -575,28 +588,22 @@ dcparam(tp, t)
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tp->t_ospeed = t->c_ospeed;
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tp->t_cflag = cflag;
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dcaddr = (dcregs *)dcpdma[unit].p_addr;
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/*
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* Handle console cases specially.
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*/
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if (raster_console()) {
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if (unit == DCKBD_PORT) {
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dcaddr->dc_lpr = LPR_RXENAB | LPR_8_BIT_CHAR |
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lpr = LPR_RXENAB | LPR_8_BIT_CHAR |
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LPR_B4800 | DCKBD_PORT;
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wbflush();
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return (0);
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goto out;
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} else if (unit == DCMOUSE_PORT) {
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dcaddr->dc_lpr = LPR_RXENAB | LPR_B4800 | LPR_OPAR |
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lpr = LPR_RXENAB | LPR_B4800 | LPR_OPAR |
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LPR_PARENB | LPR_8_BIT_CHAR | DCMOUSE_PORT;
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wbflush();
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return (0);
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goto out;
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}
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} else if (tp->t_dev == cn_tab->cn_dev) {
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dcaddr->dc_lpr = LPR_RXENAB | LPR_8_BIT_CHAR |
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LPR_B9600 | unit;
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wbflush();
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return (0);
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lpr = LPR_RXENAB | LPR_8_BIT_CHAR | LPR_B9600 | unit;
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goto out;
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}
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if (ospeed == 0) {
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(void) dcmctl(unit, 0, DMSET); /* hang up line */
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@ -613,8 +620,12 @@ dcparam(tp, t)
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lpr |= LPR_OPAR;
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if (cflag & CSTOPB)
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lpr |= LPR_2_STOP;
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out:
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dcaddr = (dcregs *)dcpdma[unit].p_addr;
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s = spltty();
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dcaddr->dc_lpr = lpr;
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wbflush();
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splx(s);
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DELAY(10);
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return (0);
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}
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@ -695,6 +706,11 @@ dcrint(unit)
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cc |= TTY_FE;
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if (c & RBUF_PERR)
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cc |= TTY_PE;
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if ((tp->t_cflag & CRTS_IFLOW) && !(tp->t_state & TS_TBLOCK) &&
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tp->t_rawq.c_cc + tp->t_canq.c_cc >= TTYHOG) {
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tp->t_state &= ~TS_TBLOCK;
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(void) dcmctl(tp->t_dev, DML_RTS, DMBIC);
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}
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(*linesw[tp->t_line].l_rint)(cc, tp);
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}
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DELAY(10);
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@ -706,12 +722,38 @@ dcxint(tp)
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{
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register struct pdma *dp;
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register dcregs *dcaddr;
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int unit = minor(tp->t_dev);
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int unit;
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unit = minor(tp->t_dev);
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dp = &dcpdma[unit];
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if (dp->p_mem < dp->p_end) {
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dcaddr = (dcregs *)dp->p_addr;
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dcaddr->dc_tdr = dc_brk[unit >> 2] | *dp->p_mem++;
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/* check for hardware flow control of output */
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if ((tp->t_cflag & CCTS_OFLOW) && pmax_boardtype != DS_PMAX) {
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switch (unit) {
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case DCCOMM_PORT:
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if (dcaddr->dc_msr & MSR_CTS2)
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break;
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goto stop;
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case DCPRINTER_PORT:
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if (dcaddr->dc_msr & MSR_CTS3)
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break;
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stop:
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tp->t_state &= ~TS_BUSY;
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tp->t_state |= TS_TTSTOP;
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ndflush(&tp->t_outq, dp->p_mem -
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(caddr_t)tp->t_outq.c_cf);
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dp->p_end = dp->p_mem = tp->t_outq.c_cf;
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dcaddr->dc_tcr &= ~(1 << unit);
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wbflush();
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DELAY(10);
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return;
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}
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}
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dcaddr->dc_tdr = dc_brk[unit >> 2] | *(u_char *)dp->p_mem;
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dp->p_mem++;
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wbflush();
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DELAY(10);
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return;
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@ -742,9 +784,9 @@ dcstart(tp)
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register struct pdma *dp;
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register dcregs *dcaddr;
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register int cc;
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int s;
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int unit, s;
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dp = &dcpdma[minor(tp->t_dev)];
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dp = &dcpdma[unit = minor(tp->t_dev)];
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dcaddr = (dcregs *)dp->p_addr;
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s = spltty();
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if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
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@ -777,14 +819,11 @@ dcstart(tp)
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}
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goto out;
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}
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cc = ndqb(&tp->t_outq, 0);
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if (cc == 0)
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goto out;
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cc = ndqb(&tp->t_outq, 0);
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tp->t_state |= TS_BUSY;
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dp->p_end = dp->p_mem = tp->t_outq.c_cf;
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dp->p_end += cc;
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dcaddr->dc_tcr |= 1 << (minor(tp->t_dev) & 03);
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dcaddr->dc_tcr |= 1 << (unit & 03);
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wbflush();
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out:
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splx(s);
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@ -819,19 +858,22 @@ dcmctl(dev, bits, how)
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register dcregs *dcaddr;
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register int unit, mbits;
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int b, s;
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register int msr;
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register int tcr, msr;
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unit = minor(dev);
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b = 1 << (unit & 03);
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dcaddr = (dcregs *)dcpdma[unit].p_addr;
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s = spltty();
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/* only channel 2 has modem control (what about line 3?) */
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mbits = DML_DTR | DML_DSR | DML_CAR;
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/* only channel 2 has modem control on a DECstation 2100/3100 */
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mbits = DML_DTR | DML_RTS | DML_DSR | DML_CAR;
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switch (unit & 03) {
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case 2:
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mbits = 0;
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if (dcaddr->dc_tcr & TCR_DTR2)
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tcr = dcaddr->dc_tcr;
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if (tcr & TCR_DTR2)
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mbits |= DML_DTR;
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if (pmax_boardtype != DS_PMAX && (tcr & TCR_RTS2))
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mbits |= DML_RTS;
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msr = dcaddr->dc_msr;
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if (msr & MSR_CD2)
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mbits |= DML_CAR;
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case 3:
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if (pmax_boardtype != DS_PMAX) {
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mbits = 0;
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if (dcaddr->dc_tcr & TCR_DTR3)
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tcr = dcaddr->dc_tcr;
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if (tcr & TCR_DTR3)
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mbits |= DML_DTR;
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if (tcr & TCR_RTS3)
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mbits |= DML_RTS;
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msr = dcaddr->dc_msr;
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if (msr & MSR_CD3)
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mbits |= DML_CAR;
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@ -874,22 +919,34 @@ dcmctl(dev, bits, how)
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}
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switch (unit & 03) {
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case 2:
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tcr = dcaddr->dc_tcr;
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if (mbits & DML_DTR)
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dcaddr->dc_tcr |= TCR_DTR2;
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tcr |= TCR_DTR2;
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else
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dcaddr->dc_tcr &= ~TCR_DTR2;
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tcr &= ~TCR_DTR2;
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if (pmax_boardtype != DS_PMAX) {
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if (mbits & DML_RTS)
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tcr |= TCR_RTS2;
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else
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tcr &= ~TCR_RTS2;
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}
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dcaddr->dc_tcr = tcr;
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break;
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case 3:
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if (pmax_boardtype != DS_PMAX) {
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tcr = dcaddr->dc_tcr;
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if (mbits & DML_DTR)
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dcaddr->dc_tcr |= TCR_DTR3;
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tcr |= TCR_DTR3;
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else
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dcaddr->dc_tcr &= ~TCR_DTR3;
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tcr &= ~TCR_DTR3;
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if (mbits & DML_RTS)
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tcr |= TCR_RTS3;
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else
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tcr &= ~TCR_RTS3;
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dcaddr->dc_tcr = tcr;
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}
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}
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if ((mbits & DML_DTR) && (dcsoftCAR[unit >> 2] & b))
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dc_tty[unit]->t_state |= TS_CARR_ON;
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(void) splx(s);
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return (mbits);
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}
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@ -904,25 +961,45 @@ dcscan(arg)
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{
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register dcregs *dcaddr;
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register struct tty *tp;
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register int i, bit, car;
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register int unit, limit, dtr, dsr;
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int s;
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/* only channel 2 has modem control on a DECstation 2100/3100 */
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dtr = TCR_DTR2;
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dsr = MSR_DSR2;
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limit = (pmax_boardtype == DS_PMAX) ? 2 : 3;
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s = spltty();
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/* only channel 2 has modem control (what about line 3?) */
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dcaddr = (dcregs *)dcpdma[i = 2].p_addr;
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tp = dc_tty[i];
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bit = TCR_DTR2;
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if (dcsoftCAR[i >> 2] & bit)
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car = 1;
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else
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car = dcaddr->dc_msr & MSR_DSR2;
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if (car) {
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/* carrier present */
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if (!(tp->t_state & TS_CARR_ON))
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(void)(*linesw[tp->t_line].l_modem)(tp, 1);
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} else if ((tp->t_state & TS_CARR_ON) &&
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(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
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dcaddr->dc_tcr &= ~bit;
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for (unit = 2; unit <= limit; unit++, dtr >>= 2, dsr >>= 8) {
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tp = dc_tty[unit];
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dcaddr = (dcregs *)dcpdma[unit].p_addr;
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if ((dcaddr->dc_msr & dsr) || (dcsoftCAR[0] & (1 << unit))) {
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/* carrier present */
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if (!(tp->t_state & TS_CARR_ON))
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(void)(*linesw[tp->t_line].l_modem)(tp, 1);
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} else if ((tp->t_state & TS_CARR_ON) &&
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(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
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dcaddr->dc_tcr &= ~dtr;
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/*
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* If we are using hardware flow control and output is stopped,
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* then resume transmit.
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*/
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if ((tp->t_cflag & CCTS_OFLOW) && (tp->t_state & TS_TTSTOP) &&
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pmax_boardtype != DS_PMAX) {
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switch (unit) {
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case DCCOMM_PORT:
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if (dcaddr->dc_msr & MSR_CTS2)
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break;
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continue;
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case DCPRINTER_PORT:
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if (dcaddr->dc_msr & MSR_CTS3)
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break;
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continue;
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}
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tp->t_state &= ~TS_TTSTOP;
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dcstart(tp);
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}
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}
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splx(s);
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timeout(dcscan, (void *)0, hz);
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}
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