2020-08-21 23:46:03 +03:00
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/* $NetBSD: xhcivar.h,v 1.17 2020/08/21 20:46:03 jakllsch Exp $ */
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2013-09-14 04:40:31 +04:00
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/*
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* Copyright (c) 2013 Jonathan A. Kollasch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_USB_XHCIVAR_H_
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#define _DEV_USB_XHCIVAR_H_
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#include <sys/pool.h>
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2020-04-02 14:37:23 +03:00
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#define XHCI_MAX_DCI 31
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2016-04-23 13:15:27 +03:00
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2019-01-07 06:00:39 +03:00
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struct xhci_soft_trb {
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uint64_t trb_0;
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uint32_t trb_2;
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uint32_t trb_3;
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};
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2013-09-14 04:40:31 +04:00
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struct xhci_xfer {
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struct usbd_xfer xx_xfer;
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2020-05-21 16:47:10 +03:00
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struct xhci_soft_trb *xx_trb;
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u_int xx_ntrb;
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2020-08-21 23:46:03 +03:00
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u_int xx_isoc_done;
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2013-09-14 04:40:31 +04:00
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};
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2016-04-23 13:15:27 +03:00
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#define XHCI_BUS2SC(bus) ((bus)->ub_hcpriv)
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#define XHCI_PIPE2SC(pipe) XHCI_BUS2SC((pipe)->up_dev->ud_bus)
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#define XHCI_XFER2SC(xfer) XHCI_BUS2SC((xfer)->ux_bus)
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2017-01-19 19:05:00 +03:00
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#define XHCI_XFER2BUS(xfer) ((xfer)->ux_bus)
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2016-04-23 13:15:27 +03:00
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#define XHCI_XPIPE2SC(d) XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus)
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#define XHCI_XFER2XXFER(xfer) ((struct xhci_xfer *)(xfer))
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2013-09-14 04:40:31 +04:00
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struct xhci_ring {
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usb_dma_t xr_dma;
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kmutex_t xr_lock;
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struct xhci_trb * xr_trb;
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void **xr_cookies;
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u_int xr_ntrb; /* number of elements for above */
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u_int xr_ep; /* enqueue pointer */
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u_int xr_cs; /* cycle state */
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bool is_halted;
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};
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struct xhci_slot {
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usb_dma_t xs_dc_dma; /* device context page */
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usb_dma_t xs_ic_dma; /* input context page */
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2020-04-02 14:37:23 +03:00
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struct xhci_ring *xs_xr[XHCI_MAX_DCI + 1];
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2020-04-02 14:52:41 +03:00
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/* transfer rings */
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2013-09-14 04:40:31 +04:00
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u_int xs_idx; /* slot index */
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};
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struct xhci_softc {
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device_t sc_dev;
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device_t sc_child;
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2017-01-19 19:05:00 +03:00
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device_t sc_child2;
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2013-09-14 04:40:31 +04:00
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bus_size_t sc_ios;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh; /* Base */
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bus_space_handle_t sc_cbh; /* Capability Base */
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bus_space_handle_t sc_obh; /* Operational Base */
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bus_space_handle_t sc_rbh; /* Runtime Base */
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bus_space_handle_t sc_dbh; /* Doorbell Registers */
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2017-01-19 19:05:00 +03:00
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struct usbd_bus sc_bus; /* USB 3 bus */
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struct usbd_bus sc_bus2; /* USB 2 bus */
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2013-09-14 04:40:31 +04:00
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kmutex_t sc_lock;
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kmutex_t sc_intr_lock;
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pool_cache_t sc_xferpool;
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bus_size_t sc_pgsz; /* xHCI page size */
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uint32_t sc_ctxsz;
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int sc_maxslots;
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int sc_maxintrs;
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2013-10-28 21:49:33 +04:00
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int sc_maxspbuf;
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2013-09-14 04:40:31 +04:00
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2017-01-19 19:05:00 +03:00
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/*
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* Port routing and root hub - xHCI 4.19.7
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*/
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int sc_maxports; /* number of controller ports */
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uint8_t *sc_ctlrportbus; /* a bus bit per port */
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int *sc_ctlrportmap;
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int *sc_rhportmap[2];
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int sc_rhportcount[2];
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struct usbd_xfer *sc_intrxfer[2];
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2013-09-14 04:40:31 +04:00
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struct xhci_slot * sc_slots;
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2020-04-02 14:37:23 +03:00
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struct xhci_ring *sc_cr; /* command ring */
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struct xhci_ring *sc_er; /* event ring */
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2013-09-14 04:40:31 +04:00
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usb_dma_t sc_eventst_dma;
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usb_dma_t sc_dcbaa_dma;
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2013-10-28 21:49:33 +04:00
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usb_dma_t sc_spbufarray_dma;
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usb_dma_t *sc_spbuf_dma;
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2013-09-14 04:40:31 +04:00
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2017-01-19 19:05:00 +03:00
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kcondvar_t sc_cmdbusy_cv;
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2013-09-14 04:40:31 +04:00
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kcondvar_t sc_command_cv;
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bus_addr_t sc_command_addr;
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2019-01-07 06:00:39 +03:00
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struct xhci_soft_trb sc_result_trb;
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2017-01-19 19:05:00 +03:00
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bool sc_resultpending;
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2013-09-14 04:40:31 +04:00
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bool sc_dying;
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2016-04-23 13:15:27 +03:00
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void (*sc_vendor_init)(struct xhci_softc *);
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int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
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int sc_quirks;
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2016-05-03 16:14:44 +03:00
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#define XHCI_QUIRK_INTEL __BIT(0) /* Intel xhci chip */
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2017-09-25 03:03:10 +03:00
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#define XHCI_DEFERRED_START __BIT(1)
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2020-08-21 23:16:39 +03:00
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uint32_t sc_hcc; /* copy of HCCPARAMS1 */
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uint32_t sc_hcc2; /* copy of HCCPARAMS2 */
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2013-09-14 04:40:31 +04:00
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};
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2014-03-10 17:12:02 +04:00
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int xhci_init(struct xhci_softc *);
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2017-09-25 03:03:10 +03:00
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void xhci_start(struct xhci_softc *);
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2014-03-10 17:12:02 +04:00
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int xhci_intr(void *);
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int xhci_detach(struct xhci_softc *, int);
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int xhci_activate(device_t, enum devact);
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void xhci_childdet(device_t, device_t);
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bool xhci_suspend(device_t, const pmf_qual_t *);
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bool xhci_resume(device_t, const pmf_qual_t *);
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bool xhci_shutdown(device_t, int);
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2013-09-14 04:40:31 +04:00
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#define XHCI_TRANSFER_RING_TRBS 256
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#endif /* _DEV_USB_XHCIVAR_H_ */
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