Add work-in-progress xhci(4) driver code. Currently (mostly) supports
interrupt-driven control, interrupt and bulk transfers at the three USB 2.0 speeds on root hub ports.
This commit is contained in:
jakllsch
parent
f6ecf6bbf1
commit
fd0968d755
230
sys/dev/pci/xhci_pci.c
Normal file
230
sys/dev/pci/xhci_pci.c
Normal file
@ -0,0 +1,230 @@
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/* $NetBSD: xhci_pci.c,v 1.1 2013/09/14 00:40:31 jakllsch Exp $ */
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/*
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net) at
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* Carlstedt Research & Technology.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.1 2013/09/14 00:40:31 jakllsch Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/proc.h>
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#include <sys/queue.h>
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#include <sys/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usbdivar.h>
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#include <dev/usb/usb_mem.h>
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#include <dev/usb/xhcireg.h>
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#include <dev/usb/xhcivar.h>
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struct xhci_pci_softc {
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struct xhci_softc sc_xhci;
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_tag;
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};
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static int
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xhci_pci_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = (struct pci_attach_args *) aux;
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
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PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI)
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return 1;
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return 0;
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}
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static void
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xhci_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct xhci_pci_softc * const psc = device_private(self);
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struct xhci_softc * const sc = &psc->sc_xhci;
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struct pci_attach_args *const pa = (struct pci_attach_args *)aux;
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const pci_chipset_tag_t pc = pa->pa_pc;
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const pcitag_t tag = pa->pa_tag;
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char const *intrstr;
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pci_intr_handle_t ih;
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pcireg_t csr, memtype;
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usbd_status r;
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//const char *vendor;
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uint32_t hccparams;
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sc->sc_dev = self;
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sc->sc_bus.hci_private = sc;
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pci_aprint_devinfo(pa, "USB Controller");
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/* check if memory space access is enabled */
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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#ifdef DEBUG
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printf("csr: %08x\n", csr);
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#endif
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if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) {
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aprint_error_dev(self, "memory access is disabled\n");
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return;
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}
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/* map MMIO registers */
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memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM);
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switch (memtype) {
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
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case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
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if (pci_mapreg_map(pa, PCI_CBMEM, memtype, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios)) {
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sc->sc_ios = 0;
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aprint_error_dev(self, "can't map mem space\n");
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return;
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}
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break;
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default:
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aprint_error_dev(self, "BAR not 64 or 32-bit MMIO\n");
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return;
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break;
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}
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psc->sc_pc = pc;
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psc->sc_tag = tag;
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hccparams = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x10);
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if (pci_dma64_available(pa) && ((hccparams&1)==1))
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sc->sc_bus.dmatag = pa->pa_dmat64;
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else
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sc->sc_bus.dmatag = pa->pa_dmat;
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/* Enable the device. */
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
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csr | PCI_COMMAND_MASTER_ENABLE);
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/* Map and establish the interrupt. */
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if (pci_intr_map(pa, &ih)) {
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aprint_error_dev(self, "couldn't map interrupt\n");
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goto fail;
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}
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/*
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* Allocate IRQ
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*/
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intrstr = pci_intr_string(pc, ih);
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sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, xhci_intr, sc);
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if (sc->sc_ih == NULL) {
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aprint_error_dev(self, "couldn't establish interrupt");
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if (intrstr != NULL)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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goto fail;
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}
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aprint_normal_dev(self, "interrupting at %s\n", intrstr);
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#if 0
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/* Figure out vendor for root hub descriptor. */
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vendor = pci_findvendor(pa->pa_id);
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sc->sc_id_vendor = PCI_VENDOR(pa->pa_id);
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if (vendor)
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strlcpy(sc->sc_vendor, vendor, sizeof(sc->sc_vendor));
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else
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snprintf(sc->sc_vendor, sizeof(sc->sc_vendor),
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"vendor 0x%04x", PCI_VENDOR(pa->pa_id));
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#endif
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r = xhci_init(sc);
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if (r != USBD_NORMAL_COMPLETION) {
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aprint_error_dev(self, "init failed, error=%d\n", r);
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goto fail;
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}
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if (!pmf_device_register1(self, xhci_suspend, xhci_resume,
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xhci_shutdown))
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aprint_error_dev(self, "couldn't establish power handler\n");
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/* Attach usb device. */
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sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint);
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return;
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fail:
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if (sc->sc_ih) {
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pci_intr_disestablish(psc->sc_pc, sc->sc_ih);
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sc->sc_ih = NULL;
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}
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if (sc->sc_ios) {
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
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sc->sc_ios = 0;
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}
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return;
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}
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static int
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xhci_pci_detach(device_t self, int flags)
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{
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struct xhci_pci_softc * const psc = device_private(self);
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struct xhci_softc * const sc = &psc->sc_xhci;
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int rv;
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rv = xhci_detach(sc, flags);
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if (rv)
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return rv;
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pmf_device_deregister(self);
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xhci_shutdown(self, flags);
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if (sc->sc_ios) {
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#if 0
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/* Disable interrupts, so we don't get any spurious ones. */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh,
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OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
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#endif
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}
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if (sc->sc_ih != NULL) {
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pci_intr_disestablish(psc->sc_pc, sc->sc_ih);
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sc->sc_ih = NULL;
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}
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if (sc->sc_ios) {
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
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sc->sc_ios = 0;
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}
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return 0;
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}
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CFATTACH_DECL3_NEW(xhci_pci, sizeof(struct xhci_pci_softc),
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xhci_pci_match, xhci_pci_attach, xhci_pci_detach, xhci_activate, NULL,
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xhci_childdet, DVF_DETACH_SHUTDOWN);
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@ -1,4 +1,4 @@
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/* $NetBSD: usb_subr.c,v 1.192 2013/09/07 16:39:15 skrll Exp $ */
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/* $NetBSD: usb_subr.c,v 1.193 2013/09/14 00:40:31 jakllsch Exp $ */
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/* $FreeBSD: src/sys/dev/usb/usb_subr.c,v 1.18 1999/11/17 22:33:47 n_hibma Exp $ */
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/*
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@ -32,7 +32,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: usb_subr.c,v 1.192 2013/09/07 16:39:15 skrll Exp $");
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__KERNEL_RCSID(0, "$NetBSD: usb_subr.c,v 1.193 2013/09/14 00:40:31 jakllsch Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_compat_netbsd.h"
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@ -82,12 +82,8 @@ Static int usbd_getnewaddr(usbd_bus_handle);
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Static int usbd_print(void *, const char *);
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Static int usbd_ifprint(void *, const char *);
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Static void usbd_free_iface_data(usbd_device_handle, int);
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Static void usbd_kill_pipe(usbd_pipe_handle);
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usbd_status usbd_attach_roothub(device_t, usbd_device_handle);
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Static usbd_status usbd_probe_and_attach(device_t, usbd_device_handle, int,
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int);
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Static u_int32_t usb_cookie_no = 0;
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uint32_t usb_cookie_no = 0;
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Static const char * const usbd_error_strs[] = {
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"NORMAL_COMPLETION",
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@ -1064,7 +1060,7 @@ usbd_reattach_device(device_t parent, usbd_device_handle dev,
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* recognize the initial descriptor fetch (before the control endpoint's
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* MaxPacketSize is known by the host) by exactly this length.
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*/
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static usbd_status
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usbd_status
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usbd_get_initial_ddesc(usbd_device_handle dev, usb_device_descriptor_t *desc)
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{
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usb_device_request_t req;
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@ -1107,6 +1103,11 @@ usbd_new_device(device_t parent, usbd_bus_handle bus, int depth,
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DPRINTF(("usbd_new_device bus=%p port=%d depth=%d speed=%d\n",
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bus, port, depth, speed));
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if (bus->methods->new_device != NULL)
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return (bus->methods->new_device)(parent, bus, depth, speed,
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port, up);
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addr = usbd_getnewaddr(bus);
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if (addr < 0) {
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printf("%s: No free USB addresses, new device ignored.\n",
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@ -1,4 +1,4 @@
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/* $NetBSD: usbdivar.h,v 1.104 2013/09/07 16:47:23 skrll Exp $ */
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/* $NetBSD: usbdivar.h,v 1.105 2013/09/14 00:40:31 jakllsch Exp $ */
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/*
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* Copyright (c) 1998, 2012 The NetBSD Foundation, Inc.
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@ -48,6 +48,7 @@
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* allocx -
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* freex -
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* get_lock - Called at attach time
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* new_device
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*
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* PIPE METHOD LOCK NOTES
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* ----------------------- ------- -------------------------
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@ -82,6 +83,7 @@ typedef struct {
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struct usbd_xfer;
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struct usbd_pipe;
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struct usbd_port;
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struct usbd_endpoint {
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usb_endpoint_descriptor_t *edesc;
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@ -99,6 +101,8 @@ struct usbd_bus_methods {
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struct usbd_xfer * (*allocx)(struct usbd_bus *);
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void (*freex)(struct usbd_bus *, struct usbd_xfer *);
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void (*get_lock)(struct usbd_bus *, kmutex_t **);
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usbd_status (*new_device)(device_t, usbd_bus_handle, int,
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int, int, struct usbd_port *);
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};
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struct usbd_pipe_methods {
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@ -191,6 +195,7 @@ struct usbd_device {
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int subdevlen; /* array length of following */
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device_t *subdevs; /* sub-devices */
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int nifaces_claimed; /* number of ifaces in use */
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void *hci_private;
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};
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struct usbd_interface {
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@ -308,6 +313,12 @@ usbd_status usb_insert_transfer(usbd_xfer_handle);
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void usb_transfer_complete(usbd_xfer_handle);
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int usb_disconnect_port(struct usbd_port *, device_t, int);
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void usbd_kill_pipe(usbd_pipe_handle);
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usbd_status usbd_attach_roothub(device_t, usbd_device_handle);
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usbd_status usbd_probe_and_attach(device_t, usbd_device_handle, int, int);
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usbd_status usbd_get_initial_ddesc(usbd_device_handle,
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usb_device_descriptor_t *);
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/* Routines from usb.c */
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void usb_needs_explore(usbd_device_handle);
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void usb_needs_reattach(usbd_device_handle);
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2841
sys/dev/usb/xhci.c
Normal file
2841
sys/dev/usb/xhci.c
Normal file
File diff suppressed because it is too large
Load Diff
426
sys/dev/usb/xhcireg.h
Normal file
426
sys/dev/usb/xhcireg.h
Normal file
@ -0,0 +1,426 @@
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/* $NetBSD: xhcireg.h,v 1.1 2013/09/14 00:40:31 jakllsch Exp $ */
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
|
||||
*
|
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*/
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#ifndef _XHCIREG_H_
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#define _XHCIREG_H_
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/* XHCI PCI config registers */
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#define PCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_INTERFACE_XHCI 0x30
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#define PCI_USBREV 0x60 /* RO USB protocol revision */
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#define PCI_USBREV_MASK 0xFF
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#define PCI_USBREV_3_0 0x30 /* USB 3.0 */
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#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */
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/* XHCI capability registers */
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#define XHCI_CAPLENGTH 0x00 /* RO capability */
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#define XHCI_CAP_CAPLENGTH(x) ((x) & 0xFF)
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#define XHCI_CAP_HCIVERSION(x) (((x) >> 16) & 0xFFFF) /* RO Interface version number */
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#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */
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#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */
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#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */
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#define XHCI_HCS1_MAXSLOTS(x) ((x) & 0xFF)
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#define XHCI_HCS1_MAXINTRS(x) (((x) >> 8) & 0x7FF)
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#define XHCI_HCS1_MAXPORTS(x) (((x) >> 24) & 0xFF)
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#define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */
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#define XHCI_HCS2_IST(x) ((x) & 0xF)
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#define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF)
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#define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1)
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#define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)
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#define XHCI_HCSPARAMS3 0x0C /* RO structual parameters 3 */
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#define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF)
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#define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */
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#define XHCI_HCC_AC64(x) ((x) & 0x1) /* 64-bit capable */
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#define XHCI_HCC_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */
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#define XHCI_HCC_CSZ(x) (((x) >> 2) & 0x1) /* context size */
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#define XHCI_HCC_PPC(x) (((x) >> 3) & 0x1) /* port power control */
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#define XHCI_HCC_PIND(x) (((x) >> 4) & 0x1) /* port indicators */
|
||||
#define XHCI_HCC_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */
|
||||
#define XHCI_HCC_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */
|
||||
#define XHCI_HCC_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */
|
||||
#define XHCI_HCC_MAXPSASIZE(x) (((x) >> 12) & 0xF) /* max pri. stream array size */
|
||||
#define XHCI_HCC_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */
|
||||
#define XHCI_DBOFF 0x14 /* RO doorbell offset */
|
||||
#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */
|
||||
|
||||
/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */
|
||||
#define XHCI_USBCMD 0x00 /* XHCI command */
|
||||
#define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */
|
||||
#define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */
|
||||
#define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */
|
||||
#define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */
|
||||
#define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */
|
||||
#define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */
|
||||
#define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */
|
||||
#define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */
|
||||
#define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */
|
||||
#define XHCI_USBSTS 0x04 /* XHCI status */
|
||||
#define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */
|
||||
#define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */
|
||||
#define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */
|
||||
#define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */
|
||||
#define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */
|
||||
#define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */
|
||||
#define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */
|
||||
#define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */
|
||||
#define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */
|
||||
#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */
|
||||
#define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */
|
||||
#define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */
|
||||
#define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */
|
||||
#define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */
|
||||
#define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */
|
||||
#define XHCI_DNCTRL 0x14 /* XHCI device notification control */
|
||||
#define XHCI_DNCTRL_MASK(n) (1U << (n))
|
||||
#define XHCI_CRCR 0x18 /* XHCI command ring control */
|
||||
#define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */
|
||||
#define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */
|
||||
#define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */
|
||||
#define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */
|
||||
#define XHCI_CRCR_LO_MASK 0x0000000F
|
||||
#define XHCI_CRCR_HI 0x1C /* XHCI command ring control */
|
||||
#define XHCI_DCBAAP 0x30 /* XHCI dev context BA pointer */
|
||||
#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */
|
||||
#define XHCI_CONFIG 0x38
|
||||
#define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
|
||||
|
||||
/* XHCI port status registers */
|
||||
#define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */
|
||||
#define XHCI_PS_CCS 0x00000001 /* RO - current connect status */
|
||||
#define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
|
||||
#define XHCI_PS_OCA 0x00000008 /* RO - over current active */
|
||||
#define XHCI_PS_PR 0x00000010 /* RW - port reset */
|
||||
#define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
|
||||
#define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
|
||||
#define XHCI_PS_PP 0x00000200 /* RW - port power */
|
||||
#define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */
|
||||
#define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
|
||||
#define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
|
||||
#define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
|
||||
#define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
|
||||
#define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
|
||||
#define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
|
||||
#define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
|
||||
#define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
|
||||
#define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
|
||||
#define XHCI_PS_CEC 0x00800000 /* RW - config error change */
|
||||
#define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */
|
||||
#define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
|
||||
#define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
|
||||
#define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
|
||||
#define XHCI_PS_DR 0x40000000 /* RO - device removable */
|
||||
#define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
|
||||
#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */
|
||||
|
||||
#define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */
|
||||
#define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
|
||||
#define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
|
||||
#define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
|
||||
#define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
|
||||
#define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
|
||||
#define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */
|
||||
#define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
|
||||
#define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
|
||||
#define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
|
||||
#define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
|
||||
#define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
|
||||
#define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
|
||||
#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */
|
||||
#define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */
|
||||
#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */
|
||||
|
||||
/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
|
||||
#define XHCI_MFINDEX 0x0000 /* RO - microframe index */
|
||||
#define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF)
|
||||
#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */
|
||||
#define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
|
||||
#define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
|
||||
#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */
|
||||
#define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */
|
||||
#define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */
|
||||
#define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */
|
||||
#define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */
|
||||
#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */
|
||||
#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */
|
||||
#define XHCI_ERSTS_GET(x) ((x) & 0xFFFF)
|
||||
#define XHCI_ERSTS_SET(x) ((x) & 0xFFFF)
|
||||
#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */
|
||||
#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */
|
||||
#define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */
|
||||
#define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */
|
||||
#define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
|
||||
#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */
|
||||
|
||||
/* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
|
||||
#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
|
||||
#define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
|
||||
#define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
|
||||
#define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
|
||||
#define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */
|
||||
|
||||
/* XHCI legacy support */
|
||||
#define XHCI_XECP_ID(x) ((x) & 0xFF)
|
||||
#define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF)
|
||||
#if 0
|
||||
#define XHCI_XECP_BIOS_SEM 0x0002
|
||||
#define XHCI_XECP_OS_SEM 0x0003
|
||||
#endif
|
||||
|
||||
/* XHCI capability ID's */
|
||||
#define XHCI_ID_USB_LEGACY 0x0001
|
||||
#define XHCI_ID_PROTOCOLS 0x0002
|
||||
#define XHCI_ID_POWER_MGMT 0x0003
|
||||
#define XHCI_ID_VIRTUALIZATION 0x0004
|
||||
#define XHCI_ID_MSG_IRQ 0x0005
|
||||
#define XHCI_ID_USB_LOCAL_MEM 0x0006
|
||||
|
||||
#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz)
|
||||
|
||||
/* Chapter 6, Table 49 */
|
||||
#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64
|
||||
#define XHCI_DEVICE_CONTEXT_ALIGN 64
|
||||
#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64
|
||||
#define XHCI_SLOT_CONTEXT_ALIGN 32
|
||||
#define XHCI_ENDPOINT_CONTEXT_ALIGN 32
|
||||
#define XHCI_STREAM_CONTEXT_ALIGN 16
|
||||
#define XHCI_STREAM_ARRAY_ALIGN 16
|
||||
#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16
|
||||
#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 16
|
||||
#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64
|
||||
#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64
|
||||
#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64
|
||||
#define XHCI_SCRATCHPAD_BUFFERS_ALIGN XHCI_PAGE_SIZE
|
||||
|
||||
#define XHCI_ERSTE_ALIGN 16
|
||||
#define XHCI_TRB_ALIGN 16
|
||||
|
||||
struct xhci_trb {
|
||||
uint64_t trb_0;
|
||||
uint32_t trb_2;
|
||||
#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
|
||||
#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
|
||||
#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
|
||||
#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
|
||||
#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
|
||||
#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
|
||||
#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
|
||||
#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
|
||||
#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
|
||||
#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
|
||||
#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
|
||||
#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
|
||||
uint32_t trb_3;
|
||||
#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
|
||||
#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
|
||||
#define XHCI_TRB_3_CYCLE_BIT (1U << 0)
|
||||
#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
|
||||
#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
|
||||
#define XHCI_TRB_3_ISP_BIT (1U << 2)
|
||||
#define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
|
||||
#define XHCI_TRB_3_CHAIN_BIT (1U << 4)
|
||||
#define XHCI_TRB_3_IOC_BIT (1U << 5)
|
||||
#define XHCI_TRB_3_IDT_BIT (1U << 6)
|
||||
#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
|
||||
#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
|
||||
#define XHCI_TRB_3_BEI_BIT (1U << 9)
|
||||
#define XHCI_TRB_3_DCEP_BIT (1U << 9)
|
||||
#define XHCI_TRB_3_PRSV_BIT (1U << 9)
|
||||
#define XHCI_TRB_3_BSR_BIT (1U << 9)
|
||||
#define XHCI_TRB_3_TRT_MASK (3U << 16)
|
||||
#define XHCI_TRB_3_TRT_NONE (0U << 16)
|
||||
#define XHCI_TRB_3_TRT_OUT (2U << 16)
|
||||
#define XHCI_TRB_3_TRT_IN (3U << 16)
|
||||
#define XHCI_TRB_3_DIR_IN (1U << 16)
|
||||
#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
|
||||
#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
|
||||
#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
|
||||
#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
|
||||
#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
|
||||
#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
|
||||
#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
|
||||
#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
|
||||
#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
|
||||
#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
|
||||
|
||||
/* Commands */
|
||||
#define XHCI_TRB_TYPE_RESERVED 0x00
|
||||
#define XHCI_TRB_TYPE_NORMAL 0x01
|
||||
#define XHCI_TRB_TYPE_SETUP_STAGE 0x02
|
||||
#define XHCI_TRB_TYPE_DATA_STAGE 0x03
|
||||
#define XHCI_TRB_TYPE_STATUS_STAGE 0x04
|
||||
#define XHCI_TRB_TYPE_ISOCH 0x05
|
||||
#define XHCI_TRB_TYPE_LINK 0x06
|
||||
#define XHCI_TRB_TYPE_EVENT_DATA 0x07
|
||||
#define XHCI_TRB_TYPE_NOOP 0x08
|
||||
#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
|
||||
#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
|
||||
#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
|
||||
#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
|
||||
#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
|
||||
#define XHCI_TRB_TYPE_RESET_EP 0x0E
|
||||
#define XHCI_TRB_TYPE_STOP_EP 0x0F
|
||||
#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
|
||||
#define XHCI_TRB_TYPE_RESET_DEVICE 0x11
|
||||
#define XHCI_TRB_TYPE_FORCE_EVENT 0x12
|
||||
#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
|
||||
#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
|
||||
#define XHCI_TRB_TYPE_GET_PORT_BW 0x15
|
||||
#define XHCI_TRB_TYPE_FORCE_HEADER 0x16
|
||||
#define XHCI_TRB_TYPE_NOOP_CMD 0x17
|
||||
|
||||
/* Events */
|
||||
#define XHCI_TRB_EVENT_TRANSFER 0x20
|
||||
#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
|
||||
#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
|
||||
#define XHCI_TRB_EVENT_BW_REQUEST 0x23
|
||||
#define XHCI_TRB_EVENT_DOORBELL 0x24
|
||||
#define XHCI_TRB_EVENT_HOST_CTRL 0x25
|
||||
#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
|
||||
#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
|
||||
|
||||
/* Error codes */
|
||||
#define XHCI_TRB_ERROR_INVALID 0x00
|
||||
#define XHCI_TRB_ERROR_SUCCESS 0x01
|
||||
#define XHCI_TRB_ERROR_DATA_BUF 0x02
|
||||
#define XHCI_TRB_ERROR_BABBLE 0x03
|
||||
#define XHCI_TRB_ERROR_XACT 0x04
|
||||
#define XHCI_TRB_ERROR_TRB 0x05
|
||||
#define XHCI_TRB_ERROR_STALL 0x06
|
||||
#define XHCI_TRB_ERROR_RESOURCE 0x07
|
||||
#define XHCI_TRB_ERROR_BANDWIDTH 0x08
|
||||
#define XHCI_TRB_ERROR_NO_SLOTS 0x09
|
||||
#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
|
||||
#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
|
||||
#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
|
||||
#define XHCI_TRB_ERROR_SHORT_PKT 0x0D
|
||||
#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
|
||||
#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
|
||||
#define XHCI_TRB_ERROR_VF_RING_FULL 0x10
|
||||
#define XHCI_TRB_ERROR_PARAMETER 0x11
|
||||
#define XHCI_TRB_ERROR_BW_OVERRUN 0x12
|
||||
#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
|
||||
#define XHCI_TRB_ERROR_NO_PING_RESP 0x14
|
||||
#define XHCI_TRB_ERROR_EV_RING_FULL 0x15
|
||||
#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
|
||||
#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
|
||||
#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
|
||||
#define XHCI_TRB_ERROR_CMD_ABORTED 0x19
|
||||
#define XHCI_TRB_ERROR_STOPPED 0x1A
|
||||
#define XHCI_TRB_ERROR_LENGTH 0x1B
|
||||
#define XHCI_TRB_ERROR_BAD_MELAT 0x1D
|
||||
#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
|
||||
#define XHCI_TRB_ERROR_EVENT_LOST 0x20
|
||||
#define XHCI_TRB_ERROR_UNDEFINED 0x21
|
||||
#define XHCI_TRB_ERROR_INVALID_SID 0x22
|
||||
#define XHCI_TRB_ERROR_SEC_BW 0x23
|
||||
#define XHCI_TRB_ERROR_SPLIT_XACT 0x24
|
||||
} __packed __aligned(XHCI_TRB_ALIGN);
|
||||
#define XHCI_TRB_SIZE sizeof(struct xhci_trb)
|
||||
|
||||
#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
|
||||
#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
|
||||
#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
|
||||
#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
|
||||
#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
|
||||
#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
|
||||
#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
|
||||
#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
|
||||
#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
|
||||
#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
|
||||
|
||||
#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
|
||||
#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
|
||||
#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
|
||||
#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
|
||||
#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
|
||||
#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
|
||||
|
||||
#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
|
||||
#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
|
||||
#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
|
||||
#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
|
||||
#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
|
||||
#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
|
||||
#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
|
||||
#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
|
||||
|
||||
#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
|
||||
#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
|
||||
#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
|
||||
#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
|
||||
|
||||
|
||||
#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
|
||||
#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
|
||||
#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
|
||||
#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
|
||||
#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
|
||||
#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
|
||||
#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
|
||||
#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
|
||||
#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
|
||||
#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
|
||||
|
||||
#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
|
||||
#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
|
||||
#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
|
||||
#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
|
||||
#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
|
||||
#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
|
||||
#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
|
||||
#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
|
||||
#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
|
||||
#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
|
||||
|
||||
#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
|
||||
#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
|
||||
#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
|
||||
|
||||
#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
|
||||
#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
|
||||
#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
|
||||
#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
|
||||
|
||||
|
||||
#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
|
||||
|
||||
#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
|
||||
|
||||
#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
|
||||
|
||||
|
||||
struct xhci_erste {
|
||||
uint64_t erste_0; /* 63:6 base */
|
||||
uint32_t erste_2; /* 15:0 trb count (16 to 4096) */
|
||||
uint32_t erste_3; /* RsvdZ */
|
||||
} __packed __aligned(XHCI_ERSTE_ALIGN);
|
||||
#define XHCI_ERSTE_SIZE sizeof(struct xhci_erste)
|
||||
|
||||
#endif /* _XHCIREG_H_ */
|
||||
127
sys/dev/usb/xhcivar.h
Normal file
127
sys/dev/usb/xhcivar.h
Normal file
@ -0,0 +1,127 @@
|
||||
/* $NetBSD: xhcivar.h,v 1.1 2013/09/14 00:40:31 jakllsch Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 Jonathan A. Kollasch
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DEV_USB_XHCIVAR_H_
|
||||
#define _DEV_USB_XHCIVAR_H_
|
||||
|
||||
#include <sys/pool.h>
|
||||
|
||||
struct xhci_xfer {
|
||||
struct usbd_xfer xx_xfer;
|
||||
struct usb_task xx_abort_task;
|
||||
struct xhci_trb xx_trb[20];
|
||||
};
|
||||
|
||||
struct xhci_ring {
|
||||
usb_dma_t xr_dma;
|
||||
kmutex_t xr_lock;
|
||||
struct xhci_trb * xr_trb;
|
||||
void **xr_cookies;
|
||||
u_int xr_ntrb; /* number of elements for above */
|
||||
u_int xr_ep; /* enqueue pointer */
|
||||
u_int xr_cs; /* cycle state */
|
||||
bool is_halted;
|
||||
};
|
||||
|
||||
struct xhci_endpoint {
|
||||
struct xhci_ring xe_tr; /* transfer ring */
|
||||
};
|
||||
|
||||
struct xhci_slot {
|
||||
usb_dma_t xs_dc_dma; /* device context page */
|
||||
usb_dma_t xs_ic_dma; /* input context page */
|
||||
struct xhci_endpoint xs_ep[32]; /* endpoints */
|
||||
u_int xs_idx; /* slot index */
|
||||
};
|
||||
|
||||
struct xhci_softc {
|
||||
device_t sc_dev;
|
||||
device_t sc_child;
|
||||
void *sc_ih;
|
||||
bus_size_t sc_ios;
|
||||
bus_space_tag_t sc_iot;
|
||||
bus_space_handle_t sc_ioh; /* Base */
|
||||
bus_space_handle_t sc_cbh; /* Capability Base */
|
||||
bus_space_handle_t sc_obh; /* Operational Base */
|
||||
bus_space_handle_t sc_rbh; /* Runtime Base */
|
||||
bus_space_handle_t sc_dbh; /* Doorbell Registers */
|
||||
struct usbd_bus sc_bus;
|
||||
|
||||
kmutex_t sc_lock;
|
||||
kmutex_t sc_intr_lock;
|
||||
kcondvar_t sc_softwake_cv;
|
||||
|
||||
usbd_xfer_handle sc_intrxfer;
|
||||
|
||||
pool_cache_t sc_xferpool;
|
||||
|
||||
bus_size_t sc_pgsz; /* xHCI page size */
|
||||
uint32_t sc_ctxsz;
|
||||
int sc_maxslots;
|
||||
int sc_maxintrs;
|
||||
int sc_maxports;
|
||||
|
||||
/* XXX suboptimal */
|
||||
int sc_hs_port_start;
|
||||
int sc_hs_port_count;
|
||||
int sc_ss_port_start;
|
||||
int sc_ss_port_count;
|
||||
|
||||
struct xhci_slot * sc_slots;
|
||||
|
||||
struct xhci_ring sc_cr; /* command ring */
|
||||
struct xhci_ring sc_er; /* event ring */
|
||||
|
||||
usb_dma_t sc_eventst_dma;
|
||||
usb_dma_t sc_dcbaa_dma;
|
||||
|
||||
//struct usb_dma_reserve sc_dma_reserve;
|
||||
|
||||
kcondvar_t sc_command_cv;
|
||||
bus_addr_t sc_command_addr;
|
||||
struct xhci_trb sc_result_trb;
|
||||
|
||||
bool sc_ac64;
|
||||
bool sc_dying;
|
||||
|
||||
uint8_t sc_addr;
|
||||
uint8_t sc_conf;
|
||||
};
|
||||
|
||||
usbd_status xhci_init(struct xhci_softc *);
|
||||
int xhci_intr(void *);
|
||||
int xhci_detach(struct xhci_softc *, int);
|
||||
int xhci_activate(device_t, enum devact);
|
||||
void xhci_childdet(device_t, device_t);
|
||||
bool xhci_suspend(device_t, const pmf_qual_t *);
|
||||
bool xhci_resume(device_t, const pmf_qual_t *);
|
||||
bool xhci_shutdown(device_t, int);
|
||||
|
||||
#define XHCI_TRANSFER_RING_TRBS 256
|
||||
|
||||
#endif /* _DEV_USB_XHCIVAR_H_ */
|
||||
Loading…
Reference in New Issue
Block a user