2008-04-29 00:22:51 +04:00
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/* $NetBSD: pcscpreg.h,v 1.2 2008/04/28 20:23:55 martin Exp $ */
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1999-01-07 02:23:33 +03:00
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Izumi Tsutsui.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Am53c974 DMA engine registers
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*/
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#define DMA_CMD 0x40 /* Command */
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#define DMACMD_RSVD 0xFFFFFF28 /* reserved */
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#define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */
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#define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */
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#define DMACMD_MDL 0x00000010 /* Map to Memory Description List */
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#define DMACMD_DIAG 0x00000004 /* Diagnostic */
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#define DMACMD_CMD 0x00000003 /* Command Code Bit */
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#define DMACMD_IDLE 0x00000000 /* Idle */
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#define DMACMD_BLAST 0x00000001 /* Blast */
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#define DMACMD_ABORT 0x00000002 /* Abort */
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#define DMACMD_START 0x00000003 /* Start */
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#define DMA_STC 0x44 /* Start Transfer Count */
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#define DMA_SPA 0x48 /* Start Physical Address */
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#define DMA_WBC 0x4C /* Working Byte Counter */
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#define DMA_WAC 0x50 /* Working Address Counter */
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#define DMA_STAT 0x54 /* Status Register */
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#define DMASTAT_RSVD 0xFFFFFF80 /* reserved */
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#define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */
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#define DMASTAT_BCMP 0x00000020 /* BLAST Complete */
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#define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */
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#define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */
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#define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */
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#define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */
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#define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */
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#define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */
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#define DMA_WMAC 0x5C /* Working MDL Counter */
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#define DMA_SBAC 0x70 /* SCSI Bus and Control */
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