Device driver for the AMD Am53c974 PCscsi-PCI SCSI chip (i.e. the chip used
on the Tekram DC-390 SCSI cards), from Izumi Tsutsui, PR#6654. Minor cosmetic changes by me.
This commit is contained in:
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/* $NetBSD: pcscp.c,v 1.1 1999/01/06 23:23:33 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center; Izumi Tsutsui.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* pcscp.c: device dependent code for AMD Am53c974 (PCscsi-PCI)
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* written by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
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*
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* Technical manual available at
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* http://www.amd.com/products/npd/techdocs/19113a.pdf
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/pci/pcscpreg.h>
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#define IO_MAP_REG 0x10
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#define MEM_MAP_REG 0x14
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struct pcscp_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_st; /* bus space tag */
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bus_space_handle_t sc_sh; /* bus space handle */
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void *sc_ih; /* interrupt cookie */
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bus_dma_tag_t sc_dmat; /* DMA tag */
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bus_dmamap_t sc_xfermap; /* DMA map for transfers */
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u_int32_t *sc_mdladdr; /* MDL array */
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bus_dmamap_t sc_mdldmap; /* MDL DMA map */
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int sc_active; /* DMA state */
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int sc_datain; /* DMA Data Direction */
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size_t sc_dmasize; /* DMA size */
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char **sc_dmaaddr; /* DMA address */
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size_t *sc_dmalen; /* DMA length */
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};
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#define READ_DMAREG(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define WRITE_DMAREG(sc, reg, var) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var))
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/* don't have to use MI defines in MD code... */
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#undef NCR_READ_REG
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#define NCR_READ_REG(sc, reg) pcscp_read_reg((sc), (reg))
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#undef NCR_WRITE_REG
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#define NCR_WRITE_REG(sc, reg, val) pcscp_write_reg((sc), (reg), (val))
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int pcscp_match __P((struct device *, struct cfdata *, void *));
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void pcscp_attach __P((struct device *, struct device *, void *));
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struct cfattach pcscp_ca = {
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sizeof(struct pcscp_softc), pcscp_match, pcscp_attach
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};
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struct scsipi_device pcscp_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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u_char pcscp_read_reg __P((struct ncr53c9x_softc *, int));
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void pcscp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int pcscp_dma_isintr __P((struct ncr53c9x_softc *));
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void pcscp_dma_reset __P((struct ncr53c9x_softc *));
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int pcscp_dma_intr __P((struct ncr53c9x_softc *));
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int pcscp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void pcscp_dma_go __P((struct ncr53c9x_softc *));
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void pcscp_dma_stop __P((struct ncr53c9x_softc *));
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int pcscp_dma_isactive __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue pcscp_glue = {
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pcscp_read_reg,
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pcscp_write_reg,
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pcscp_dma_isintr,
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pcscp_dma_reset,
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pcscp_dma_intr,
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pcscp_dma_setup,
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pcscp_dma_go,
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pcscp_dma_stop,
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pcscp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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int
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pcscp_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
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return 0;
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_AMD_PCSCSI_PCI:
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#if 0
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case PCI_PRODUCT_AMD_PCNETS_PCI:
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#endif
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return 1;
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}
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return 0;
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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pcscp_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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struct pcscp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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bus_space_tag_t st, iot, memt;
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bus_space_handle_t sh, ioh, memh;
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int ioh_valid, memh_valid;
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pci_intr_handle_t ih;
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const char *intrstr;
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pcireg_t csr;
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bus_dma_segment_t seg;
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int error, rseg;
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ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
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PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, NULL, NULL) == 0);
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#if 0 /* XXX cannot use memory map? */
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memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&memt, &memh, NULL, NULL) == 0);
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#else
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memh_valid = 0;
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#endif
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if (memh_valid) {
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st = memt;
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sh = memh;
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} else if (ioh_valid) {
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st = iot;
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sh = ioh;
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} else {
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printf(": unable to map registers\n");
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return;
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}
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printf("\n");
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sc->sc_glue = &pcscp_glue;
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esc->sc_st = st;
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esc->sc_sh = sh;
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esc->sc_dmat = pa->pa_dmat;
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csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* Set up static configuration info.
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*/
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/*
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* XXX should read configuration from EEPROM?
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*
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* MI ncr53c9x driver does not support configuration
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* per each target device, though...
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*/
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sc->sc_id = 7;
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
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sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK;
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sc->sc_rev = NCR_VARIANT_AM53C974;
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sc->sc_features = NCR_F_FASTSCSI;
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sc->sc_freq = 40; /* MHz */
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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/* Really no limit, but since we want to fit into the TCR... */
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sc->sc_maxxfer = 16 * 1024 * 1024;
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/* map and establish interrupt */
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if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &ih)) {
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printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, ih);
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esc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
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(int (*)(void *))ncr53c9x_intr, esc);
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if (esc->sc_ih == NULL) {
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printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname);
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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if (intrstr != NULL)
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printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname,
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intrstr);
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/*
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* Create the DMA maps for the data transfers.
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*/
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#define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */
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#define MDL_SEG_OFFSET 0x0FFF
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#define MDL_SIZE (MAXPHYS / MDL_SEG_SIZE + 1) /* no hardware limit? */
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if (bus_dmamap_create(esc->sc_dmat, MAXPHYS, MDL_SIZE, MAXPHYS, 0,
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BUS_DMA_NOWAIT, &esc->sc_xfermap)) {
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printf("%s: can't create dma maps\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Allocate and map memory for the MDL.
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*/
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if ((error = bus_dmamem_alloc(esc->sc_dmat,
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sizeof(u_int32_t) * MDL_SIZE, NBPG, 0, &seg, 1, &rseg,
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BUS_DMA_NOWAIT)) != 0) {
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printf("%s: unable to allocate memory for the MDL, "
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"error = %d\n", sc->sc_dev.dv_xname, error);
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return;
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}
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if ((error = bus_dmamem_map(esc->sc_dmat, &seg, rseg,
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sizeof(u_int32_t) * MDL_SIZE , (caddr_t *)&esc->sc_mdladdr,
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BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
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printf("%s: unable to map the MDL memory, error = %d\n",
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sc->sc_dev.dv_xname, error);
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return;
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}
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if ((error = bus_dmamap_create(esc->sc_dmat,
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sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE,
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0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) {
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printf("%s: unable to map_create for the MDL, error = %d\n",
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sc->sc_dev.dv_xname, error);
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return;
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}
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if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_mdldmap,
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esc->sc_mdladdr, sizeof(u_int32_t) * MDL_SIZE,
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NULL, BUS_DMA_NOWAIT)) != 0) {
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printf("%s: unable to load for the MDL, error = %d\n",
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sc->sc_dev.dv_xname, error);
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return;
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}
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/* Do the common parts of attachment. */
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printf("%s", sc->sc_dev.dv_xname);
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sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
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sc->sc_adapter.scsipi_minphys = minphys;
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ncr53c9x_attach(sc, &pcscp_dev);
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/* Turn on target selection using the `dma' method */
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ncr53c9x_dmaselect = 1;
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}
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/*
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* Glue functions.
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*/
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u_char
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pcscp_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct pcscp_softc *esc = (struct pcscp_softc *)sc;
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return bus_space_read_1(esc->sc_st, esc->sc_sh, reg << 2);
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}
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void
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pcscp_write_reg(sc, reg, v)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char v;
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{
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struct pcscp_softc *esc = (struct pcscp_softc *)sc;
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bus_space_write_1(esc->sc_st, esc->sc_sh, reg << 2, v);
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}
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int
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pcscp_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT;
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}
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void
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pcscp_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct pcscp_softc *esc = (struct pcscp_softc *)sc;
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WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE);
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esc->sc_active = 0;
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}
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int
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pcscp_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct pcscp_softc *esc = (struct pcscp_softc *)sc;
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int trans, resid, i;
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bus_dmamap_t dmap = esc->sc_xfermap;
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int datain = esc->sc_datain;
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u_int32_t dmastat;
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char *p = NULL;
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dmastat = READ_DMAREG(esc, DMA_STAT);
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if (dmastat & DMASTAT_ERR) {
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/* XXX not tested... */
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WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT |
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(datain ? DMACMD_DIR : 0));
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printf("%s: error: DMA error detected; Aborting.\n",
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sc->sc_dev.dv_xname);
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bus_dmamap_unload(esc->sc_dmat, dmap);
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return -1;
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}
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if (dmastat & DMASTAT_ABT) {
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/* XXX What should be done? */
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printf("%s: dma_intr: DMA aborted.\n", sc->sc_dev.dv_xname);
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WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE |
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(datain ? DMACMD_DIR : 0));
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esc->sc_active = 0;
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return 0;
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}
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/* This is an "assertion" :) */
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if (esc->sc_active == 0)
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panic("pcscp dmaintr: DMA wasn't active");
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/* DMA has stopped */
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esc->sc_active = 0;
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if (esc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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NCR_READ_REG(sc, NCR_TCL) |
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(NCR_READ_REG(sc, NCR_TCM) << 8),
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NCR_READ_REG(sc, NCR_TCL),
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NCR_READ_REG(sc, NCR_TCM)));
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE |
|
||||
(datain ? DMACMD_DIR : 0));
|
||||
bus_dmamap_unload(esc->sc_dmat, dmap);
|
||||
return 0;
|
||||
}
|
||||
|
||||
resid = 0;
|
||||
|
||||
if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
|
||||
/*
|
||||
* `Terminal count' is off, so read the residue
|
||||
* out of the ESP counter registers.
|
||||
*/
|
||||
if (datain) {
|
||||
resid = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF;
|
||||
while (resid > 1)
|
||||
resid = NCR_READ_REG(sc, NCR_FFLAG) &
|
||||
NCRFIFO_FF;
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_MDL |
|
||||
(datain ? DMACMD_DIR : 0));
|
||||
|
||||
for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
|
||||
if (READ_DMAREG(esc, DMA_STAT) & DMASTAT_BCMP)
|
||||
break;
|
||||
|
||||
/* See the below comments... */
|
||||
if (resid)
|
||||
p = *esc->sc_dmaaddr;
|
||||
}
|
||||
|
||||
resid += (NCR_READ_REG(sc, NCR_TCL) |
|
||||
(NCR_READ_REG(sc, NCR_TCM) << 8) |
|
||||
((sc->sc_cfg2 & NCRCFG2_FE)
|
||||
? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0));
|
||||
|
||||
if (resid == 0 && esc->sc_dmasize == 65536 &&
|
||||
(sc->sc_cfg2 & NCRCFG2_FE) == 0)
|
||||
/* A transfer of 64K is encoded as `TCL=TCM=0' */
|
||||
resid = 65536;
|
||||
} else {
|
||||
while((dmastat & DMASTAT_DONE) == 0)
|
||||
dmastat = READ_DMAREG(esc, DMA_STAT);
|
||||
}
|
||||
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
|
||||
|
||||
bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
|
||||
datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(esc->sc_dmat, dmap);
|
||||
|
||||
trans = esc->sc_dmasize - resid;
|
||||
|
||||
/*
|
||||
* From the technical manual notes:
|
||||
*
|
||||
* `In some odd byte conditions, one residual byte will be left
|
||||
* in the SCSI FIFO, and the FIFO flags will never count to 0.
|
||||
* When this happens, the residual byte should be retrieved
|
||||
* via PIO following completion of the BLAST operation.'
|
||||
*/
|
||||
|
||||
if (p) {
|
||||
p += trans;
|
||||
*p = NCR_READ_REG(sc, NCR_FIFO);
|
||||
trans++;
|
||||
}
|
||||
|
||||
if (trans < 0) { /* transferred < 0 ? */
|
||||
#if 0
|
||||
/*
|
||||
* This situation can happen in perfectly normal operation
|
||||
* if the ESP is reselected while using DMA to select
|
||||
* another target. As such, don't print the warning.
|
||||
*/
|
||||
printf("%s: xfer (%d) > req (%d)\n",
|
||||
sc->sc_dev.dv_xname, trans, esc->sc_dmasize);
|
||||
#endif
|
||||
trans = esc->sc_dmasize;
|
||||
}
|
||||
|
||||
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
||||
NCR_READ_REG(sc, NCR_TCL),
|
||||
NCR_READ_REG(sc, NCR_TCM),
|
||||
(sc->sc_cfg2 & NCRCFG2_FE)
|
||||
? NCR_READ_REG(sc, NCR_TCH) : 0,
|
||||
trans, resid));
|
||||
|
||||
*esc->sc_dmalen -= trans;
|
||||
*esc->sc_dmaaddr += trans;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
pcscp_dma_setup(sc, addr, len, datain, dmasize)
|
||||
struct ncr53c9x_softc *sc;
|
||||
caddr_t *addr;
|
||||
size_t *len;
|
||||
int datain;
|
||||
size_t *dmasize;
|
||||
{
|
||||
struct pcscp_softc *esc = (struct pcscp_softc *)sc;
|
||||
bus_dmamap_t dmap = esc->sc_xfermap;
|
||||
u_int32_t *mdl;
|
||||
int error, nseg, seg;
|
||||
bus_addr_t s_offset, s_addr;
|
||||
long rest, count;
|
||||
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain ? DMACMD_DIR : 0));
|
||||
|
||||
esc->sc_dmaaddr = addr;
|
||||
esc->sc_dmalen = len;
|
||||
esc->sc_dmasize = *dmasize;
|
||||
esc->sc_datain = datain;
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if ((*dmasize / MDL_SEG_SIZE) > MDL_SIZE)
|
||||
panic("pcscp: transfer size too large");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* XXX should handle `Transfer Pad' operation?
|
||||
* (case of *dmasize == 0)
|
||||
*/
|
||||
|
||||
error = bus_dmamap_load(esc->sc_dmat, dmap, *esc->sc_dmaaddr,
|
||||
*esc->sc_dmalen, NULL,
|
||||
sc->sc_nexus->xs->flags & SCSI_NOSLEEP ?
|
||||
BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
|
||||
if (error) {
|
||||
printf("%s: unable to load dmamap, error = %d\n",
|
||||
sc->sc_dev.dv_xname, error);
|
||||
return error;
|
||||
}
|
||||
|
||||
/* set transfer length */
|
||||
WRITE_DMAREG(esc, DMA_STC, *dmasize);
|
||||
|
||||
/* set up MDL */
|
||||
mdl = esc->sc_mdladdr;
|
||||
nseg = dmap->dm_nsegs;
|
||||
seg = 0;
|
||||
|
||||
/* the first segment is possibly not aligned with 4k MDL boundary */
|
||||
count = dmap->dm_segs[seg].ds_len;
|
||||
s_offset = dmap->dm_segs[seg].ds_addr & MDL_SEG_OFFSET;
|
||||
s_addr = dmap->dm_segs[seg].ds_addr - s_offset;
|
||||
rest = MDL_SEG_SIZE - s_offset;
|
||||
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
#define htopci(addr) bswap32(addr)
|
||||
#else
|
||||
#define htopci(addr) (addr)
|
||||
#endif
|
||||
|
||||
/* set the first MDL and offset */
|
||||
WRITE_DMAREG(esc, DMA_SPA, s_offset);
|
||||
*mdl++ = htopci(s_addr);
|
||||
count -= rest;
|
||||
|
||||
/* rests of the first dmamap segment */
|
||||
while (count > 0) {
|
||||
s_addr += MDL_SEG_SIZE;
|
||||
*mdl++ = htopci(s_addr);
|
||||
count -= MDL_SEG_SIZE;
|
||||
}
|
||||
|
||||
/* the rest dmamap segments are aligned with 4k boundary */
|
||||
for (seg = 1; seg < nseg; seg++) {
|
||||
count = dmap->dm_segs[seg].ds_len;
|
||||
s_addr = dmap->dm_segs[seg].ds_addr;
|
||||
|
||||
/* first 4kbyte of each dmamap segment */
|
||||
*mdl++ = htopci(s_addr);
|
||||
count -= MDL_SEG_SIZE;
|
||||
|
||||
/* trailing contiguous 4k frames of each dmamap segments */
|
||||
while (count > 0) {
|
||||
s_addr += MDL_SEG_SIZE;
|
||||
*mdl++ = htopci(s_addr);
|
||||
count -= MDL_SEG_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
#undef htopci
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
pcscp_dma_go(sc)
|
||||
struct ncr53c9x_softc *sc;
|
||||
{
|
||||
struct pcscp_softc *esc = (struct pcscp_softc *)sc;
|
||||
bus_dmamap_t dmap = esc->sc_xfermap, mdldmap = esc->sc_mdldmap;
|
||||
int datain = esc->sc_datain;
|
||||
|
||||
/* sync transfer buffer */
|
||||
bus_dmamap_sync(esc->sc_dmat, dmap, 0, dmap->dm_mapsize,
|
||||
datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
|
||||
|
||||
/* sync MDL */
|
||||
bus_dmamap_sync(esc->sc_dmat, mdldmap, 0, mdldmap->dm_mapsize,
|
||||
BUS_DMASYNC_PREWRITE);
|
||||
|
||||
/* set Starting MDL Address */
|
||||
WRITE_DMAREG(esc, DMA_SMDLA, esc->sc_mdldmap->dm_segs[0].ds_addr);
|
||||
|
||||
/* set DMA command register bits */
|
||||
/* XXX DMA Transfer Interrupt Enable bit is broken? */
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | DMACMD_MDL |
|
||||
/* DMACMD_INTE | */
|
||||
(datain ? DMACMD_DIR : 0));
|
||||
|
||||
/* issue DMA start command */
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | DMACMD_MDL |
|
||||
/* DMACMD_INTE | */
|
||||
(datain ? DMACMD_DIR : 0));
|
||||
|
||||
esc->sc_active = 1;
|
||||
}
|
||||
|
||||
void
|
||||
pcscp_dma_stop(sc)
|
||||
struct ncr53c9x_softc *sc;
|
||||
{
|
||||
struct pcscp_softc *esc = (struct pcscp_softc *)sc;
|
||||
|
||||
/* dma stop */
|
||||
/* XXX What should we do here ? */
|
||||
WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT |
|
||||
( esc->sc_datain ? DMACMD_DIR : 0));
|
||||
|
||||
esc->sc_active = 0;
|
||||
}
|
||||
|
||||
int
|
||||
pcscp_dma_isactive(sc)
|
||||
struct ncr53c9x_softc *sc;
|
||||
{
|
||||
struct pcscp_softc *esc = (struct pcscp_softc *)sc;
|
||||
|
||||
/* XXX should check esc->sc_active? */
|
||||
if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,72 @@
|
|||
/* $NetBSD: pcscpreg.h,v 1.1 1999/01/06 23:23:33 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Izumi Tsutsui.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the NetBSD
|
||||
* Foundation, Inc. and its contributors.
|
||||
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Am53c974 DMA engine registers
|
||||
*/
|
||||
|
||||
#define DMA_CMD 0x40 /* Command */
|
||||
#define DMACMD_RSVD 0xFFFFFF28 /* reserved */
|
||||
#define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */
|
||||
#define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */
|
||||
#define DMACMD_MDL 0x00000010 /* Map to Memory Description List */
|
||||
#define DMACMD_DIAG 0x00000004 /* Diagnostic */
|
||||
#define DMACMD_CMD 0x00000003 /* Command Code Bit */
|
||||
#define DMACMD_IDLE 0x00000000 /* Idle */
|
||||
#define DMACMD_BLAST 0x00000001 /* Blast */
|
||||
#define DMACMD_ABORT 0x00000002 /* Abort */
|
||||
#define DMACMD_START 0x00000003 /* Start */
|
||||
|
||||
#define DMA_STC 0x44 /* Start Transfer Count */
|
||||
#define DMA_SPA 0x48 /* Start Physical Address */
|
||||
#define DMA_WBC 0x4C /* Working Byte Counter */
|
||||
#define DMA_WAC 0x50 /* Working Address Counter */
|
||||
|
||||
#define DMA_STAT 0x54 /* Status Register */
|
||||
#define DMASTAT_RSVD 0xFFFFFF80 /* reserved */
|
||||
#define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */
|
||||
#define DMASTAT_BCMP 0x00000020 /* BLAST Complete */
|
||||
#define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */
|
||||
#define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */
|
||||
#define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */
|
||||
#define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */
|
||||
#define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */
|
||||
|
||||
#define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */
|
||||
#define DMA_WMAC 0x5C /* Working MDL Counter */
|
||||
#define DMA_SBAC 0x70 /* SCSI Bus and Control */
|
Loading…
Reference in New Issue