2002-02-28 04:56:57 +03:00
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/* $NetBSD: mmu.h,v 1.3 2002/02/28 01:56:58 uch Exp $ */
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2002-02-17 23:55:50 +03:00
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_MMU_H_
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#define _SH3_MMU_H_
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/*
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* Initialize routines.
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* sh_mmu_init Assign function vector, and register addresses.
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* Don't access hardware.
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* Call as possible as first.
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* sh_mmu_start Reset TLB entry, set default ASID, and start to
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* translate address.
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* Call after exception vector was installed.
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*
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* TLB access ops.
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* sh_tlb_invalidate_addr invalidate TLB entris for given
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* virtual addr with ASID.
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* sh_tlb_invalidate_asid invalidate TLB entries for given ASID.
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* sh_tlb_invalidate_all invalidate all non-wired TLB entries. //sana
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* sh_tlb_reset invalidate all TLB entries.
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* sh_tlb_set_asid set ASID to PTEH
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*
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* Page table acess ops. (for current NetBSD/sh3 implementation)
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*
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*/
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extern void sh_mmu_init(void);
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2002-02-22 22:43:58 +03:00
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extern void sh_mmu_information(void);
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2002-02-17 23:55:50 +03:00
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extern void (*__sh_mmu_start)(void);
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extern void sh3_mmu_start(void);
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extern void sh4_mmu_start(void);
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#define sh_mmu_start() (*__sh_mmu_start)()
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extern void sh_tlb_set_asid(int);
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extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t);
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extern void (*__sh_tlb_invalidate_asid)(int);
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extern void (*__sh_tlb_invalidate_all)(void);
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extern void (*__sh_tlb_reset)(void);
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extern void sh3_tlb_invalidate_addr(int, vaddr_t);
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extern void sh3_tlb_invalidate_asid(int);
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extern void sh3_tlb_invalidate_all(void);
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extern void sh3_tlb_reset(void);
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extern void sh4_tlb_invalidate_addr(int, vaddr_t);
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extern void sh4_tlb_invalidate_asid(int);
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extern void sh4_tlb_invalidate_all(void);
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extern void sh4_tlb_reset(void);
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#if defined(SH3) && defined(SH4)
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#define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va)
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#define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a)
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#define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)()
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#define sh_tlb_reset() (*__sh_tlb_reset)()
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#elif defined(SH3)
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#define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va)
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#define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a)
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#define sh_tlb_invalidate_all() sh3_tlb_invalidate_all()
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#define sh_tlb_reset() sh3_tlb_reset()
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#elif defined(SH4)
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#define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va)
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#define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a)
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#define sh_tlb_invalidate_all() sh4_tlb_invalidate_all()
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#define sh_tlb_reset() sh4_tlb_reset()
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#endif
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/*
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* MMU and page table entry access ops.
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*/
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#if defined(SH3) && defined(SH4)
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extern u_int32_t __sh_PTEH;
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extern u_int32_t __sh_TTB;
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extern u_int32_t __sh_TEA;
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#define SH_PTEH (*(__volatile__ u_int32_t *)__sh_PTEH)
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#define SH_TTB (*(__volatile__ u_int32_t *)__sh_TTB)
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#define SH_TEA (*(__volatile__ u_int32_t *)__sh_TEA)
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2002-02-28 04:56:57 +03:00
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2002-02-17 23:55:50 +03:00
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#elif defined(SH3)
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#define SH_PTEH (*(__volatile__ u_int32_t *)SH3_PTEH)
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#define SH_TTB (*(__volatile__ u_int32_t *)SH3_TTB)
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#define SH_TEA (*(__volatile__ u_int32_t *)SH3_TEA)
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2002-02-28 04:56:57 +03:00
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2002-02-17 23:55:50 +03:00
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#elif defined(SH4)
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#define SH_PTEH (*(__volatile__ u_int32_t *)SH4_PTEH)
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#define SH_TTB (*(__volatile__ u_int32_t *)SH4_TTB)
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#define SH_TEA (*(__volatile__ u_int32_t *)SH4_TEA)
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#endif
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extern void (*__sh_mmu_pte_setup)(vaddr_t, u_int32_t);
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extern void sh3_mmu_pte_setup(vaddr_t, u_int32_t);
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extern void sh4_mmu_pte_setup(vaddr_t, u_int32_t);
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#if defined(SH3) && defined(SH4)
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#define SH_MMU_PTE_SETUP(v, pte) (*__sh_mmu_pte_setup)((v), (pte))
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#elif defined(SH3)
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#define SH_MMU_PTE_SETUP(v, pte) sh3_mmu_pte_setup((v), (pte))
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#elif defined(SH4)
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#define SH_MMU_PTE_SETUP(v, pte) sh4_mmu_pte_setup((v), (pte))
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#endif
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/*
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* SH3 port access pte from P1, SH4 port access it from P2.
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*/
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extern u_int32_t (*__sh_mmu_pd_area)(u_int32_t);
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extern u_int32_t __sh3_mmu_pd_area(u_int32_t);
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extern u_int32_t __sh4_mmu_pd_area(u_int32_t);
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#if defined(SH3) && defined(SH4)
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#define SH_MMU_PD_AREA(x) __sh_mmu_pd_area(x)
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#elif defined(SH3)
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#define SH_MMU_PD_AREA(x) (x)
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#elif defined(SH4)
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#define SH_MMU_PD_AREA(x) SH3_P1SEG_TO_P2SEG(x)
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#endif
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/*
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* TTB stores pte entry start address.
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*/
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extern u_int32_t (*__sh_mmu_ttb_read)(void);
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extern void (*__sh_mmu_ttb_write)(u_int32_t);
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extern u_int32_t sh3_mmu_ttb_read(void);
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extern void sh3_mmu_ttb_write(u_int32_t);
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extern u_int32_t sh4_mmu_ttb_read(void);
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extern void sh4_mmu_ttb_write(u_int32_t);
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#if defined(SH3) && defined(SH4)
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#define SH_MMU_TTB_READ() (*__sh_mmu_ttb_read)()
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#define SH_MMU_TTB_WRITE(x) (*__sh_mmu_ttb_write)(x)
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#elif defined(SH3)
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#define SH_MMU_TTB_READ() sh3_mmu_ttb_read()
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#define SH_MMU_TTB_WRITE(x) sh3_mmu_ttb_write(x)
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#elif defined(SH4)
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#define SH_MMU_TTB_READ() sh4_mmu_ttb_read()
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#define SH_MMU_TTB_WRITE(x) sh4_mmu_ttb_write(x)
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#endif
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/*
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* some macros for pte access.
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*/
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#define SH_MMU_PD_TOP() ((u_long *)SH_MMU_PD_AREA(SH_MMU_TTB_READ()))
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#define SH_MMU_PDE(pd, i) ((u_long *)SH_MMU_PD_AREA((pd)[(i)]))
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#include <sh3/mmu_sh3.h>
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#include <sh3/mmu_sh4.h>
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#endif /* !_SH3_MMU_H_ */
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