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Add new MMU API. for detail, see sh3/mmu.h's comment.

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This commit is contained in:
uch 2002-02-17 20:55:50 +00:00
parent 779bf563f4
commit 780de330ba
15 changed files with 1106 additions and 393 deletions
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9
sys/arch/sh3/conf/files.sh3
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@ -1,4 +1,4 @@
# $NetBSD: files.sh3,v 1.15 2002/02/11 18:03:05 uch Exp $
# $NetBSD: files.sh3,v 1.16 2002/02/17 20:55:59 uch Exp $
#
# new style config file for sh3 architecture
#
@ -24,8 +24,11 @@ file arch/sh3/sh3/sys_machdep.c
file arch/sh3/sh3/trap.c
file arch/sh3/sh3/vm_machdep.c
file arch/sh3/sh3/cache.c
file arch/sh3/sh3/cache_sh3.c
file arch/sh3/sh3/cache_sh4.c
file arch/sh3/sh3/cache_sh3.c sh3
file arch/sh3/sh3/cache_sh4.c sh4
file arch/sh3/sh3/mmu.c
file arch/sh3/sh3/mmu_sh3.c sh3
file arch/sh3/sh3/mmu_sh4.c sh4
file dev/clock_subr.c
file dev/cninit.c
file dev/cons.c

10
sys/arch/sh3/include/cpu.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.15 2002/02/12 15:26:47 uch Exp $ */
/* $NetBSD: cpu.h,v 1.16 2002/02/17 20:55:52 uch Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -173,17 +173,12 @@ do { \
*/
#include <machine/cputypes.h>
#ifdef _KERNEL
extern int cpu;
extern int cpu_class;
extern struct cpu_nocpuid_nameclass sh3_nocpuid_cpus[];
extern struct cpu_cpuid_nameclass sh3_cpuid_cpus[];
/* autoconf.c */
void configure(void);
/* sh3_machdep.c */
void sh_cpu_init(int, int);
void sh3_startup(void);
/* machdep.c */
@ -197,7 +192,6 @@ void lgdt(struct region_descriptor *);
void fillw(short, void *, size_t);
void bcopyb (caddr_t, caddr_t, size_t);
void bcopyw(caddr_t, caddr_t, size_t);
void setPageDirReg(int);
struct pcb;
void savectx(struct pcb *);

38
sys/arch/sh3/include/cpufunc.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpufunc.h,v 1.10 2002/02/12 15:26:48 uch Exp $ */
/* $NetBSD: cpufunc.h,v 1.11 2002/02/17 20:55:52 uch Exp $ */
/*
* Copyright (c) 1993 Charles Hannum.
@ -45,7 +45,6 @@
#include <sys/cdefs.h>
#include <sys/types.h>
#include <sh3/mmureg.h>
#ifdef _KERNEL
@ -56,44 +55,15 @@ static __inline void breakpoint(void);
/*
* memory-mapped register access method.
*/
#define _wb_flush() /* not required */
#define _reg_read_1(a) (*(__volatile__ u_int8_t *)((vaddr_t)(a)))
#define _reg_read_2(a) (*(__volatile__ u_int16_t *)((vaddr_t)(a)))
#define _reg_read_4(a) (*(__volatile__ u_int32_t *)((vaddr_t)(a)))
#define _reg_write_1(a, v) \
{ \
*(__volatile__ u_int8_t *)(a) = (u_int8_t)(v); \
_wb_flush(); \
}
(*(__volatile__ u_int8_t *)(a) = (u_int8_t)(v))
#define _reg_write_2(a, v) \
{ \
*(__volatile__ u_int16_t *)(a) = (u_int16_t)(v); \
_wb_flush(); \
}
(*(__volatile__ u_int16_t *)(a) = (u_int16_t)(v))
#define _reg_write_4(a, v) \
{ \
*(__volatile__ u_int32_t *)(a) = (u_int32_t)(v); \
_wb_flush(); \
}
static __inline void
tlbflush(void)
{
#ifdef SH4
SHREG_MMUCR = (SHREG_MMUCR | MMUCR_TF) & MMUCR_VALIDBITS;
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
__asm __volatile("nop");
#else
SHREG_MMUCR |= MMUCR_TF;
#endif
}
(*(__volatile__ u_int32_t *)(a) = (u_int32_t)(v))
/* XXXX ought to be in psl.h with spl() functions */

186
sys/arch/sh3/include/mmu.h Normal file
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@ -0,0 +1,186 @@
/* $NetBSD: mmu.h,v 1.1 2002/02/17 20:55:50 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by UCHIYAMA Yasushi.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SH3_MMU_H_
#define _SH3_MMU_H_
/*
* Initialize routines.
* sh_mmu_init Assign function vector, and register addresses.
* Don't access hardware.
* Call as possible as first.
* sh_mmu_start Reset TLB entry, set default ASID, and start to
* translate address.
* Call after exception vector was installed.
*
* TLB access ops.
* sh_tlb_invalidate_addr invalidate TLB entris for given
* virtual addr with ASID.
* sh_tlb_invalidate_asid invalidate TLB entries for given ASID.
* sh_tlb_invalidate_all invalidate all non-wired TLB entries. //sana
* sh_tlb_reset invalidate all TLB entries.
* sh_tlb_set_asid set ASID to PTEH
*
* Page table acess ops. (for current NetBSD/sh3 implementation)
*
*/
extern void sh_mmu_init(void);
extern void (*__sh_mmu_start)(void);
extern void sh3_mmu_start(void);
extern void sh4_mmu_start(void);
#define sh_mmu_start() (*__sh_mmu_start)()
extern void sh_tlb_set_asid(int);
extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t);
extern void (*__sh_tlb_invalidate_asid)(int);
extern void (*__sh_tlb_invalidate_all)(void);
extern void (*__sh_tlb_reset)(void);
extern void sh3_tlb_invalidate_addr(int, vaddr_t);
extern void sh3_tlb_invalidate_asid(int);
extern void sh3_tlb_invalidate_all(void);
extern void sh3_tlb_reset(void);
extern void sh4_tlb_invalidate_addr(int, vaddr_t);
extern void sh4_tlb_invalidate_asid(int);
extern void sh4_tlb_invalidate_all(void);
extern void sh4_tlb_reset(void);
#if defined(SH3) && defined(SH4)
#define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va)
#define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a)
#define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)()
#define sh_tlb_reset() (*__sh_tlb_reset)()
#elif defined(SH3)
#define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va)
#define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a)
#define sh_tlb_invalidate_all() sh3_tlb_invalidate_all()
#define sh_tlb_reset() sh3_tlb_reset()
#elif defined(SH4)
#define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va)
#define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a)
#define sh_tlb_invalidate_all() sh4_tlb_invalidate_all()
#define sh_tlb_reset() sh4_tlb_reset()
#endif
/*
* MMU and page table entry access ops.
*/
#if defined(SH3) && defined(SH4)
extern u_int32_t __sh_PTEH;
extern u_int32_t __sh_TTB;
extern u_int32_t __sh_TEA;
extern u_int32_t __sh_TRA;
extern u_int32_t __sh_EXPEVT;
extern u_int32_t __sh_INTEVT;
#define SH_PTEH (*(__volatile__ u_int32_t *)__sh_PTEH)
#define SH_TTB (*(__volatile__ u_int32_t *)__sh_TTB)
#define SH_TEA (*(__volatile__ u_int32_t *)__sh_TEA)
#define SH_TRA (*(__volatile__ u_int32_t *)__sh_TRA)
#define SH_EXPEVT (*(__volatile__ u_int32_t *)__sh_EXPEVT)
#define SH_INTEVT (*(__volatile__ u_int32_t *)__sh_INTEVT)
#elif defined(SH3)
#define SH_PTEH (*(__volatile__ u_int32_t *)SH3_PTEH)
#define SH_TTB (*(__volatile__ u_int32_t *)SH3_TTB)
#define SH_TEA (*(__volatile__ u_int32_t *)SH3_TEA)
#define SH_TRA (*(__volatile__ u_int32_t *)0xffffffd0)
#define SH_EXPEVT (*(__volatile__ u_int32_t *)0xffffffd4)
#define SH_INTEVT (*(__volatile__ u_int32_t *)0xffffffd8)
#elif defined(SH4)
#define SH_PTEH (*(__volatile__ u_int32_t *)SH4_PTEH)
#define SH_TTB (*(__volatile__ u_int32_t *)SH4_TTB)
#define SH_TEA (*(__volatile__ u_int32_t *)SH4_TEA)
#define SH_TRA (*(__volatile__ u_int32_t *)0xff000020)
#define SH_EXPEVT (*(__volatile__ u_int32_t *)0xff000024)
#define SH_INTEVT (*(__volatile__ u_int32_t *)0xff000028)
#endif
extern void (*__sh_mmu_pte_setup)(vaddr_t, u_int32_t);
extern void sh3_mmu_pte_setup(vaddr_t, u_int32_t);
extern void sh4_mmu_pte_setup(vaddr_t, u_int32_t);
#if defined(SH3) && defined(SH4)
#define SH_MMU_PTE_SETUP(v, pte) (*__sh_mmu_pte_setup)((v), (pte))
#elif defined(SH3)
#define SH_MMU_PTE_SETUP(v, pte) sh3_mmu_pte_setup((v), (pte))
#elif defined(SH4)
#define SH_MMU_PTE_SETUP(v, pte) sh4_mmu_pte_setup((v), (pte))
#endif
/*
* SH3 port access pte from P1, SH4 port access it from P2.
*/
extern u_int32_t (*__sh_mmu_pd_area)(u_int32_t);
extern u_int32_t __sh3_mmu_pd_area(u_int32_t);
extern u_int32_t __sh4_mmu_pd_area(u_int32_t);
#if defined(SH3) && defined(SH4)
#define SH_MMU_PD_AREA(x) __sh_mmu_pd_area(x)
#elif defined(SH3)
#define SH_MMU_PD_AREA(x) (x)
#elif defined(SH4)
#define SH_MMU_PD_AREA(x) SH3_P1SEG_TO_P2SEG(x)
#endif
/*
* TTB stores pte entry start address.
*/
extern u_int32_t (*__sh_mmu_ttb_read)(void);
extern void (*__sh_mmu_ttb_write)(u_int32_t);
extern u_int32_t sh3_mmu_ttb_read(void);
extern void sh3_mmu_ttb_write(u_int32_t);
extern u_int32_t sh4_mmu_ttb_read(void);
extern void sh4_mmu_ttb_write(u_int32_t);
#if defined(SH3) && defined(SH4)
#define SH_MMU_TTB_READ() (*__sh_mmu_ttb_read)()
#define SH_MMU_TTB_WRITE(x) (*__sh_mmu_ttb_write)(x)
#elif defined(SH3)
#define SH_MMU_TTB_READ() sh3_mmu_ttb_read()
#define SH_MMU_TTB_WRITE(x) sh3_mmu_ttb_write(x)
#elif defined(SH4)
#define SH_MMU_TTB_READ() sh4_mmu_ttb_read()
#define SH_MMU_TTB_WRITE(x) sh4_mmu_ttb_write(x)
#endif
/*
* some macros for pte access.
*/
#define SH_MMU_PD_TOP() ((u_long *)SH_MMU_PD_AREA(SH_MMU_TTB_READ()))
#define SH_MMU_PDE(pd, i) ((u_long *)SH_MMU_PD_AREA((pd)[(i)]))
#include <sh3/mmu_sh3.h>
#include <sh3/mmu_sh4.h>
#endif /* !_SH3_MMU_H_ */

87
sys/arch/sh3/include/mmu_sh3.h Normal file
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@ -0,0 +1,87 @@
/* $NetBSD: mmu_sh3.h,v 1.1 2002/02/17 20:55:51 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by UCHIYAMA Yasushi.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SH3_MMU_SH3_H_
#define _SH3_MMU_SH3_H_
/* 128-entry 4-way set-associative */
#define SH3_MMU_WAY 4
#define SH3_MMU_ENTRY 32
#define SH3_PTEH 0xfffffff0
#define SH3_PTEH_ASID_MASK 0x0000000f
#define SH3_PTEH_VPN_MASK 0xfffffc00
#define SH3_PTEL 0xfffffff4
#define SH3_PTEL_HWBITS 0x1ffff17e /* [28:12][8][6:1] */
#define SH3_TTB 0xfffffff8
#define SH3_TEA 0xfffffffc
#define SH3_MMUCR 0xffffffe0
#define SH3_MMUCR_AT 0x00000001
#define SH3_MMUCR_IX 0x00000002
#define SH3_MMUCR_TF 0x00000004
#define SH3_MMUCR_RC 0x00000030
#define SH3_MMUCR_SV 0x00000100
/*
* memory-mapped TLB
*/
/* Address array */
#define SH3_MMUAA 0xf2000000
/* address specification */
#define SH3_MMU_VPN_SHIFT 12
#define SH3_MMU_VPN_MASK 0x0001f000 /* [16:12] */
#define SH3_MMU_WAY_SHIFT 8
#define SH3_MMU_WAY_MASK 0x00000300 /* [9:8] */
/* data specification */
#define SH3_MMU_D_VALID 0x00000100
#define SH3_MMUAA_D_VPN_MASK_1K 0xfffe0c00 /* [31:17][11:10] */
#define SH3_MMUAA_D_VPN_MASK_4K 0xfffe0000 /* [31:17] */
#define SH3_MMUAA_D_ASID_MASK 0x0000000f
/* Data array */
#define SH3_MMUDA 0xf3000000
#define SH3_MMUDA_D_PPN_MASK 0xfffffc00
#define SH3_MMUDA_D_V 0x00000100
#define SH3_MMUDA_D_PR_SHIFT 5
#define SH3_MMUDA_D_PR_MASK 0x00000060 /* [6:5] */
#define SH3_MMUDA_D_SZ 0x00000010
#define SH3_MMUDA_D_C 0x00000008
#define SH3_MMUDA_D_D 0x00000004
#define SH3_MMUDA_D_SH 0x00000002
#endif /* !_SH3_MMU_SH3_H_ */

151
sys/arch/sh3/include/mmu_sh4.h Normal file
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@ -0,0 +1,151 @@
/* $NetBSD: mmu_sh4.h,v 1.1 2002/02/17 20:55:51 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by UCHIYAMA Yasushi.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _SH3_MMU_SH4_H_
#define _SH3_MMU_SH4_H_
/* ITLB 4-entry full-associative UTLB 64-entry full-associative */
#define SH4_PTEH 0xff000000
#define SH4_PTEH_VPN_MASK 0xfffffc00
#define SH4_PTEH_ASID_MASK 0x0000000f
#define SH4_PTEL 0xff000004
#define SH4_PTEL_WT 0x00000001
#define SH4_PTEL_SH 0x00000002
#define SH4_PTEL_D 0x00000004
#define SH4_PTEL_C 0x00000008
#define SH4_PTEL_PR_SHIFT 5
#define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */
#define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */
#define SH4_PTEL_SZ_1K 0x00000000
#define SH4_PTEL_SZ_4K 0x00000010
#define SH4_PTEL_SZ_64K 0x00000080
#define SH4_PTEL_SZ_1M 0x00000090
#define SH4_PTEL_V 0x00000100
#define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */
#define SH4_PTEA 0xff000034
#define SH4_PTEA_SA_MASK 0x00000007
#define SH4_PTEA_SA_TC 0x00000008
#define SH4_TTB 0xff000008
#define SH4_TEA 0xff00000c
#define SH4_MMUCR 0xff000010
#define SH4_MMUCR_AT 0x00000001
#define SH4_MMUCR_TI 0x00000004
#define SH4_MMUCR_SV 0x00000100
#define SH4_MMUCR_SQMD 0x00000200
#define SH4_MMUCR_URC_SHIFT 10
#define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */
#define SH4_MMUCR_URB_SHIFT 18
#define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */
#define SH4_MMUCR_LRUI_SHIFT 26
#define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */
#define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \
SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT)
/*
* memory-mapped TLB
* must be access from P2-area program.
* branch to the other area must be maed at least 8 instruction
* after access.
*/
#define SH4_ITLB_ENTRY 4
#define SH4_UTLB_ENTRY 64
/* ITLB */
#define SH4_ITLB_AA 0xf2000000
/* address specification (common for address and data array(0,1)) */
#define SH4_ITLB_E_SHIFT 8
#define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */
/* data specification */
/* address-array */
#define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */
#define SH4_ITLB_AA_V 0x00000100
#define SH4_ITLB_AA_VPN_SHIFT 10
#define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
/* data-array 1 */
#define SH4_ITLB_DA1 0xf3000000
#define SH4_ITLB_DA1_SH 0x00000002
#define SH4_ITLB_DA1_C 0x00000008
#define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
#define SH4_ITLB_DA1_SZ_1K 0x00000000
#define SH4_ITLB_DA1_SZ_4K 0x00000010
#define SH4_ITLB_DA1_SZ_64K 0x00000080
#define SH4_ITLB_DA1_SZ_1M 0x00000090
#define SH4_ITLB_DA1_PR 0x00000040
#define SH4_ITLB_DA1_V 0x00000100
#define SH4_ITLB_DA1_PPN_SHIFT 11
#define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
/* data-array 2 */
#define SH4_ITLB_DA2 0xf3800000
#define SH4_ITLB_DA2_SA_MASK 0x00000003
#define SH4_ITLB_DA2_TC 0x00000004
/* UTLB */
#define SH4_UTLB_AA 0xf6000000
/* address specification (common for address and data array(0,1)) */
#define SH4_UTLB_E_SHIFT 8
#define SH4_UTLB_E_MASK 0x00003f00
#define SH4_UTLB_A 0x00000080
/* data specification */
/* address-array */
#define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
#define SH4_UTLB_AA_D 0x00000200
#define SH4_UTLB_AA_V 0x00000100
#define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */
/* data-array 1 */
#define SH4_UTLB_DA1 0xf7000000
#define SH4_UTLB_DA1_WT 0x00000001
#define SH4_UTLB_DA1_SH 0x00000002
#define SH4_UTLB_DA1_D 0x00000004
#define SH4_UTLB_DA1_C 0x00000008
#define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
#define SH4_UTLB_DA1_SZ_1K 0x00000000
#define SH4_UTLB_DA1_SZ_4K 0x00000010
#define SH4_UTLB_DA1_SZ_64K 0x00000080
#define SH4_UTLB_DA1_SZ_1M 0x00000090
#define SH4_UTLB_DA1_PR_SHIFT 5
#define SH4_UTLB_DA1_PR_MASK 0x00000060
#define SH4_UTLB_DA1_V 0x00000100
#define SH4_UTLB_DA1_PPN_SHIFT 11
#define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
/* data-array 2 */
#define SH4_UTLB_DA2 0xf7800000
#define SH4_UTLB_DA2_SA_MASK 0x00000003
#define SH4_UTLB_DA2_TC 0x00000004
#endif !_SH3_MMU_SH4_H_

159
sys/arch/sh3/include/mmureg.h
View File

@ -1,7 +1,6 @@
/* $NetBSD: mmureg.h,v 1.6 2002/02/11 18:03:48 uch Exp $ */
/* $NetBSD: mmureg.h,v 1.7 2002/02/17 20:55:52 uch Exp $ */
/*-
* Copyright (C) 2002 UCHIYAMA Yasushi. All rights reserved.
* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -81,161 +80,5 @@
#endif /* !SH4 */
extern int PageDirReg;
/*
* name-space free version.
*/
/*
* SH3
*/
/* 128-entry 4-way set-associative */
#define SH3_MMU_WAY 4
#define SH3_MMU_ENTRY 32
#define SH3_PTEH 0xfffffff0
#define SH3_PTEH_ASID_MASK 0x0000000f
#define SH3_PTEH_VPN_MASK 0xfffffc00
#define SH3_PTEL 0xfffffff4
#define SH3_PTEL_HWBITS 0x1ffff17e /* [28:12][8][6:1] */
#define SH3_TTB 0xfffffff8
#define SH3_TEA 0xfffffffc
#define SH3_MMUCR 0xffffffe0
#define SH3_MMUCR_AT 0x00000001
#define SH3_MMUCR_IX 0x00000002
#define SH3_MMUCR_TF 0x00000004
#define SH3_MMUCR_RC 0x00000030
#define SH3_MMUCR_SV 0x00000100
/*
* memory-mapped TLB
*/
/* Address array */
#define SH3_MMUAA 0xf2000000
/* address specification */
#define SH3_MMU_VPN_SHIFT 12
#define SH3_MMU_VPN_MASK 0x0001f000 /* [16:12] */
#define SH3_MMU_WAY_SHIFT 8
#define SH3_MMU_WAY_MASK 0x00000300
/* data specification */
#define SH3_MMU_D_VALID 0x00000100
#define SH3_MMUAA_D_VPN_MASK 0xfffe0c00 /* [31:17][11:10] */
#define SH3_MMUAA_D_ASID_MASK 0x0000000f
/* Data array */
#define SH3_MMUDA 0xf3000000
#define SH3_MMUDA_D_PPN_MASK 0xfffffc00
#define SH3_MMUDA_D_V 0x00000100
#define SH3_MMUDA_D_PR_SHIFT 5
#define SH3_MMUDA_D_PR_MASK 0x00000060 /* [6:5] */
#define SH3_MMUDA_D_SZ 0x00000010
#define SH3_MMUDA_D_C 0x00000008
#define SH3_MMUDA_D_D 0x00000004
#define SH3_MMUDA_D_SH 0x00000002
/*
* SH4
*/
/* ITLB 4-entry full-associative UTLB 64-entry full-associative */
#define SH4_PTEH 0xff000000
#define SH4_PTEH_ASID_MASK 0x0000000f
#define SH4_PTEL 0xff000004
#define SH4_PTEL_WT 0x00000001
#define SH4_PTEL_SH 0x00000002
#define SH4_PTEL_D 0x00000004
#define SH4_PTEL_C 0x00000008
#define SH4_PTEL_PR_SHIFT 5
#define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */
#define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */
#define SH4_PTEL_SZ_1K 0x00000000
#define SH4_PTEL_SZ_4K 0x00000010
#define SH4_PTEL_SZ_64K 0x00000080
#define SH4_PTEL_SZ_1M 0x00000090
#define SH4_PTEL_V 0x00000100
#define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */
#define SH4_PTEA 0xff000034
#define SH4_PTEA_SA_MASK 0x00000007
#define SH4_PTEA_SA_TC 0x00000008
#define SH4_TTB 0xff000008
#define SH4_TTA 0xff00000c
#define SH4_MMUCR 0xff000010
#define SH4_MMUCR_AT 0x00000001
#define SH4_MMUCR_TI 0x00000004
#define SH4_MMUCR_SV 0x00000100
#define SH4_MMUCR_SQMD 0x00000200
#define SH4_MMUCR_URC_SHIFT 10
#define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */
#define SH4_MMUCR_URB_SHIFT 18
#define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */
#define SH4_MMUCR_LRUI_SHIFT 26
#define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */
/*
* memory-mapped TLB
* must be access from P2-area program.
* branch to the other area must be maed at least 8 instruction
* after access.
*/
/* ITLB */
#define SH4_ITLB_AA 0xf2000000
/* address specification (common for address and data array(0,1)) */
#define SH4_ITLB_E_SHIFT 8
#define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */
/* data specification */
/* address-array */
#define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */
#define SH4_ITLB_AA_V 0x00000100
#define SH4_ITLB_AA_VPN_SHIFT 10
#define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
/* data-array 1 */
#define SH4_ITLB_DA1 0xf3000000
#define SH4_ITLB_DA1_SH 0x00000002
#define SH4_ITLB_DA1_C 0x00000008
#define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
#define SH4_ITLB_DA1_SZ_1K 0x00000000
#define SH4_ITLB_DA1_SZ_4K 0x00000010
#define SH4_ITLB_DA1_SZ_64K 0x00000080
#define SH4_ITLB_DA1_SZ_1M 0x00000090
#define SH4_ITLB_DA1_PR 0x00000040
#define SH4_ITLB_DA1_V 0x00000100
#define SH4_ITLB_DA1_PPN_SHIFT 11
#define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
/* data-array 2 */
#define SH4_ITLB_DA2 0xf3800000
#define SH4_ITLB_DA2_SA_MASK 0x00000003
#define SH4_ITLB_DA2_TC 0x00000004
/* UTLB */
#define SH4_UTLB_AA 0xf6000000
/* address specification (common for address and data array(0,1)) */
#define SH4_UTLB_E_SHIFT 8
#define SH4_UTLB_E_MASK 0x00003f00
/* data specification */
/* address-array */
#define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
#define SH4_UTLB_AA_D 0x00000200
#define SH4_UTLB_AA_V 0x00000100
#define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */
/* data-array 1 */
#define SH4_UTLB_DA1 0xf7000000
#define SH4_UTLB_DA1_WT 0x00000001
#define SH4_UTLB_DA1_SH 0x00000002
#define SH4_UTLB_DA1_D 0x00000004
#define SH4_UTLB_DA1_C 0x00000008
#define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
#define SH4_UTLB_DA1_SZ_1K 0x00000000
#define SH4_UTLB_DA1_SZ_4K 0x00000010
#define SH4_UTLB_DA1_SZ_64K 0x00000080
#define SH4_UTLB_DA1_SZ_1M 0x00000090
#define SH4_UTLB_DA1_PR_SHIFT 5
#define SH4_UTLB_DA1_PR_MASK 0x00000060
#define SH4_UTLB_DA1_V 0x00000100
#define SH4_UTLB_DA1_PPN_SHIFT 11
#define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
/* data-array 2 */
#define SH4_UTLB_DA2 0xf7800000
#define SH4_UTLB_DA2_SA_MASK 0x00000003
#define SH4_UTLB_DA2_TC 0x00000004
#endif /* _KERNEL */
#endif /* !_SH3_MMUREG_H__ */

88
sys/arch/sh3/include/pmap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.16 2002/02/12 15:26:48 uch Exp $ */
/* $NetBSD: pmap.h,v 1.17 2002/02/17 20:55:52 uch Exp $ */
/*
* Copyright (c) 1997 Charles D. Cranor and Washington University.
@ -354,13 +354,6 @@ extern int pmap_pg_g; /* do we support PG_G? */
* macros
*/
/* XXX XXX XXX */
#ifdef SH4
#define TLBFLUSH() (cacheflush(), tlbflush())
#else
#define TLBFLUSH() tlbflush()
#endif
#define pmap_kernel() (&kernel_pmap_store)
#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
@ -384,14 +377,14 @@ void pmap_bootstrap(vaddr_t);
boolean_t pmap_change_attrs(struct vm_page *, int, int);
void pmap_deactivate(struct proc *);
void pmap_page_remove (struct vm_page *);
static void pmap_protect(struct pmap *, vaddr_t,
void pmap_protect(struct pmap *, vaddr_t,
vaddr_t, vm_prot_t);
void pmap_remove(struct pmap *, vaddr_t, vaddr_t);
boolean_t pmap_test_attrs(struct vm_page *, int);
void pmap_transfer(struct pmap *, struct pmap *, vaddr_t,
vsize_t, vaddr_t, boolean_t);
static void pmap_update_pg(vaddr_t);
static void pmap_update_2pg(vaddr_t,vaddr_t);
void pmap_update_pg(vaddr_t);
void pmap_update_2pg(vaddr_t,vaddr_t);
void pmap_write_protect(struct pmap *, vaddr_t,
vaddr_t, vm_prot_t);
@ -419,82 +412,9 @@ vaddr_t reserve_dumppages(vaddr_t); /* XXX: not a pmap fn */
#define PMAP_UNMAP_POOLPAGE(va) (va)
#endif
/*
* inline functions
*/
/*
* pmap_update_pg: flush one page from the TLB
*/
__inline static void
pmap_update_pg(vaddr_t va)
{
#ifdef SH4
#if 1
tlbflush();
cacheflush();
#else
u_int32_t *addr, data;
addr = (void *)(0xf6000080 | (va & 0x00003f00)); /* 13-8 */
data = (0x00000000 | (va & 0xfffff000)); /* 31-17, 11-10 */
*addr = data;
#endif
#else
u_int32_t *addr, data;
addr = (void *)(0xf2000080 | (va & 0x0001f000)); /* 16-12 */
data = (0x00000000 | (va & 0xfffe0c00)); /* 31-17, 11-10 */
*addr = data;
#endif
}
/*
* pmap_update_2pg: flush two pages from the TLB
*/
__inline static void
pmap_update_2pg(va, vb)
vaddr_t va, vb;
{
#ifdef SH4
tlbflush();
cacheflush();
#else
pmap_update_pg(va);
pmap_update_pg(vb);
#endif
}
/*
* pmap_protect: change the protection of pages in a pmap
*
* => this function is a frontend for pmap_remove/pmap_write_protect
* => we only have to worry about making the page more protected.
* unprotecting a page is done on-demand at fault time.
*/
__inline static void
pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
{
if ((prot & VM_PROT_WRITE) == 0) {
if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
pmap_write_protect(pmap, sva, eva, prot);
} else {
pmap_remove(pmap, sva, eva);
}
}
}
vaddr_t pmap_map(vaddr_t, paddr_t, paddr_t, vm_prot_t);
paddr_t vtophys(vaddr_t);
void pmap_emulate_reference(struct proc *, vaddr_t, int, int);
/* XXX */
#define PG_U 0 /* referenced bit */
#endif /* _KERNEL */
#endif /* _SH3_PMAP_H_ */

4
sys/arch/sh3/include/pte.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pte.h,v 1.5 2002/02/11 18:06:06 uch Exp $ */
/* $NetBSD: pte.h,v 1.6 2002/02/17 20:55:52 uch Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@ -106,6 +106,8 @@ typedef int pt_entry_t; /* Mach page table entry */
/*
* Software bits
*/
/* XXX referece bit is not emulated. */
#define PG_U 0 /* referenced bit */
#define PG_W 0x00000080 /* page is wired */
#define PG_PVLIST 0x00000001 /* mapping has entry on pvlist */
/* SH4 PCMCIA MMU support bits */

268
sys/arch/sh3/sh3/mmu.c Normal file
View File

@ -0,0 +1,268 @@
/* $NetBSD: mmu.c,v 1.1 2002/02/17 20:55:56 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by UCHIYAMA Yasushi.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sh3/cpufunc.h>
#include <sh3/pte.h>
#include <sh3/cache.h>
#include <sh3/mmu.h>
#include <sh3/mmu_sh3.h>
#include <sh3/mmu_sh4.h>
/* Start MMU. call after exception vector is setuped. */
void (*__sh_mmu_start)(void);
/* TLB functions */
void (*__sh_tlb_invalidate_addr)(int, vaddr_t);
void (*__sh_tlb_invalidate_asid)(int);
void (*__sh_tlb_invalidate_all)(void);
void (*__sh_tlb_reset)(void);
/* TTB access */
u_int32_t (*__sh_mmu_ttb_read)(void);
void (*__sh_mmu_ttb_write)(u_int32_t);
/* PTEL, PTEA access */
void (*__sh_mmu_pte_setup)(vaddr_t, u_int32_t);
/* Page table method (software) */
vaddr_t sh3_mmu_pt_p1addr(vaddr_t);
vaddr_t sh4_mmu_pt_p2addr(vaddr_t);
vaddr_t (*__sh_mmu_pt_kaddr)(vaddr_t);
u_int32_t (*__sh_mmu_pd_area)(u_int32_t);
/* register addresses for (SH3 && SH4) */
u_int32_t __sh_PTEH;
u_int32_t __sh_TTB;
u_int32_t __sh_TEA;
u_int32_t __sh_TRA;
u_int32_t __sh_EXPEVT;
u_int32_t __sh_INTEVT;
void
sh_mmu_init()
{
/*
* Assing function hook. but if only defined SH3 or SH4, it is called
* directly. see sh3/mmu.h
*/
if (CPU_IS_SH3) {
__sh_mmu_start = sh3_mmu_start;
__sh_tlb_invalidate_addr = sh3_tlb_invalidate_addr;
__sh_tlb_invalidate_asid = sh3_tlb_invalidate_asid;
__sh_tlb_invalidate_all = sh3_tlb_invalidate_all;
__sh_tlb_reset = sh3_tlb_reset;
__sh_mmu_pt_kaddr = sh3_mmu_pt_p1addr;
__sh_mmu_pte_setup = sh3_mmu_pte_setup;
__sh_mmu_ttb_read = sh3_mmu_ttb_read;
__sh_mmu_ttb_write = sh3_mmu_ttb_write;
__sh_mmu_pd_area = __sh3_mmu_pd_area;
__sh_PTEH = SH3_PTEH;
__sh_TEA = SH3_TEA;
__sh_TTB = SH3_TTB;
__sh_TRA = 0xffffffd0;
__sh_EXPEVT = 0xffffffd4;
__sh_INTEVT = 0xffffffd8;
} else {
__sh_mmu_start = sh4_mmu_start;
__sh_tlb_invalidate_addr = sh4_tlb_invalidate_addr;
__sh_tlb_invalidate_asid = sh4_tlb_invalidate_asid;
__sh_tlb_invalidate_all = sh4_tlb_invalidate_all;
__sh_tlb_reset = sh4_tlb_reset;
__sh_mmu_pt_kaddr = sh4_mmu_pt_p2addr;
__sh_mmu_pte_setup = sh4_mmu_pte_setup;
__sh_mmu_ttb_read = sh4_mmu_ttb_read;
__sh_mmu_ttb_write = sh4_mmu_ttb_write;
__sh_mmu_pd_area = __sh4_mmu_pd_area;
__sh_PTEH = SH4_PTEH;
__sh_TEA = SH4_TEA;
__sh_TTB = SH4_TTB;
__sh_TRA = 0xff000020;
__sh_EXPEVT = 0xff000024;
__sh_INTEVT = 0xff000028;
}
}
void
sh_tlb_set_asid(int asid)
{
_reg_write_4(__sh_PTEH, 0);
}
#ifdef SH3
u_int32_t
__sh3_mmu_pd_area(u_int32_t a)
{
return (a);
}
#endif /* SH3 */
#ifdef SH4
u_int32_t
__sh4_mmu_pd_area(u_int32_t a)
{
return (SH3_P1SEG_TO_P2SEG(a));
}
#endif /* SH4 */
/*
* TTB
*/
#ifdef SH3
u_int32_t
sh3_mmu_ttb_read()
{
return (_reg_read_4(SH3_TTB));
}
void
sh3_mmu_ttb_write(u_int32_t r)
{
_reg_write_4(SH3_TTB, r);
sh_tlb_invalidate_all();
}
#endif /* SH3 */
#ifdef SH4
u_int32_t
sh4_mmu_ttb_read()
{
return (_reg_read_4(SH4_TTB));
}
void
sh4_mmu_ttb_write(u_int32_t r)
{
_reg_write_4(SH4_TTB, r);
sh_tlb_invalidate_all();
}
#endif /* SH4 */
/*
* Load PTEL, PTEA utility
*/
#ifdef SH3
void
sh3_mmu_pte_setup(vaddr_t va, u_int32_t pte)
{
_reg_write_4(SH3_PTEL, pte & PG_HW_BITS);
}
#endif /* SH3 */
#ifdef SH4
void
sh4_mmu_pte_setup(vaddr_t va, u_int32_t pte)
{
u_int32_t ptel;
ptel = pte & PG_HW_BITS;
if (pte & _PG_PCMCIA) {
_reg_write_4(SH4_PTEA,
(pte >> _PG_PCMCIA_SHIFT) & SH4_PTEA_SA_MASK);
_reg_write_4(SH4_PTEL, ptel & ~PG_N);
} else {
if (va >= SH3_P1SEG_BASE)
ptel |= PG_WT; /* P3SEG is always write-through */
_reg_write_4(SH4_PTEA, 0);
_reg_write_4(SH4_PTEL, ptel);
}
}
#endif /* SH4 */
/*
* Page table utility. will be obsoleted.
*/
#ifdef SH3
/*
* returns P1 address of U0, P0, P1 address.
*/
vaddr_t
sh3_mmu_pt_p1addr(vaddr_t va) /* va = U0, P0, P1 */
{
u_int32_t *pd, *pde, pte;
vaddr_t p1addr;
/* P1SEG */
if ((va & 0xc0000000) == 0x80000000)
return (va);
/* P0/U0SEG */
pd = (u_int32_t *)_reg_read_4(SH3_TTB);
pde = (u_int32_t *)(pd[va >> PDSHIFT] & PG_FRAME);
pte = pde[(va & PT_MASK) >> PGSHIFT];
p1addr = (pte & PG_FRAME) | (va & PGOFSET);
return (p1addr);
}
#endif /* SH3 */
#ifdef SH4
/*
* returns P2 address of U0, P0, P1 address.
*/
vaddr_t
sh4_mmu_pt_p2addr(vaddr_t va) /* va = U0, P0, P1 */
{
u_int32_t *pd, *pde, pte;
vaddr_t p1addr;
sh_dcache_wbinv_all();
/* P1SEG */
if ((va & 0xc0000000) == 0x80000000)
return SH3_P1SEG_TO_P2SEG(va);
/* P0/U0SEG */
pd = (u_int32_t *)SH3_P1SEG_TO_P2SEG(_reg_read_4(SH4_TTB));
pde = (u_int32_t *)SH3_P1SEG_TO_P2SEG((pd[va >> PDSHIFT] & PG_FRAME));
pte = pde[(va & PT_MASK) >> PGSHIFT];
p1addr = (pte & PG_FRAME) | (va & PGOFSET);
return SH3_P1SEG_TO_P2SEG(p1addr);
}
#endif

122
sys/arch/sh3/sh3/mmu_sh3.c Normal file
View File

@ -0,0 +1,122 @@
/* $NetBSD: mmu_sh3.c,v 1.1 2002/02/17 20:55:57 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by UCHIYAMA Yasushi.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sh3/cpufunc.h>
#include <sh3/mmu.h>
#include <sh3/mmu_sh3.h>
void
sh3_mmu_start()
{
/* Zero clear all TLB entry */
sh_tlb_reset();
/* Set current ASID to 0 */
sh_tlb_set_asid(0);
/* Single virtual memory mode. */
_reg_write_4(SH3_MMUCR, SH3_MMUCR_AT | SH3_MMUCR_TF | SH3_MMUCR_SV);
}
void
sh3_tlb_invalidate_addr(int asid, vaddr_t va)
{
u_int32_t r, a, d;
int w;
d = (va & SH3_MMUAA_D_VPN_MASK_4K) | asid; /* 4K page */
va = SH3_MMUAA | (va & SH3_MMU_VPN_MASK); /* [16:12] entry index */
/* Probe entry and invalidate it. */
for (w = 0; w < 4; w++) {
a = va | (w << SH3_MMU_WAY_SHIFT); /* way [9:8] */
r = _reg_read_4(a);
if ((r & (SH3_MMUAA_D_VPN_MASK_4K | SH3_MMUAA_D_ASID_MASK))
== d) {
_reg_write_4(a, 0);
return;
}
}
}
void
sh3_tlb_invalidate_asid(int asid)
{
u_int32_t aw, a;
int e, w;
/* Invalidate entry attribute to ASID */
for (w = 0; w < SH3_MMU_WAY; w++) {
aw = (w << SH3_MMU_WAY_SHIFT);
for (e = 0; e < SH3_MMU_ENTRY; e++) {
a = aw | (e << SH3_MMU_VPN_SHIFT);
if ((_reg_read_4(SH3_MMUAA | a) & SH3_MMUAA_D_ASID_MASK)
== asid)
_reg_write_4(SH3_MMUAA | a, 0);
}
}
}
void
sh3_tlb_invalidate_all()
{
/* SH3 has no wired entry. so merely clear whole V bit */
_reg_write_4(SH3_MMUCR, _reg_read_4(SH3_MMUCR) | SH3_MMUCR_TF);
}
void
sh3_tlb_reset()
{
u_int32_t aw, a;
int e, w;
/* Zero clear all TLB entry */
for (w = 0; w < SH3_MMU_WAY; w++) {
aw = (w << SH3_MMU_WAY_SHIFT);
for (e = 0; e < SH3_MMU_ENTRY; e++) {
a = aw | (e << SH3_MMU_VPN_SHIFT);
_reg_write_4(SH3_MMUAA | a, 0);
_reg_write_4(SH3_MMUDA | a, 0);
}
}
}

146
sys/arch/sh3/sh3/mmu_sh4.c Normal file
View File

@ -0,0 +1,146 @@
/* $NetBSD: mmu_sh4.c,v 1.1 2002/02/17 20:55:57 uch Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by UCHIYAMA Yasushi.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sh3/cpufunc.h>
#include <sh3/mmu.h>
#include <sh3/mmu_sh4.h>
#define SH4_MMU_HAZARD __asm__ __volatile__("nop;nop;nop;nop;nop;nop;nop;nop;")
extern __inline__ void __sh4_itlb_invalidate_all(void);
void
__sh4_itlb_invalidate_all()
{
_reg_write_4(SH4_ITLB_AA, 0);
_reg_write_4(SH4_ITLB_AA | (1 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_ITLB_AA | (2 << SH4_ITLB_E_SHIFT), 0);
_reg_write_4(SH4_ITLB_AA | (3 << SH4_ITLB_E_SHIFT), 0);
}
void
sh4_mmu_start()
{
/* Zero clear all TLB entry */
_reg_write_4(SH4_MMUCR, 0); /* zero wired entry */
sh_tlb_invalidate_all();
/* Set current ASID to 0 */
sh_tlb_set_asid(0);
/* Single virtual memory mode. User can't access store queue */
_reg_write_4(SH4_MMUCR, SH4_MMUCR_AT | SH4_MMUCR_TI | SH4_MMUCR_SV |
SH4_MMUCR_SQMD);
SH4_MMU_HAZARD;
}
void
sh4_tlb_invalidate_addr(int asid, vaddr_t va)
{
u_int32_t pteh;
va &= SH4_PTEH_VPN_MASK;
/* Save current ASID */
pteh = _reg_read_4(SH4_PTEH);
/* Set ASID for associative write */
_reg_write_4(SH4_PTEH, asid);
/* Associative write(UTLB/ITLB). not required ITLB invalidate. */
RUN_P2;
_reg_write_4(SH4_UTLB_AA | SH4_UTLB_A, va); /* Clear D, V */
RUN_P1;
/* Restore ASID */
_reg_write_4(SH4_PTEH, pteh);
}
void
sh4_tlb_invalidate_asid(int asid)
{
u_int32_t a;
int e;
/* Invalidate entry attribute to ASID */
RUN_P2;
for (e = 0; e < SH4_UTLB_ENTRY; e++) {
a = SH4_UTLB_AA | (e << SH4_UTLB_E_SHIFT);
if ((_reg_read_4(a) & SH4_UTLB_AA_ASID_MASK) == asid)
_reg_write_4(a, 0);
}
__sh4_itlb_invalidate_all();
RUN_P1;
}
void
sh4_tlb_invalidate_all()
{
u_int32_t a;
int e, eend;
/* If non-wired entry limit is zero, clear all entry. */
a = _reg_read_4(SH4_MMUCR) & SH4_MMUCR_URB_MASK;
eend = a ? (a >> SH4_MMUCR_URB_SHIFT) : SH4_UTLB_ENTRY;
RUN_P2;
for (e = 0; e < eend; e++) {
a = SH4_UTLB_AA | (e << SH4_UTLB_E_SHIFT);
_reg_write_4(a, 0);
}
__sh4_itlb_invalidate_all();
RUN_P1;
}
void
sh4_tlb_reset()
{
/*
* SH4 MMUCR reserved bit
* read: unknown.
* write: must be 0.
*/
_reg_write_4(SH4_MMUCR,
(_reg_read_4(SH4_MMUCR) & SH4_MMUCR_MASK) | SH4_MMUCR_TI);
SH4_MMU_HAZARD;
}

132
sys/arch/sh3/sh3/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.32 2002/02/12 15:26:50 uch Exp $ */
/* $NetBSD: pmap.c,v 1.33 2002/02/17 20:55:57 uch Exp $ */
/*
* Copyright (c) 1997 Charles D. Cranor and Washington University.
@ -71,6 +71,16 @@
#include <uvm/uvm.h>
#include <machine/cpu.h>
#include <sh3/cache.h>
#include <sh3/mmu.h>
/* XXX XXX XXX */
#ifdef SH4
#define TLBFLUSH() (cacheflush(), sh_tlb_invalidate_all())
#else
#define TLBFLUSH() sh_tlb_invalidate_all()
#endif
/* XXX XXX XXX */
/*
* general info:
@ -409,7 +419,7 @@ pmap_is_curpmap(struct pmap *pmap)
{
return ((pmap == pmap_kernel()) ||
(pmap->pm_pdirpa == (paddr_t)SHREG_TTB));
(pmap->pm_pdirpa == (paddr_t)SH_MMU_TTB_READ()));
}
/*
@ -419,12 +429,14 @@ pmap_is_curpmap(struct pmap *pmap)
__inline static vaddr_t
pmap_tmpmap_pa(paddr_t pa)
{
#ifdef SH4
cacheflush();
return SH3_PHYS_TO_P2SEG(pa);
#else
return SH3_PHYS_TO_P1SEG(pa);
#endif
if (CPU_IS_SH3) {
return SH3_PHYS_TO_P1SEG(pa);
} else {
cacheflush();
return SH3_PHYS_TO_P2SEG(pa);
}
return (0);
}
/*
@ -1664,7 +1676,7 @@ pmap_activate(struct proc *p)
pcb->pcb_pmap = pmap;
pcb->pageDirReg = pmap->pm_pdirpa;
if (p == curproc)
setPageDirReg(pcb->pageDirReg);
SH_MMU_TTB_WRITE(pcb->pageDirReg);
}
/*
@ -1749,12 +1761,13 @@ pmap_map(vaddr_t va, paddr_t spa, paddr_t epa, vm_prot_t prot)
void
pmap_zero_page(paddr_t pa)
{
#ifdef SH4
cacheflush();
memset((void *)SH3_PHYS_TO_P2SEG(pa), 0, NBPG);
#else
memset((void *)SH3_PHYS_TO_P1SEG(pa), 0, NBPG);
#endif
if (CPU_IS_SH3) {
memset((void *)SH3_PHYS_TO_P1SEG(pa), 0, NBPG);
} else {
cacheflush();
memset((void *)SH3_PHYS_TO_P2SEG(pa), 0, NBPG);
}
}
/*
@ -1764,14 +1777,15 @@ pmap_zero_page(paddr_t pa)
void
pmap_copy_page(paddr_t srcpa, paddr_t dstpa)
{
#ifdef SH4
cacheflush();
memcpy((void *)SH3_PHYS_TO_P2SEG(dstpa),
(void *)SH3_PHYS_TO_P2SEG(srcpa), NBPG);
#else
memcpy((void *)SH3_PHYS_TO_P1SEG(dstpa),
(void *)SH3_PHYS_TO_P1SEG(srcpa), NBPG);
#endif
if (CPU_IS_SH3) {
memcpy((void *)SH3_PHYS_TO_P1SEG(dstpa),
(void *)SH3_PHYS_TO_P1SEG(srcpa), NBPG);
} else {
cacheflush();
memcpy((void *)SH3_PHYS_TO_P2SEG(dstpa),
(void *)SH3_PHYS_TO_P2SEG(srcpa), NBPG);
}
}
/*
@ -3441,20 +3455,66 @@ pmap_emulate_reference(struct proc *p, vaddr_t va, int user, int write)
paddr_t
vtophys(vaddr_t va)
{
#ifdef SH4
cacheflush();
if (va >= SH3_P1SEG_BASE && va <= SH3_P2SEG_END)
return (va|SH3_P1234SEG_SIZE);
#else
if (va >= SH3_P1SEG_BASE && va <= SH3_P2SEG_END)
return va;
#endif
if (CPU_IS_SH3) {
if (va >= SH3_P1SEG_BASE && va <= SH3_P2SEG_END)
return va;
} else {
cacheflush();
if (va >= SH3_P1SEG_BASE && va <= SH3_P2SEG_END)
return (va|SH3_P1234SEG_SIZE);
}
/* XXX P4SEG? */
#ifdef SH4
return (*vtopte(va) & PG_FRAME) | (va & ~PG_FRAME) | SH3_P1234SEG_SIZE;
#else
return (*vtopte(va) & PG_FRAME) | (va & ~PG_FRAME);
#endif
return CPU_IS_SH3 ? (*vtopte(va) & PG_FRAME) | (va & ~PG_FRAME) :
(*vtopte(va) & PG_FRAME) | (va & ~PG_FRAME) | SH3_P1234SEG_SIZE;
}
/*
* pmap_update_pg: flush one page from the TLB
*/
void
pmap_update_pg(vaddr_t va)
{
if (CPU_IS_SH3) {
sh_tlb_invalidate_addr(0, va); /* all entries are ASID 0. */
} else {
TLBFLUSH();
}
}
/*
* pmap_update_2pg: flush two pages from the TLB
*/
void
pmap_update_2pg(vaddr_t va, vaddr_t vb)
{
pmap_update_pg(va);
pmap_update_pg(vb);
}
/*
* pmap_protect: change the protection of pages in a pmap
*
* => this function is a frontend for pmap_remove/pmap_write_protect
* => we only have to worry about making the page more protected.
* unprotecting a page is done on-demand at fault time.
*/
void
pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
{
if ((prot & VM_PROT_WRITE) == 0) {
if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
pmap_write_protect(pmap, sva, eva, prot);
} else {
pmap_remove(pmap, sva, eva);
}
}
}

83
sys/arch/sh3/sh3/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.31 2002/02/14 07:08:14 chs Exp $ */
/* $NetBSD: trap.c,v 1.32 2002/02/17 20:55:58 uch Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
@ -66,8 +66,9 @@
#include <uvm/uvm_extern.h>
#include <sh3/mmureg.h>
#include <sh3/trapreg.h>
#include <sh3/mmu.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/psl.h>
@ -81,7 +82,7 @@
#include <sys/kgdb.h>
#endif
char *trap_type[] = {
const char *trap_type[] = {
"power-on", /* 0x000 T_POWERON */
"manual reset", /* 0x020 T_RESET */
"TLB miss/invalid (load)", /* 0x040 T_TLBMISSR */
@ -99,7 +100,7 @@ char *trap_type[] = {
"nonmaskable interrupt", /* 0x1c0 T_NMI */
"user break point trap", /* 0x1e0 T_USERBREAK */
};
int trap_types = sizeof trap_type / sizeof trap_type[0];
const int trap_types = sizeof trap_type / sizeof trap_type[0];
extern int cpu_debug_mode;
int trapdebug = 1;
@ -109,19 +110,6 @@ void trap(int, int, int, int /* dummy 4 param*/, struct trapframe);
int trapwrite(unsigned);
void syscall(struct trapframe *);
void tlb_handler(int, int, int, int /* dummy 4 param */, struct trapframe);
void __setup_pte_sh3(vaddr_t, u_int32_t);
void __setup_pte_sh4(vaddr_t, u_int32_t);
#ifdef SH4
#define __SETUP_PTE(v, pte) __setup_pte_sh4((v), (pte))
#define __PD_AREA(x) SH3_P1SEG_TO_P2SEG(x)
#else /* SH4 */
#define __SETUP_PTE(v, pte) __setup_pte_sh3((v), (pte))
#define __PD_AREA(x) (x)
#endif /* SH4 */
#define __PD_TOP() ((u_long *)__PD_AREA(SHREG_TTB))
#define __PDE(pd, i) ((u_long *)__PD_AREA((pd)[(i)]))
/*
* Define the code needed before returning to user mode, for
@ -157,37 +145,6 @@ userret(struct proc *p, int pc, u_quad_t oticks)
curcpu()->ci_schedstate.spc_curpriority = p->p_priority;
}
/*
* PTEL, PTEA
*/
void
__setup_pte_sh3(vaddr_t va, u_int32_t pte)
{
SHREG_PTEL = pte & PG_HW_BITS;
}
#ifdef SH4
void
__setup_pte_sh4(vaddr_t va, u_int32_t pte)
{
u_int32_t ptel;
ptel = pte & PG_HW_BITS;
if (pte & _PG_PCMCIA) {
SHREG_PTEA = (pte >> _PG_PCMCIA_SHIFT) & SH4_PTEA_SA_MASK;
SHREG_PTEL = ptel & ~PG_N;
} else {
if (va >= SH3_P1SEG_BASE)
ptel |= PG_WT; /* P3SEG is always write-through */
SHREG_PTEL = ptel;
SHREG_PTEA = 0;
}
}
#endif /* SH4 */
/*
* trap(frame):
* Exception, fault, and trap interface to BSD kernel. This
@ -247,7 +204,7 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
/*NOTREACHED*/
case T_TRAP|T_USER:
if (SHREG_TRA == (0x000000c3 << 2)) {
if (SH_TRA == (0x000000c3 << 2)) {
trapsignal(p, SIGTRAP, type &~ T_USER);
break;
} else {
@ -257,7 +214,7 @@ trap(int p1, int p2, int p3, int p4,/* dummy param */ struct trapframe frame)
case T_INITPAGEWR:
case T_INITPAGEWR|T_USER:
va = (vaddr_t)SHREG_TEA;
va = (vaddr_t)SH_TEA;
pmap_emulate_reference(p, va, type & T_USER, 1);
return;
@ -540,12 +497,10 @@ syscall(struct trapframe *frame)
error = 0;
}
//#ifdef TRAP_DEBUG
#ifdef SYSCALL_DEBUG
if (cpu_debug_mode)
scdebug_call(p, code, args);
#endif
//#endif
#ifdef KTRACE
if (KTRPOINT(p, KTR_SYSCALL))
ktrsyscall(p, code, argsize, args);
@ -585,12 +540,10 @@ syscall(struct trapframe *frame)
break;
}
//#ifdef TRAP_DEBUG
#ifdef SYSCALL_DEBUG
if (cpu_debug_mode)
scdebug_ret(p, code, error, rval);
#endif
//#endif
userret(p, frame->tf_spc, sticks);
#ifdef KTRACE
if (KTRPOINT(p, KTR_SYSRET))
@ -643,19 +596,19 @@ tlb_handler(int p1, int p2, int p3, int p4, struct trapframe frame)
uvmexp.traps++;
va = (vaddr_t)SHREG_TEA;
va = (vaddr_t)SH_TEA;
va = trunc_page(va);
pde_index = pdei(va);
pd_top = __PD_TOP();
pde = __PDE(pd_top, pde_index);
exptype = SHREG_EXPEVT;
pd_top = SH_MMU_PD_TOP();
pde = SH_MMU_PDE(pd_top, pde_index);
exptype = SH_EXPEVT;
if (((u_long)pde & PG_V) != 0 && exptype != T_TLBPRIVW) {
(u_long)pde &= ~PGOFSET;
pte_index = ptei(va);
pte = (u_int32_t)__PDE(pde, pte_index);
pte = (u_int32_t)SH_MMU_PDE(pde, pte_index);
if ((pte & PG_V) != 0) {
__SETUP_PTE(va, pte);
SH_MMU_PTE_SETUP(va, pte);
__asm __volatile ("ldtlb; nop");
return;
}
@ -667,7 +620,7 @@ tlb_handler(int p1, int p2, int p3, int p4, struct trapframe frame)
user = !KERNELMODE(frame.tf_r15, frame.tf_ssr);
pteh_save = SHREG_PTEH;
pteh_save = SH_PTEH;
va_save = va;
p = curproc;
if (p == NULL) {
@ -742,10 +695,10 @@ tlb_handler(int p1, int p2, int p3, int p4, struct trapframe frame)
if (rv == 0) {
va = va_save;
SHREG_PTEH = pteh_save;
SH_PTEH = pteh_save;
pde_index = pdei(va);
pd_top = __PD_TOP();
pde = __PDE(pd_top, pde_index);
pd_top = SH_MMU_PD_TOP();
pde = SH_MMU_PDE(pd_top, pde_index);
if (((u_long)pde & PG_V) != 0) {
(u_long)pde &= ~PGOFSET;
@ -753,7 +706,7 @@ tlb_handler(int p1, int p2, int p3, int p4, struct trapframe frame)
pte = pde[pte_index];
if ((pte & PG_V) != 0)
__SETUP_PTE(va, pte);
SH_MMU_PTE_SETUP(va, pte);
}
__asm __volatile("ldtlb; nop");
if (user)

16
sys/arch/sh3/sh3/vm_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: vm_machdep.c,v 1.23 2002/02/12 15:26:51 uch Exp $ */
/* $NetBSD: vm_machdep.c,v 1.24 2002/02/17 20:55:58 uch Exp $ */
/*-
* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
@ -63,6 +63,15 @@
void setredzone(u_short *, caddr_t);
/* XXX XXX XXX */
#include <sh3/mmu.h>
#ifdef SH4
#define TLBFLUSH() (cacheflush(), sh_tlb_invalidate_all())
#else
#define TLBFLUSH() sh_tlb_invalidate_all()
#endif
/* XXX XXX XXX */
/*
* Finish a fork operation, with process p2 nearly set up.
* Copy and update the pcb and trap frame, making the child ready to run.
@ -93,9 +102,8 @@ cpu_fork(struct proc *p1, struct proc *p2, void *stack,
printf("cpu_fork:p1(%p),p2(%p)\n", p1, p2);
#endif
#ifdef SH4
cacheflush();
#endif
if (CPU_IS_SH4)
cacheflush();
p2->p_md.md_flags = p1->p_md.md_flags;