1999-02-19 17:57:00 +03:00
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/* $NetBSD: be.c,v 1.4 1999/02/19 14:57:00 pk Exp $ */
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1999-01-16 15:43:09 +03:00
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include "opt_inet.h"
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#include "opt_ccitt.h"
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#include "opt_llc.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include "rnd.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/netisr.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#endif
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1999-01-18 16:29:01 +03:00
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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1999-01-16 15:43:09 +03:00
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <dev/sbus/sbusvar.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/sbus/qecreg.h>
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#include <dev/sbus/qecvar.h>
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#include <dev/sbus/bereg.h>
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struct be_softc {
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struct device sc_dev;
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struct sbusdev sc_sd; /* sbus device */
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bus_space_tag_t sc_bustag; /* bus & dma tags */
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bus_dma_tag_t sc_dmatag;
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struct ethercom sc_ethercom;
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/*struct ifmedia sc_ifmedia; -* interface media */
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struct mii_data sc_mii; /* MII media control */
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#define sc_media sc_mii.mii_media/* shorthand */
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struct qec_softc *sc_qec; /* QEC parent */
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bus_space_handle_t sc_qr; /* QEC registers */
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bus_space_handle_t sc_br; /* BE registers */
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bus_space_handle_t sc_cr; /* channel registers */
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bus_space_handle_t sc_tr; /* transceiver registers */
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u_int sc_rev;
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int sc_channel; /* channel number */
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int sc_promisc;
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int sc_burst;
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int sc_conf;
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#define BE_CONF_MII 1
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1999-01-17 23:47:50 +03:00
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struct qec_ring sc_rb; /* Packet Ring Buffer */
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1999-01-16 15:43:09 +03:00
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/* MAC address */
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u_int8_t sc_enaddr[6];
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};
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int bematch __P((struct device *, struct cfdata *, void *));
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void beattach __P((struct device *, struct device *, void *));
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void beinit __P((struct be_softc *));
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void bestart __P((struct ifnet *));
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void bestop __P((struct be_softc *));
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void bewatchdog __P((struct ifnet *));
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int beioctl __P((struct ifnet *, u_long, caddr_t));
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void bereset __P((struct be_softc *));
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int beintr __P((void *));
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int berint __P((struct be_softc *));
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int betint __P((struct be_softc *));
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int beqint __P((struct be_softc *, u_int32_t));
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int beeint __P((struct be_softc *, u_int32_t));
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static void be_read __P((struct be_softc *, int, int));
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static int be_put __P((struct be_softc *, int, struct mbuf *));
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static struct mbuf *be_get __P((struct be_softc *, int, int));
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void be_tcvr_init __P((struct be_softc *));
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/* ifmedia callbacks */
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void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
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int be_ifmedia_upd __P((struct ifnet *));
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1999-01-17 23:47:50 +03:00
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1999-01-16 15:43:09 +03:00
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void be_mcreset __P((struct be_softc *));
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/* MII methods & callbacks */
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static int be_mii_readreg __P((struct device *, int, int));
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static void be_mii_writereg __P((struct device *, int, int, int));
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static void be_statchg __P((struct device *));
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/* MII helpers */
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static void be_mii_sync __P((struct be_softc *));
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static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int));
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static int be_mii_reset __P((struct be_softc *, int));
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static int be_tcvr_read_bit __P((struct be_softc *, int));
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static void be_tcvr_write_bit __P((struct be_softc *, int, int));
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void be_tick __P((void *));
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void be_internal_phy_auto __P((struct be_softc *));
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struct cfattach be_ca = {
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sizeof(struct be_softc), bematch, beattach
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};
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int
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bematch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct sbus_attach_args *sa = aux;
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return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
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}
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void
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beattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct sbus_attach_args *sa = aux;
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struct qec_softc *qec = (struct qec_softc *)parent;
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struct be_softc *sc = (struct be_softc *)self;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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struct mii_data *mii = &sc->sc_mii;
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int node = sa->sa_node;
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bus_dma_segment_t seg;
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bus_size_t size;
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int rseg, error;
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extern void myetheraddr __P((u_char *));
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if (sa->sa_nreg < 3) {
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printf("%s: only %d register sets\n",
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self->dv_xname, sa->sa_nreg);
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return;
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}
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if (bus_space_map2(sa->sa_bustag,
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(bus_type_t)sa->sa_reg[0].sbr_slot,
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(bus_addr_t)sa->sa_reg[0].sbr_offset,
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(bus_size_t)sa->sa_reg[0].sbr_size,
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BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) {
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printf("beattach: cannot map registers\n");
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return;
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}
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if (bus_space_map2(sa->sa_bustag,
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(bus_type_t)sa->sa_reg[1].sbr_slot,
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(bus_addr_t)sa->sa_reg[1].sbr_offset,
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(bus_size_t)sa->sa_reg[1].sbr_size,
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BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) {
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printf("beattach: cannot map registers\n");
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return;
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}
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if (bus_space_map2(sa->sa_bustag,
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(bus_type_t)sa->sa_reg[2].sbr_slot,
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(bus_addr_t)sa->sa_reg[2].sbr_offset,
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(bus_size_t)sa->sa_reg[2].sbr_size,
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BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) {
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printf("beattach: cannot map registers\n");
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return;
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}
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sc->sc_qec = qec;
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sc->sc_qr = qec->sc_regs;
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sc->sc_rev = getpropint(node, "board-version", -1);
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printf(" rev %x", sc->sc_rev);
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bestop(sc);
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sc->sc_channel = getpropint(node, "channel#", -1);
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if (sc->sc_channel == -1)
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sc->sc_channel = 0;
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sc->sc_burst = getpropint(node, "burst-sizes", -1);
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if (sc->sc_burst == -1)
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sc->sc_burst = qec->sc_burst;
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/* Clamp at parent's burst sizes */
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sc->sc_burst &= qec->sc_burst;
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(void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 0, beintr, sc);
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myetheraddr(sc->sc_enaddr);
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printf(" address %s\n", ether_sprintf(sc->sc_enaddr));
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/*
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* Allocate descriptor ring and buffers.
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*/
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1999-01-17 23:47:50 +03:00
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/* for now, allocate as many bufs as there are ring descriptors */
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sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
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sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
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1999-01-16 15:43:09 +03:00
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size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
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QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
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1999-01-17 23:47:50 +03:00
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sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ +
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sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ;
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1999-01-16 15:43:09 +03:00
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if ((error = bus_dmamem_alloc(sa->sa_dmatag, size,
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NBPG, 0,
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&seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
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printf("%s: DMA buffer alloc error %d\n",
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self->dv_xname, error);
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return;
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}
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1999-01-17 23:47:50 +03:00
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sc->sc_rb.rb_dmabase = seg.ds_addr;
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1999-01-16 15:43:09 +03:00
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if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size,
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1999-01-17 23:47:50 +03:00
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&sc->sc_rb.rb_membase,
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1999-01-16 15:43:09 +03:00
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BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
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printf("%s: DMA buffer map error %d\n",
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self->dv_xname, error);
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bus_dmamem_free(sa->sa_dmatag, &seg, rseg);
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return;
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}
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/*
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* Initialize transceiver and determine which PHY connection to use.
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*/
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be_tcvr_init(sc);
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/*
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* Initialize our media structures and MII info.
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*/
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mii->mii_ifp = ifp;
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mii->mii_readreg = be_mii_readreg;
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mii->mii_writereg = be_mii_writereg;
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mii->mii_statchg = be_statchg;
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ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts);
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if ((sc->sc_conf & BE_CONF_MII) != 0) {
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#if 1
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mii_phy_probe(&sc->sc_dev, mii, 0xffffffff);
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|
|
|
#else
|
|
|
|
/* TEST */
|
|
|
|
extern int mii_print __P((void *, const char *));
|
|
|
|
struct mii_attach_args ma;
|
|
|
|
struct mii_softc *child;
|
|
|
|
|
|
|
|
bzero(&ma, sizeof(ma));
|
|
|
|
ma.mii_phyno = BE_PHY_INTERNAL;
|
|
|
|
ma.mii_data = mii;
|
|
|
|
ma.mii_capmask = 0xffffffff;
|
|
|
|
if ((child = (struct mii_softc *)
|
|
|
|
config_found(&sc->sc_dev, &ma, mii_print)) != NULL) {
|
|
|
|
/*
|
|
|
|
* Link it up in the parent's MII data.
|
|
|
|
*/
|
|
|
|
LIST_INSERT_HEAD(&mii->mii_phys, child, mii_list);
|
|
|
|
mii->mii_instance++;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
|
|
|
|
/* No PHY attached */
|
|
|
|
ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_NONE, 0, NULL);
|
|
|
|
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_NONE);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* XXX - we can really do the following ONLY if the
|
|
|
|
* phy indeed has the auto negotiation capability!!
|
|
|
|
*/
|
|
|
|
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The be internal phy looks vaguely like MII hardware,
|
|
|
|
* but not enough to be able to use the MII device
|
|
|
|
* layer. Hence, we have to take care of media selection
|
|
|
|
* ourselves.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Use `ifm_data' to store BMCR bits */
|
|
|
|
ifmedia_add(&sc->sc_media,
|
|
|
|
IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0),
|
|
|
|
0, NULL);
|
|
|
|
ifmedia_add(&sc->sc_media,
|
|
|
|
IFM_MAKEWORD(IFM_ETHER,IFM_10_T,IFM_FDX,0),
|
|
|
|
BMCR_FDX, NULL);
|
|
|
|
ifmedia_add(&sc->sc_media,
|
|
|
|
IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,0),
|
|
|
|
BMCR_S100, NULL);
|
|
|
|
ifmedia_add(&sc->sc_media,
|
|
|
|
IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,IFM_FDX,0),
|
|
|
|
BMCR_S100|BMCR_FDX, NULL);
|
|
|
|
ifmedia_add(&sc->sc_media,
|
|
|
|
IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0),
|
|
|
|
0, NULL);
|
|
|
|
ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
|
|
|
|
}
|
|
|
|
|
|
|
|
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
|
|
|
|
ifp->if_softc = sc;
|
|
|
|
ifp->if_start = bestart;
|
|
|
|
ifp->if_ioctl = beioctl;
|
|
|
|
ifp->if_watchdog = bewatchdog;
|
|
|
|
ifp->if_flags =
|
|
|
|
IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
|
|
|
|
|
|
|
|
/* Attach the interface. */
|
|
|
|
if_attach(ifp);
|
|
|
|
ether_ifattach(ifp, sc->sc_enaddr);
|
|
|
|
|
|
|
|
#if NBPFILTER > 0
|
|
|
|
bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB,
|
|
|
|
sizeof(struct ether_header));
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Routine to copy from mbuf chain to transmit buffer in
|
|
|
|
* network buffer memory.
|
|
|
|
*/
|
|
|
|
static __inline__ int
|
|
|
|
be_put(sc, idx, m)
|
|
|
|
struct be_softc *sc;
|
|
|
|
int idx;
|
|
|
|
struct mbuf *m;
|
|
|
|
{
|
|
|
|
struct mbuf *n;
|
|
|
|
int len, tlen = 0, boff = 0;
|
1999-01-17 23:47:50 +03:00
|
|
|
caddr_t bp;
|
|
|
|
|
|
|
|
bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
for (; m; m = n) {
|
|
|
|
len = m->m_len;
|
|
|
|
if (len == 0) {
|
|
|
|
MFREE(m, n);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
bcopy(mtod(m, caddr_t), bp+boff, len);
|
|
|
|
boff += len;
|
|
|
|
tlen += len;
|
|
|
|
MFREE(m, n);
|
|
|
|
}
|
|
|
|
return (tlen);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pull data off an interface.
|
|
|
|
* Len is the length of data, with local net header stripped.
|
|
|
|
* We copy the data into mbufs. When full cluster sized units are present,
|
|
|
|
* we copy into clusters.
|
|
|
|
*/
|
|
|
|
static __inline__ struct mbuf *
|
|
|
|
be_get(sc, idx, totlen)
|
|
|
|
struct be_softc *sc;
|
|
|
|
int idx, totlen;
|
|
|
|
{
|
|
|
|
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
struct mbuf *m;
|
|
|
|
struct mbuf *top, **mp;
|
|
|
|
int len, pad, boff = 0;
|
1999-01-17 23:47:50 +03:00
|
|
|
caddr_t bp;
|
|
|
|
|
|
|
|
bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
|
|
if (m == NULL)
|
|
|
|
return (NULL);
|
|
|
|
m->m_pkthdr.rcvif = ifp;
|
|
|
|
m->m_pkthdr.len = totlen;
|
|
|
|
|
|
|
|
pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
|
|
|
|
m->m_data += pad;
|
|
|
|
len = MHLEN - pad;
|
|
|
|
top = NULL;
|
|
|
|
mp = ⊤
|
|
|
|
|
|
|
|
while (totlen > 0) {
|
|
|
|
if (top) {
|
|
|
|
MGET(m, M_DONTWAIT, MT_DATA);
|
|
|
|
if (m == NULL) {
|
|
|
|
m_freem(top);
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
len = MLEN;
|
|
|
|
}
|
|
|
|
if (top && totlen >= MINCLSIZE) {
|
|
|
|
MCLGET(m, M_DONTWAIT);
|
|
|
|
if (m->m_flags & M_EXT)
|
|
|
|
len = MCLBYTES;
|
|
|
|
}
|
|
|
|
m->m_len = len = min(totlen, len);
|
|
|
|
bcopy(bp + boff, mtod(m, caddr_t), len);
|
|
|
|
boff += len;
|
|
|
|
totlen -= len;
|
|
|
|
*mp = m;
|
|
|
|
mp = &m->m_next;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (top);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pass a packet to the higher levels.
|
|
|
|
*/
|
|
|
|
static __inline__ void
|
|
|
|
be_read(sc, idx, len)
|
|
|
|
struct be_softc *sc;
|
|
|
|
int idx, len;
|
|
|
|
{
|
|
|
|
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
struct ether_header *eh;
|
|
|
|
struct mbuf *m;
|
|
|
|
|
|
|
|
if (len <= sizeof(struct ether_header) ||
|
|
|
|
len > ETHERMTU + sizeof(struct ether_header)) {
|
|
|
|
|
|
|
|
printf("%s: invalid packet size %d; dropping\n",
|
|
|
|
ifp->if_xname, len);
|
|
|
|
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pull packet off interface.
|
|
|
|
*/
|
|
|
|
m = be_get(sc, idx, len);
|
|
|
|
if (m == NULL) {
|
|
|
|
ifp->if_ierrors++;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
ifp->if_ipackets++;
|
|
|
|
|
|
|
|
/* We assume that the header fits entirely in one mbuf. */
|
|
|
|
eh = mtod(m, struct ether_header *);
|
|
|
|
|
|
|
|
#if NBPFILTER > 0
|
|
|
|
/*
|
|
|
|
* Check if there's a BPF listener on this interface.
|
|
|
|
* If so, hand off the raw packet to BPF.
|
|
|
|
*/
|
|
|
|
if (ifp->if_bpf)
|
|
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
|
|
#endif
|
|
|
|
/* Pass the packet up, with the ether header sort-of removed. */
|
|
|
|
m_adj(m, sizeof(struct ether_header));
|
|
|
|
ether_input(ifp, eh, m);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start output on interface.
|
|
|
|
* We make two assumptions here:
|
|
|
|
* 1) that the current priority is set to splnet _before_ this code
|
|
|
|
* is called *and* is returned to the appropriate priority after
|
|
|
|
* return
|
|
|
|
* 2) that the IFF_OACTIVE flag is checked before this code is called
|
|
|
|
* (i.e. that the output part of the interface is idle)
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
bestart(ifp)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
|
|
|
struct be_softc *sc = (struct be_softc *)ifp->if_softc;
|
1999-01-17 23:47:50 +03:00
|
|
|
struct qec_xd *txd = sc->sc_rb.rb_txd;
|
1999-01-16 15:43:09 +03:00
|
|
|
struct mbuf *m;
|
|
|
|
unsigned int bix, len;
|
1999-01-17 23:47:50 +03:00
|
|
|
unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
|
|
|
|
return;
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
bix = sc->sc_rb.rb_tdhead;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
IF_DEQUEUE(&ifp->if_snd, m);
|
|
|
|
if (m == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
#if NBPFILTER > 0
|
|
|
|
/*
|
|
|
|
* If BPF is listening on this interface, let it see the
|
|
|
|
* packet before we commit it to the wire.
|
|
|
|
*/
|
|
|
|
if (ifp->if_bpf)
|
|
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Copy the mbuf chain into the transmit buffer.
|
|
|
|
*/
|
|
|
|
len = be_put(sc, bix, m);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize transmit registers and start transmission
|
|
|
|
*/
|
|
|
|
txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
|
|
|
|
(len & QEC_XD_LENGTH);
|
|
|
|
bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL,
|
|
|
|
BE_CR_CTRL_TWAKEUP);
|
|
|
|
|
|
|
|
if (++bix == QEC_XD_RING_MAXSIZE)
|
|
|
|
bix = 0;
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
|
1999-01-16 15:43:09 +03:00
|
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
sc->sc_rb.rb_tdhead = bix;
|
1999-01-16 15:43:09 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
bestop(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
|
|
|
int n;
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t br = sc->sc_br;
|
|
|
|
|
|
|
|
untimeout(be_tick, sc);
|
|
|
|
|
|
|
|
/* Stop the transmitter */
|
|
|
|
bus_space_write_4(t, br, BE_BRI_TXCFG, 0);
|
|
|
|
for (n = 32; n > 0; n--) {
|
|
|
|
if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0)
|
|
|
|
break;
|
|
|
|
DELAY(20);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Stop the receiver */
|
|
|
|
bus_space_write_4(t, br, BE_BRI_RXCFG, 0);
|
|
|
|
for (n = 32; n > 0; n--) {
|
|
|
|
if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0)
|
|
|
|
break;
|
|
|
|
DELAY(20);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset interface.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
bereset(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
|
|
|
int s;
|
|
|
|
|
|
|
|
s = splnet();
|
|
|
|
bestop(sc);
|
|
|
|
beinit(sc);
|
|
|
|
splx(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
bewatchdog(ifp)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
|
|
|
struct be_softc *sc = ifp->if_softc;
|
|
|
|
|
|
|
|
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
|
|
|
|
++sc->sc_ethercom.ec_if.if_oerrors;
|
|
|
|
|
|
|
|
bereset(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
beintr(v)
|
|
|
|
void *v;
|
|
|
|
{
|
|
|
|
struct be_softc *sc = (struct be_softc *)v;
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
u_int32_t whyq, whyb, whyc;
|
|
|
|
int r = 0;
|
|
|
|
|
|
|
|
/* Read QEC status, channel status and BE status */
|
|
|
|
whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
|
|
|
|
whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT);
|
|
|
|
whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT);
|
|
|
|
|
|
|
|
if (whyq & QEC_STAT_BM)
|
|
|
|
r |= beeint(sc, whyb);
|
|
|
|
|
|
|
|
if (whyq & QEC_STAT_ER)
|
|
|
|
r |= beqint(sc, whyc);
|
|
|
|
|
|
|
|
if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ)
|
|
|
|
r |= betint(sc);
|
|
|
|
|
|
|
|
if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ)
|
|
|
|
r |= berint(sc);
|
|
|
|
|
|
|
|
return (r);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* QEC Interrupt.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
beqint(sc, why)
|
|
|
|
struct be_softc *sc;
|
|
|
|
u_int32_t why;
|
|
|
|
{
|
|
|
|
int r = 0, rst = 0;
|
|
|
|
|
|
|
|
if (why & BE_CR_STAT_TXIRQ)
|
|
|
|
r |= 1;
|
|
|
|
if (why & BE_CR_STAT_RXIRQ)
|
|
|
|
r |= 1;
|
|
|
|
|
|
|
|
if (why & BE_CR_STAT_BERROR) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: bigmac error\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (why & BE_CR_STAT_TXDERR) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: tx dma error ( ", sc->sc_dev.dv_xname);
|
|
|
|
if (why & BE_CR_STAT_TXLERR)
|
|
|
|
printf("Late ");
|
|
|
|
if (why & BE_CR_STAT_TXPERR)
|
|
|
|
printf("Parity ");
|
|
|
|
if (why & BE_CR_STAT_TXSERR)
|
|
|
|
printf("Generic ");
|
|
|
|
printf(")\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (why & BE_CR_STAT_RXDROP) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (why & BE_CR_STAT_RXSMALL) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: rx dma error ( ", sc->sc_dev.dv_xname);
|
|
|
|
if (why & BE_CR_STAT_RXLERR)
|
|
|
|
printf("Late ");
|
|
|
|
if (why & BE_CR_STAT_RXPERR)
|
|
|
|
printf("Parity ");
|
|
|
|
if (why & BE_CR_STAT_RXSERR)
|
|
|
|
printf("Generic ");
|
|
|
|
printf(")\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!r) {
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: unexpected error interrupt %08x\n",
|
|
|
|
sc->sc_dev.dv_xname, why);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rst) {
|
|
|
|
printf("%s: resetting\n", sc->sc_dev.dv_xname);
|
|
|
|
bereset(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (r);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Error interrupt.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
beeint(sc, why)
|
|
|
|
struct be_softc *sc;
|
|
|
|
u_int32_t why;
|
|
|
|
{
|
|
|
|
int r = 0, rst = 0;
|
|
|
|
|
|
|
|
if (why & BE_BR_STAT_RFIFOVF) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
if (why & BE_BR_STAT_TFIFO_UND) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
if (why & BE_BR_STAT_MAXPKTERR) {
|
|
|
|
r |= 1;
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: max packet size error\n", sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!r) {
|
|
|
|
rst = 1;
|
|
|
|
printf("%s: unexpected error interrupt %08x\n",
|
|
|
|
sc->sc_dev.dv_xname, why);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rst) {
|
|
|
|
printf("%s: resetting\n", sc->sc_dev.dv_xname);
|
|
|
|
bereset(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (r);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Transmit interrupt.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
betint(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
|
|
|
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t br = sc->sc_br;
|
|
|
|
unsigned int bix, txflags;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Unload collision counters
|
|
|
|
*/
|
|
|
|
ifp->if_collisions +=
|
|
|
|
bus_space_read_4(t, br, BE_BRI_NCCNT) +
|
|
|
|
bus_space_read_4(t, br, BE_BRI_FCCNT) +
|
|
|
|
bus_space_read_4(t, br, BE_BRI_EXCNT) +
|
|
|
|
bus_space_read_4(t, br, BE_BRI_LTCNT);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* the clear the hardware counters
|
|
|
|
*/
|
|
|
|
bus_space_write_4(t, br, BE_BRI_NCCNT, 0);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_FCCNT, 0);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_EXCNT, 0);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_LTCNT, 0);
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
bix = sc->sc_rb.rb_tdtail;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
for (;;) {
|
1999-01-17 23:47:50 +03:00
|
|
|
if (sc->sc_rb.rb_td_nbusy <= 0)
|
1999-01-16 15:43:09 +03:00
|
|
|
break;
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
txflags = sc->sc_rb.rb_txd[bix].xd_flags;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
if (txflags & QEC_XD_OWN)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
ifp->if_opackets++;
|
|
|
|
|
|
|
|
if (++bix == QEC_XD_RING_MAXSIZE)
|
|
|
|
bix = 0;
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
--sc->sc_rb.rb_td_nbusy;
|
1999-01-16 15:43:09 +03:00
|
|
|
}
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
sc->sc_rb.rb_tdtail = bix;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
bestart(ifp);
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
if (sc->sc_rb.rb_td_nbusy == 0)
|
1999-01-16 15:43:09 +03:00
|
|
|
ifp->if_timer = 0;
|
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Receive interrupt.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
berint(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
1999-01-17 23:47:50 +03:00
|
|
|
struct qec_xd *xd = sc->sc_rb.rb_rxd;
|
1999-01-16 15:43:09 +03:00
|
|
|
unsigned int bix, len;
|
1999-01-17 23:47:50 +03:00
|
|
|
unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
bix = sc->sc_rb.rb_rdtail;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Process all buffers with valid data.
|
|
|
|
*/
|
|
|
|
for (;;) {
|
|
|
|
len = xd[bix].xd_flags;
|
|
|
|
if (len & QEC_XD_OWN)
|
|
|
|
break;
|
|
|
|
|
|
|
|
len &= QEC_XD_LENGTH;
|
|
|
|
be_read(sc, bix, len);
|
|
|
|
|
|
|
|
/* ... */
|
|
|
|
xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
|
|
|
|
QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH);
|
|
|
|
|
|
|
|
if (++bix == QEC_XD_RING_MAXSIZE)
|
|
|
|
bix = 0;
|
|
|
|
}
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
sc->sc_rb.rb_rdtail = bix;
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
beioctl(ifp, cmd, data)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
u_long cmd;
|
|
|
|
caddr_t data;
|
|
|
|
{
|
|
|
|
struct be_softc *sc = ifp->if_softc;
|
|
|
|
struct ifaddr *ifa = (struct ifaddr *)data;
|
|
|
|
struct ifreq *ifr = (struct ifreq *)data;
|
|
|
|
int s, error = 0;
|
|
|
|
|
|
|
|
s = splnet();
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SIOCSIFADDR:
|
|
|
|
ifp->if_flags |= IFF_UP;
|
|
|
|
switch (ifa->ifa_addr->sa_family) {
|
|
|
|
#ifdef INET
|
|
|
|
case AF_INET:
|
|
|
|
beinit(sc);
|
|
|
|
arp_ifinit(ifp, ifa);
|
|
|
|
break;
|
|
|
|
#endif /* INET */
|
|
|
|
#ifdef NS
|
|
|
|
case AF_NS:
|
|
|
|
{
|
|
|
|
struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
|
|
|
|
|
|
|
|
if (ns_nullhost(*ina))
|
1999-01-18 16:29:01 +03:00
|
|
|
ina->x_host =
|
|
|
|
*(union ns_host *)LLADDR(ifp->if_sadl);
|
1999-01-16 15:43:09 +03:00
|
|
|
else
|
1999-01-18 16:29:01 +03:00
|
|
|
bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
|
|
|
|
sizeof(sc->sc_enaddr));
|
1999-01-16 15:43:09 +03:00
|
|
|
/* Set new address. */
|
|
|
|
beinit(sc);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif /* NS */
|
|
|
|
default:
|
|
|
|
beinit(sc);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SIOCSIFFLAGS:
|
|
|
|
sc->sc_promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI);
|
|
|
|
if ((ifp->if_flags & IFF_UP) == 0 &&
|
|
|
|
(ifp->if_flags & IFF_RUNNING) != 0) {
|
|
|
|
/*
|
|
|
|
* If interface is marked down and it is running, then
|
|
|
|
* stop it.
|
|
|
|
*/
|
|
|
|
bestop(sc);
|
|
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
|
|
} else if ((ifp->if_flags & IFF_UP) != 0 &&
|
|
|
|
(ifp->if_flags & IFF_RUNNING) == 0) {
|
|
|
|
/*
|
|
|
|
* If interface is marked up and it is stopped, then
|
|
|
|
* start it.
|
|
|
|
*/
|
|
|
|
beinit(sc);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Reset the interface to pick up changes in any other
|
|
|
|
* flags that affect hardware registers.
|
|
|
|
*/
|
|
|
|
bestop(sc);
|
|
|
|
beinit(sc);
|
|
|
|
}
|
|
|
|
#ifdef BEDEBUG
|
|
|
|
if (ifp->if_flags & IFF_DEBUG)
|
1999-01-17 23:47:50 +03:00
|
|
|
sc->sc_debug = 1;
|
1999-01-16 15:43:09 +03:00
|
|
|
else
|
|
|
|
sc->sc_debug = 0;
|
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SIOCADDMULTI:
|
|
|
|
case SIOCDELMULTI:
|
|
|
|
error = (cmd == SIOCADDMULTI) ?
|
|
|
|
ether_addmulti(ifr, &sc->sc_ethercom):
|
|
|
|
ether_delmulti(ifr, &sc->sc_ethercom);
|
|
|
|
|
|
|
|
if (error == ENETRESET) {
|
|
|
|
/*
|
|
|
|
* Multicast list has changed; set the hardware filter
|
|
|
|
* accordingly.
|
|
|
|
*/
|
|
|
|
be_mcreset(sc);
|
|
|
|
error = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SIOCGIFMEDIA:
|
|
|
|
case SIOCSIFMEDIA:
|
|
|
|
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
error = EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
splx(s);
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
beinit(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
1999-01-17 23:47:50 +03:00
|
|
|
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
1999-01-16 15:43:09 +03:00
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t br = sc->sc_br;
|
|
|
|
bus_space_handle_t cr = sc->sc_cr;
|
|
|
|
struct qec_softc *qec = sc->sc_qec;
|
|
|
|
u_int32_t qecaddr;
|
|
|
|
u_int8_t *ea;
|
|
|
|
int s;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
|
1999-01-16 15:43:09 +03:00
|
|
|
be_tcvr_init(sc);
|
|
|
|
|
|
|
|
be_ifmedia_upd(ifp);
|
|
|
|
|
|
|
|
bestop(sc);
|
|
|
|
|
|
|
|
ea = sc->sc_enaddr;
|
|
|
|
bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
|
|
|
|
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
|
|
|
|
|
|
|
|
DELAY(20);
|
|
|
|
|
|
|
|
bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
|
|
|
|
|
|
|
|
bus_space_write_4(t, br, BE_BRI_XIFCFG,
|
|
|
|
BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
|
|
|
|
|
|
|
|
bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Turn off counter expiration interrupts as well as
|
|
|
|
* 'gotframe' and 'sentframe'
|
|
|
|
*/
|
|
|
|
bus_space_write_4(t, br, BE_BRI_IMASK,
|
|
|
|
BE_BR_IMASK_GOTFRAME |
|
|
|
|
BE_BR_IMASK_RCNTEXP |
|
|
|
|
BE_BR_IMASK_ACNTEXP |
|
|
|
|
BE_BR_IMASK_CCNTEXP |
|
|
|
|
BE_BR_IMASK_LCNTEXP |
|
|
|
|
BE_BR_IMASK_CVCNTEXP |
|
|
|
|
BE_BR_IMASK_SENTFRAME |
|
|
|
|
BE_BR_IMASK_NCNTEXP |
|
|
|
|
BE_BR_IMASK_ECNTEXP |
|
|
|
|
BE_BR_IMASK_LCCNTEXP |
|
|
|
|
BE_BR_IMASK_FCNTEXP |
|
|
|
|
BE_BR_IMASK_DTIMEXP);
|
|
|
|
|
|
|
|
/* Channel registers: */
|
1999-01-17 23:47:50 +03:00
|
|
|
bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
|
1999-01-16 15:43:09 +03:00
|
|
|
|
|
|
|
qecaddr = sc->sc_channel * qec->sc_msize;
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
|
|
|
|
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
|
|
|
|
bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
|
|
|
|
|
|
|
|
/* Enable transmitter */
|
|
|
|
bus_space_write_4(t, br, BE_BRI_TXCFG,
|
|
|
|
BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
|
|
|
|
|
|
|
|
/* Enable receiver */
|
|
|
|
bus_space_write_4(t, br, BE_BRI_RXCFG,
|
|
|
|
BE_BR_RXCFG_HENABLE | BE_BR_RXCFG_FIFO |
|
|
|
|
BE_BR_RXCFG_ENABLE);
|
|
|
|
|
|
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
|
|
|
|
timeout(be_tick, sc, hz);
|
|
|
|
splx(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
be_mcreset(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
1999-01-17 23:47:50 +03:00
|
|
|
struct ethercom *ec = &sc->sc_ethercom;
|
1999-01-16 15:43:09 +03:00
|
|
|
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t br = sc->sc_br;
|
|
|
|
u_int32_t crc;
|
|
|
|
u_int16_t hash[4];
|
|
|
|
u_int8_t octet;
|
|
|
|
int i, j;
|
|
|
|
struct ether_multi *enm;
|
|
|
|
struct ether_multistep step;
|
|
|
|
|
|
|
|
if (ifp->if_flags & IFF_ALLMULTI) {
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0xffff);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0xffff);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0xffff);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0xffff);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ifp->if_flags & IFF_PROMISC) {
|
|
|
|
u_int32_t v;
|
|
|
|
|
|
|
|
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
|
|
|
|
v |= BE_BR_RXCFG_PMISC;
|
|
|
|
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
hash[3] = hash[2] = hash[1] = hash[0] = 0;
|
|
|
|
|
1999-01-17 23:47:50 +03:00
|
|
|
ETHER_FIRST_MULTI(step, ec, enm);
|
1999-01-16 15:43:09 +03:00
|
|
|
while (enm != NULL) {
|
|
|
|
if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
|
|
|
|
/*
|
|
|
|
* We must listen to a range of multicast
|
|
|
|
* addresses. For now, just accept all
|
|
|
|
* multicasts, rather than trying to set only
|
|
|
|
* those filter bits needed to match the range.
|
|
|
|
* (At this time, the only use of address
|
|
|
|
* ranges is for IP multicast routing, for
|
|
|
|
* which the range is big enough to require
|
|
|
|
* all bits set.)
|
|
|
|
*/
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0xffff);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0xffff);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0xffff);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0xffff);
|
|
|
|
ifp->if_flags |= IFF_ALLMULTI;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
crc = 0xffffffff;
|
|
|
|
|
|
|
|
for (i = 0; i < ETHER_ADDR_LEN; i++) {
|
|
|
|
octet = enm->enm_addrlo[i];
|
|
|
|
|
|
|
|
for (j = 0; j < 8; j++) {
|
|
|
|
if ((crc & 1) ^ (octet & 1)) {
|
|
|
|
crc >>= 1;
|
|
|
|
crc ^= MC_POLY_LE;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
crc >>= 1;
|
|
|
|
octet >>= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
crc >>= 26;
|
|
|
|
hash[crc >> 4] |= 1 << (crc & 0xf);
|
|
|
|
ETHER_NEXT_MULTI(step, enm);
|
|
|
|
}
|
|
|
|
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]);
|
|
|
|
bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]);
|
|
|
|
ifp->if_flags &= ~IFF_ALLMULTI;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the tcvr to an idle state
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
be_mii_sync(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t tr = sc->sc_tr;
|
|
|
|
int n = 20;
|
|
|
|
|
|
|
|
while (n--) {
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
|
|
|
|
MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
|
|
|
|
MGMT_PAL_OENAB);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
|
|
|
|
MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
|
|
|
|
MGMT_PAL_OENAB | MGMT_PAL_DCLOCK);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the transceiver and figure out whether we're using the
|
|
|
|
* external or internal one.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
be_tcvr_init(sc)
|
|
|
|
struct be_softc *sc;
|
|
|
|
{
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t tr = sc->sc_tr;
|
|
|
|
u_int32_t v;
|
|
|
|
|
|
|
|
be_mii_sync(sc);
|
|
|
|
|
|
|
|
if (sc->sc_rev != 1) {
|
|
|
|
printf("%s: rev %d PAL not supported.\n",
|
|
|
|
sc->sc_dev.dv_xname,
|
|
|
|
sc->sc_rev);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
|
|
|
|
MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
|
|
|
|
MGMT_PAL_DCLOCK);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
|
|
|
|
MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
DELAY(200);
|
|
|
|
|
|
|
|
v = bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
1999-01-17 23:47:50 +03:00
|
|
|
#ifdef BEDEBUG
|
|
|
|
if (sc->sc_debug != 0) {
|
1999-01-16 15:43:09 +03:00
|
|
|
char bits[64];
|
|
|
|
printf("be_tcvr_init: MGMTPAL=%s\n",
|
|
|
|
bitmask_snprintf(v, MGMT_PAL_BITS, bits, sizeof(bits)));
|
|
|
|
}
|
|
|
|
#endif
|
1999-02-19 17:57:00 +03:00
|
|
|
{
|
|
|
|
char bits[64];
|
|
|
|
printf("be_tcvr_init: MGMTPAL=%s\n",
|
|
|
|
bitmask_snprintf(v, MGMT_PAL_BITS, bits, sizeof(bits)));
|
|
|
|
if ((v & MGMT_PAL_EXT_MDIO) != 0) {
|
|
|
|
printf("EXTERNAL\n");
|
|
|
|
}
|
|
|
|
}
|
1999-01-17 23:47:50 +03:00
|
|
|
if ((v & MGMT_PAL_EXT_MDIO) != 0) {
|
1999-01-16 15:43:09 +03:00
|
|
|
sc->sc_conf |= BE_CONF_MII;
|
|
|
|
/*sc->sc_tcvr_type = BE_TCVR_EXTERNAL;*/
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_TCVRPAL,
|
|
|
|
~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE |
|
|
|
|
TCVR_PAL_LTENABLE));
|
|
|
|
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
|
1999-01-17 23:47:50 +03:00
|
|
|
} else if ((v & MGMT_PAL_INT_MDIO) != 0) {
|
1999-01-16 15:43:09 +03:00
|
|
|
/*sc->sc_tcvr_type = BE_TCVR_INTERNAL;*/
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_TCVRPAL,
|
|
|
|
~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE |
|
|
|
|
TCVR_PAL_LTENABLE | TCVR_PAL_SERIAL));
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
|
1999-01-17 23:47:50 +03:00
|
|
|
} else {
|
1999-01-16 15:43:09 +03:00
|
|
|
printf("%s: no internal or external transceiver found.\n",
|
|
|
|
sc->sc_dev.dv_xname);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static __inline__ int
|
|
|
|
be_tcvr_read_bit(sc, phy)
|
|
|
|
struct be_softc *sc;
|
|
|
|
int phy;
|
|
|
|
{
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t tr = sc->sc_tr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (phy == BE_PHY_INTERNAL) {
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
|
|
|
|
MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
DELAY(20);
|
|
|
|
ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
|
|
|
|
MGMT_PAL_INT_MDIO) >> 3;
|
|
|
|
} else {
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
DELAY(20);
|
|
|
|
ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
|
|
|
|
MGMT_PAL_EXT_MDIO) >> 2;
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
|
|
|
|
MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ void
|
|
|
|
be_tcvr_write_bit(sc, phy, bit)
|
|
|
|
struct be_softc *sc;
|
|
|
|
int phy;
|
|
|
|
int bit;
|
|
|
|
{
|
|
|
|
bus_space_tag_t t = sc->sc_bustag;
|
|
|
|
bus_space_handle_t tr = sc->sc_tr;
|
|
|
|
|
|
|
|
if (phy == BE_PHY_INTERNAL) {
|
|
|
|
bit = ((bit & 1) << 3) | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO;
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit | MGMT_PAL_DCLOCK);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
} else {
|
|
|
|
bit = ((bit & 1) << 2) | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO;
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit | MGMT_PAL_DCLOCK);
|
|
|
|
(void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ void
|
|
|
|
be_mii_sendbits(sc, phy, data, nbits)
|
|
|
|
struct be_softc *sc;
|
|
|
|
int phy;
|
|
|
|
u_int32_t data;
|
|
|
|
int nbits;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
|
|
|
|
be_tcvr_write_bit(sc, phy, (data & i) != 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1999-02-19 17:57:00 +03:00
|
|
|
static int
|
|
|
|
be_mii_readreg(self, phy, reg)
|
1999-01-16 15:43:09 +03:00
|
|
|
struct device *self;
|
|
|
|
int phy, reg;
|
|
|
|
{
|
|
|
|
struct be_softc *sc = (struct be_softc *)self;
|
|
|
|
int val = 0, i;
|
|
|
|
|
1999-02-19 17:57:00 +03:00
|
|
|
/* The `be' internal PHY is not treated as an MII device */
|
|
|
|
if (phy == BE_PHY_INTERNAL)
|
|
|
|
return (0);
|
|
|
|
|
1999-01-16 15:43:09 +03:00
|
|
|
/*
|
|
|
|
* Read the PHY register by manually driving the MII control lines.
|
|
|
|
*/
|
|
|
|
be_mii_sync(sc);
|
|
|
|
be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
|
|
|
|
be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);
|
|
|
|
be_mii_sendbits(sc, phy, phy, 5);
|
|
|
|
be_mii_sendbits(sc, phy, reg, 5);
|
|
|
|
|
|
|
|
(void) be_tcvr_read_bit(sc, phy);
|
|
|
|
(void) be_tcvr_read_bit(sc, phy);
|
|
|
|
|
|
|
|
for (i = 15; i >= 0; i--)
|
|
|
|
val |= (be_tcvr_read_bit(sc, phy) << i);
|
|
|
|
|
|
|
|
(void) be_tcvr_read_bit(sc, phy);
|
|
|
|
(void) be_tcvr_read_bit(sc, phy);
|
|
|
|
(void) be_tcvr_read_bit(sc, phy);
|
|
|
|
|
|
|
|
return (val);
|
|
|
|
}
|
|
|
|
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void
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be_mii_writereg(self, phy, reg, val)
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struct device *self;
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int phy, reg, val;
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{
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struct be_softc *sc = (struct be_softc *)self;
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int i;
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/*
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* Write the PHY register by manually driving the MII control lines.
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*/
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be_mii_sync(sc);
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be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
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be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);
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be_mii_sendbits(sc, phy, phy, 5);
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be_mii_sendbits(sc, phy, reg, 5);
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be_tcvr_write_bit(sc, phy, 1);
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be_tcvr_write_bit(sc, phy, 0);
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for (i = 15; i >= 0; i--)
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be_tcvr_write_bit(sc, phy, (val >> i) & 1);
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}
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int
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be_mii_reset(sc, phy)
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struct be_softc *sc;
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int phy;
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{
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int n;
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be_mii_writereg((struct device *)sc, phy, MII_BMCR,
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BMCR_LOOP | BMCR_PDOWN | BMCR_ISO);
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be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);
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for (n = 16; n >= 0; n--) {
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int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
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if ((bmcr & BMCR_RESET) == 0)
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break;
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DELAY(20);
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}
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if (n == 0) {
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printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname);
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return (EIO);
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}
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return (0);
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}
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void
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be_statchg(self)
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struct device *self;
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{
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struct be_softc *sc = (struct be_softc *)self;
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printf("be_statchg: media_active=%x\n", sc->sc_mii.mii_media_active);
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}
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void
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be_tick(arg)
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void *arg;
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{
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struct be_softc *sc = arg;
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int s = splnet();
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if ((sc->sc_conf & BE_CONF_MII) != 0)
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mii_tick(&sc->sc_mii);
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else
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be_internal_phy_auto(sc);
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splx(s);
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timeout(be_tick, sc, hz);
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}
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void
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be_internal_phy_auto(sc)
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struct be_softc *sc;
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{
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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int bmcr, bmsr;
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/*
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* Check link status; if we don't have a link, try another
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* speed. We can't detect duplex mode, so half-duplex is
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* what we have to settle for.
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*/
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/* Only used for automatic media selection */
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if (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media) != IFM_AUTO)
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return;
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/* Don't bother if interface isn't up */
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if ((ifp->if_flags & IFF_UP) == 0)
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return;
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/* Read twice in case the register is latched */
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1999-02-19 17:57:00 +03:00
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bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)|
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be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR);
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1999-01-16 15:43:09 +03:00
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if ((bmsr & BMSR_LINK) != 0) {
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/* We have a carrier */
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return;
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}
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1999-02-19 17:57:00 +03:00
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bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR);
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1999-01-16 15:43:09 +03:00
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/* Just flip the fast speed bit */
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bmcr ^= BMCR_S100;
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be_mii_writereg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
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}
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/*
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* Get current media settings.
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*/
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void
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be_ifmedia_sts(ifp, ifmr)
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struct ifnet *ifp;
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struct ifmediareq *ifmr;
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{
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struct be_softc *sc = ifp->if_softc;
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int bmcr, bmsr;
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if ((sc->sc_conf & BE_CONF_MII) != 0) {
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mii_pollstat(&sc->sc_mii);
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ifmr->ifm_status = sc->sc_mii.mii_media_status;
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ifmr->ifm_active = sc->sc_mii.mii_media_active;
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return;
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}
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/*
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* Internal transceiver; do the work here.
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*/
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1999-02-19 17:57:00 +03:00
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bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR);
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1999-01-16 15:43:09 +03:00
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switch (bmcr & (BMCR_S100 | BMCR_FDX)) {
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case (BMCR_S100 | BMCR_FDX):
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ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
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break;
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case BMCR_S100:
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ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
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break;
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case BMCR_FDX:
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ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
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break;
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case 0:
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ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
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break;
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}
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/* Read twice in case the register is latched */
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1999-02-19 17:57:00 +03:00
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bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)|
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be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR);
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1999-01-16 15:43:09 +03:00
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if (bmsr & BMSR_LINK)
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ifmr->ifm_status |= IFM_AVALID | IFM_ACTIVE;
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else {
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ifmr->ifm_status |= IFM_AVALID;
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ifmr->ifm_status &= ~IFM_ACTIVE;
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}
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}
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/*
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* Set media options.
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*/
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int
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be_ifmedia_upd(ifp)
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struct ifnet *ifp;
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{
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struct be_softc *sc = ifp->if_softc;
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struct ifmedia *ifm = &sc->sc_media;
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int newmedia = ifm->ifm_media;
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int n, error, phy, bmcr;
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char *speed, *mode;
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u_int32_t v;
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t br = sc->sc_br;
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if (IFM_TYPE(newmedia) != IFM_ETHER)
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return (EINVAL);
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if ((sc->sc_conf & BE_CONF_MII) != 0) {
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int error;
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if ((error = mii_mediachg(&sc->sc_mii)) != 0)
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return (error);
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v = bus_space_read_4(t, br, BE_BRI_TXCFG);
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if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
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v |= BE_BR_TXCFG_FULLDPLX;
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else
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v &= ~BE_BR_TXCFG_FULLDPLX;
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bus_space_write_4(t, br, BE_BRI_TXCFG, v);
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return (0);
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}
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/*
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* The rest of this routine is devoted to the
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* not-quite-a-phy internal transceiver case.
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*/
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phy = BE_PHY_INTERNAL;
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/* Why must we reset the device? */
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if ((error = be_mii_reset(sc, phy)) != 0)
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return (error);
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bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
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if (IFM_SUBTYPE(newmedia) == IFM_100_TX) {
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bmcr |= BMCR_S100;
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speed = "100baseTX";
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} else if (IFM_SUBTYPE(newmedia) == IFM_10_T) {
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bmcr &= ~BMCR_S100;
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speed = "10baseT";
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} else {
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speed = "auto sense";
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}
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printf("%s: selecting %s", sc->sc_dev.dv_xname, speed);
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v = bus_space_read_4(t, br, BE_BRI_TXCFG);
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if ((IFM_OPTIONS(newmedia) & IFM_FDX) != 0) {
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bmcr |= BMCR_FDX;
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v |= BE_BR_TXCFG_FULLDPLX;
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mode = "full";
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} else {
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bmcr &= ~BMCR_FDX;
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v &= ~BE_BR_TXCFG_FULLDPLX;
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mode = "half";
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}
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bus_space_write_4(t, br, BE_BRI_TXCFG, v);
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printf(" %s-duplex\n", mode);
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/* Select the new mode and take out of isolation */
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be_mii_writereg((struct device *)sc, phy, MII_BMCR, bmcr & ~BMCR_ISO);
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for (n = 32; n >= 0; n--) {
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bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
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if ((bmcr & BMCR_ISO) == 0)
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break;
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DELAY(20);
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}
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if (n == 0) {
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printf("%s: bmcr unisolate failed\n", sc->sc_dev.dv_xname);
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return (EIO);
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}
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return (0);
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}
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