Share ring buffer code and data structure for `be' and `qe' in
the QEC module. Adapt the QEC interrupt establish code to suit the needs of the `qe' device.
This commit is contained in:
pk
parent
58fa0024a5
commit
fb846bde24
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@ -1,4 +1,4 @@
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/* $NetBSD: be.c,v 1.1 1999/01/16 12:43:09 pk Exp $ */
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/* $NetBSD: be.c,v 1.2 1999/01/17 20:47:50 pk Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -141,24 +141,8 @@ struct be_softc {
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int sc_burst;
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int sc_conf;
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#define BE_CONF_MII 1
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int sc_nticks; /* negotiation ticks */
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/* Ring Descriptors */
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caddr_t sc_membase;
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bus_addr_t sc_dmabase;
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struct qec_xd *sc_txd; /* Transmit descriptors */
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bus_addr_t sc_txddma; /* DMA address of same */
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struct qec_xd *sc_rxd; /* Receive descriptors */
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bus_addr_t sc_rxddma; /* DMA address of same */
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caddr_t sc_txbuf; /* Transmit buffers */
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caddr_t sc_rxbuf; /* Receive buffers */
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int sc_ntbuf; /* # of transmit buffers */
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int sc_nrbuf; /* # of receive buffers */
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/* Ring Descriptor state */
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int sc_tdhead, sc_tdtail;
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int sc_rdtail;
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int sc_td_nbusy;
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struct qec_ring sc_rb; /* Packet Ring Buffer */
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/* MAC address */
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u_int8_t sc_enaddr[6];
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@ -168,7 +152,6 @@ int bematch __P((struct device *, struct cfdata *, void *));
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void beattach __P((struct device *, struct device *, void *));
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void beinit __P((struct be_softc *));
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void bememinit __P((struct be_softc *));
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void bestart __P((struct ifnet *));
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void bestop __P((struct be_softc *));
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void bewatchdog __P((struct ifnet *));
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@ -190,6 +173,7 @@ void be_tcvr_init __P((struct be_softc *));
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/* ifmedia callbacks */
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void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
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int be_ifmedia_upd __P((struct ifnet *));
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void be_mcreset __P((struct be_softc *));
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/* MII methods & callbacks */
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@ -300,13 +284,15 @@ beattach(parent, self, aux)
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/*
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* Allocate descriptor ring and buffers.
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*/
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sc->sc_ntbuf = QEC_XD_RING_MAXSIZE; /* for now, allocate as many bufs */
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sc->sc_nrbuf = QEC_XD_RING_MAXSIZE; /* as there are ring descriptors */
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/* for now, allocate as many bufs as there are ring descriptors */
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sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
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sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
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size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
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QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
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sc->sc_ntbuf * BE_PKT_BUF_SZ +
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sc->sc_nrbuf * BE_PKT_BUF_SZ;
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sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ +
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sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ;
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if ((error = bus_dmamem_alloc(sa->sa_dmatag, size,
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NBPG, 0,
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&seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
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@ -314,10 +300,10 @@ beattach(parent, self, aux)
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self->dv_xname, error);
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return;
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}
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sc->sc_dmabase = seg.ds_addr;
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sc->sc_rb.rb_dmabase = seg.ds_addr;
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if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size,
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&sc->sc_membase,
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&sc->sc_rb.rb_membase,
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BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
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printf("%s: DMA buffer map error %d\n",
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self->dv_xname, error);
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@ -432,7 +418,9 @@ be_put(sc, idx, m)
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{
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struct mbuf *n;
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int len, tlen = 0, boff = 0;
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caddr_t bp = sc->sc_txbuf + (idx % sc->sc_ntbuf) * BE_PKT_BUF_SZ;
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caddr_t bp;
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bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ;
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for (; m; m = n) {
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len = m->m_len;
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@ -463,7 +451,9 @@ be_get(sc, idx, totlen)
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struct mbuf *m;
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struct mbuf *top, **mp;
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int len, pad, boff = 0;
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caddr_t bp = sc->sc_rxbuf + (idx % sc->sc_nrbuf) * BE_PKT_BUF_SZ;
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caddr_t bp;
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bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ;
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MGETHDR(m, M_DONTWAIT, MT_DATA);
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if (m == NULL)
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@ -564,15 +554,15 @@ bestart(ifp)
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struct ifnet *ifp;
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{
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struct be_softc *sc = (struct be_softc *)ifp->if_softc;
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struct qec_xd *txd = sc->sc_txd;
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struct qec_xd *txd = sc->sc_rb.rb_txd;
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struct mbuf *m;
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unsigned int bix, len;
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unsigned int ntbuf = sc->sc_ntbuf;
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unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
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if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
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return;
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bix = sc->sc_tdhead;
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bix = sc->sc_rb.rb_tdhead;
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for (;;) {
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IF_DEQUEUE(&ifp->if_snd, m);
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@ -604,13 +594,13 @@ bestart(ifp)
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if (++bix == QEC_XD_RING_MAXSIZE)
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bix = 0;
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if (++sc->sc_td_nbusy == ntbuf) {
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if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
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ifp->if_flags |= IFF_OACTIVE;
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break;
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}
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}
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sc->sc_tdhead = bix;
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sc->sc_rb.rb_tdhead = bix;
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}
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void
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@ -844,13 +834,13 @@ betint(sc)
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bus_space_write_4(t, br, BE_BRI_EXCNT, 0);
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bus_space_write_4(t, br, BE_BRI_LTCNT, 0);
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bix = sc->sc_tdtail;
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bix = sc->sc_rb.rb_tdtail;
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for (;;) {
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if (sc->sc_td_nbusy <= 0)
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if (sc->sc_rb.rb_td_nbusy <= 0)
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break;
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txflags = sc->sc_txd[bix].xd_flags;
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txflags = sc->sc_rb.rb_txd[bix].xd_flags;
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if (txflags & QEC_XD_OWN)
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break;
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@ -861,14 +851,14 @@ betint(sc)
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if (++bix == QEC_XD_RING_MAXSIZE)
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bix = 0;
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--sc->sc_td_nbusy;
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--sc->sc_rb.rb_td_nbusy;
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}
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sc->sc_tdtail = bix;
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sc->sc_rb.rb_tdtail = bix;
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bestart(ifp);
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if (sc->sc_td_nbusy == 0)
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if (sc->sc_rb.rb_td_nbusy == 0)
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ifp->if_timer = 0;
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return (1);
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@ -881,11 +871,11 @@ int
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berint(sc)
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struct be_softc *sc;
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{
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struct qec_xd *xd = sc->sc_rxd;
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struct qec_xd *xd = sc->sc_rb.rb_rxd;
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unsigned int bix, len;
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unsigned int nrbuf = sc->sc_nrbuf;
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unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
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bix = sc->sc_rdtail;
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bix = sc->sc_rb.rb_rdtail;
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/*
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* Process all buffers with valid data.
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@ -906,7 +896,7 @@ berint(sc)
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bix = 0;
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}
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sc->sc_rdtail = bix;
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sc->sc_rb.rb_rdtail = bix;
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return (1);
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}
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@ -984,7 +974,7 @@ beioctl(ifp, cmd, data)
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}
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#ifdef BEDEBUG
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if (ifp->if_flags & IFF_DEBUG)
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sc->sc_debug = BE_XXX;
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sc->sc_debug = 1;
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else
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sc->sc_debug = 0;
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#endif
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@ -1017,97 +1007,23 @@ beioctl(ifp, cmd, data)
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return (error);
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}
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void
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bememinit(sc)
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struct be_softc *sc;
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{
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bus_addr_t txbufdma, rxbufdma;
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bus_addr_t dma;
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caddr_t p;
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unsigned int ntbuf, nrbuf, i;
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p = sc->sc_membase;
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dma = sc->sc_dmabase;
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ntbuf = sc->sc_ntbuf;
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nrbuf = sc->sc_nrbuf;
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/*
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* Allocate transmit descriptors
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*/
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sc->sc_txd = (struct qec_xd *)p;
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sc->sc_txddma = dma;
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p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
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dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
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/*
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* Allocate receive descriptors
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*/
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sc->sc_rxd = (struct qec_xd *)p;
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sc->sc_rxddma = dma;
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p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
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dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
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/*
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* Allocate transmit buffers
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*/
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sc->sc_txbuf = p;
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txbufdma = dma;
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p += ntbuf * BE_PKT_BUF_SZ;
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dma += ntbuf * BE_PKT_BUF_SZ;
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/*
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* Allocate receive buffers
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*/
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sc->sc_rxbuf = p;
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rxbufdma = dma;
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p += nrbuf * BE_PKT_BUF_SZ;
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dma += nrbuf * BE_PKT_BUF_SZ;
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/*
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* Initialize transmit buffer descriptors
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*/
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for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) {
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sc->sc_txd[i].xd_addr = (u_int32_t)
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(txbufdma + (i % ntbuf) * BE_PKT_BUF_SZ);
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sc->sc_txd[i].xd_flags = 0;
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}
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/*
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* Initialize receive buffer descriptors
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*/
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for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) {
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sc->sc_rxd[i].xd_addr = (u_int32_t)
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(rxbufdma + (i % nrbuf) * BE_PKT_BUF_SZ);
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sc->sc_rxd[i].xd_flags = (i < nrbuf)
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? QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH)
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: 0;
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}
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sc->sc_tdhead = sc->sc_tdtail = 0;
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sc->sc_td_nbusy = 0;
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sc->sc_rdtail = 0;
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}
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void
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beinit(sc)
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struct be_softc *sc;
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{
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t br = sc->sc_br;
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bus_space_handle_t cr = sc->sc_cr;
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struct qec_softc *qec = sc->sc_qec;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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u_int32_t qecaddr;
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u_int8_t *ea;
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int s;
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s = splimp();
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sc->sc_nticks = 0;
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bememinit(sc);
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qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
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be_tcvr_init(sc);
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be_ifmedia_upd(ifp);
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@ -1152,8 +1068,8 @@ beinit(sc)
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BE_BR_IMASK_DTIMEXP);
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/* Channel registers: */
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bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rxddma);
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bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_txddma);
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bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
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bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
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qecaddr = sc->sc_channel * qec->sc_msize;
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bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
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@ -1187,7 +1103,7 @@ void
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be_mcreset(sc)
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struct be_softc *sc;
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{
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struct ethercom *ac = &sc->sc_ethercom;
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struct ethercom *ec = &sc->sc_ethercom;
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t br = sc->sc_br;
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@ -1217,7 +1133,7 @@ be_mcreset(sc)
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hash[3] = hash[2] = hash[1] = hash[0] = 0;
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ETHER_FIRST_MULTI(step, ac, enm);
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ETHER_FIRST_MULTI(step, ec, enm);
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while (enm != NULL) {
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if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
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/*
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@ -1321,14 +1237,14 @@ be_tcvr_init(sc)
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DELAY(200);
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v = bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
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#ifdef DEBUG
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if (bedebug) {
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#ifdef BEDEBUG
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if (sc->sc_debug != 0) {
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char bits[64];
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printf("be_tcvr_init: MGMTPAL=%s\n",
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bitmask_snprintf(v, MGMT_PAL_BITS, bits, sizeof(bits)));
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}
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#endif
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if (v & MGMT_PAL_EXT_MDIO) {
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if ((v & MGMT_PAL_EXT_MDIO) != 0) {
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sc->sc_conf |= BE_CONF_MII;
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/*sc->sc_tcvr_type = BE_TCVR_EXTERNAL;*/
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bus_space_write_4(t, tr, BE_TRI_TCVRPAL,
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@ -1336,15 +1252,13 @@ be_tcvr_init(sc)
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TCVR_PAL_LTENABLE));
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(void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
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}
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else if (v & MGMT_PAL_INT_MDIO) {
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} else if ((v & MGMT_PAL_INT_MDIO) != 0) {
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/*sc->sc_tcvr_type = BE_TCVR_INTERNAL;*/
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bus_space_write_4(t, tr, BE_TRI_TCVRPAL,
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~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE |
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TCVR_PAL_LTENABLE | TCVR_PAL_SERIAL));
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(void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
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}
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else {
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} else {
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printf("%s: no internal or external transceiver found.\n",
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sc->sc_dev.dv_xname);
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: bereg.h,v 1.1 1999/01/16 13:19:11 pk Exp $ */
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/* $NetBSD: bereg.h,v 1.2 1999/01/17 20:47:50 pk Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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@ -158,6 +158,12 @@ struct be_bregs {
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#define BE_BR_STAT_LCCNTEXP 0x00002000 /* late-collision cntr exp */
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#define BE_BR_STAT_FCNTEXP 0x00004000 /* first-collision cntr exp */
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#define BE_BR_STAT_DTIMEXP 0x00008000 /* defer-timer expired */
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#define BE_BR_STAT_BITS "\177\020" \
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"b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \
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"b\3CCNTEXP\0b\5LCNTEXP\0b\6RFIFOVF\0" \
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"b\7CVCNTEXP\0b\10SENTFRAME\0b\11TFIFO_UND\0" \
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"b\12MAXPKTERR\0b\13NCNTEXP\0b\14ECNTEXP\0" \
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"b\15LCCNTEXP\0b\16FCNTEXP\0b\17DTIMEXP\0\0"
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/* be_bregs.imask: interrupt mask. */
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#define BE_BR_IMASK_GOTFRAME 0x00000001 /* received a frame */
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@ -1,4 +1,4 @@
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/* $NetBSD: qec.c,v 1.7 1999/01/16 12:46:08 pk Exp $ */
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/* $NetBSD: qec.c,v 1.8 1999/01/17 20:47:50 pk Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -64,6 +64,12 @@ static int qec_bus_map __P((
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int, /*flags*/
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vaddr_t, /*preferred virtual address */
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bus_space_handle_t *));
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static void *qec_intr_establish __P((
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bus_space_tag_t,
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int, /*level*/
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int, /*flags*/
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int (*) __P((void *)), /*handler*/
|
||||
void *)); /*arg*/
|
||||
|
||||
struct cfattach qec_ca = {
|
||||
sizeof(struct qec_softc), qecmatch, qecattach
|
||||
|
|
@ -202,6 +208,18 @@ qecattach(parent, self, aux)
|
|||
sbt->cookie = sc;
|
||||
sbt->parent = sc->sc_bustag;
|
||||
sbt->sparc_bus_map = qec_bus_map;
|
||||
sbt->sparc_intr_establish = qec_intr_establish;
|
||||
|
||||
/*
|
||||
* Save interrupt information for use in our qec_intr_establish()
|
||||
* function below. Apparently, the intr level for the quad
|
||||
* ethernet board (qe) is stored in the QEC node rather then
|
||||
* separately in each of the QE nodes.
|
||||
*
|
||||
* XXX - qe.c should call bus_intr_establish() with `level = 0'..
|
||||
* XXX - maybe we should have our own attach args for all that.
|
||||
*/
|
||||
sc->sc_intr = sa->sa_intr;
|
||||
|
||||
printf(": %dK memory\n", sc->sc_bufsiz / 1024);
|
||||
|
||||
|
|
@ -248,6 +266,32 @@ qec_bus_map(t, btype, offset, size, flags, vaddr, hp)
|
|||
return (EINVAL);
|
||||
}
|
||||
|
||||
void *
|
||||
qec_intr_establish(t, level, flags, handler, arg)
|
||||
bus_space_tag_t t;
|
||||
int level;
|
||||
int flags;
|
||||
int (*handler) __P((void *));
|
||||
void *arg;
|
||||
{
|
||||
struct qec_softc *sc = t->cookie;
|
||||
|
||||
if (level == 0) {
|
||||
/*
|
||||
* qe.c calls bus_intr_establish() with `level = 0'
|
||||
* XXX - see also comment in qec_attach().
|
||||
*/
|
||||
if (sc->sc_intr == NULL) {
|
||||
printf("%s: warning: no interrupts\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return (NULL);
|
||||
}
|
||||
level = sc->sc_intr->sbi_pri;
|
||||
}
|
||||
|
||||
return (bus_intr_establish(t->parent, level, flags, handler, arg));
|
||||
}
|
||||
|
||||
void
|
||||
qec_init(sc)
|
||||
struct qec_softc *sc;
|
||||
|
|
@ -280,3 +324,81 @@ qec_init(sc)
|
|||
v = (v & QEC_CTRL_MODEMASK) | burst;
|
||||
bus_space_write_4(t, qr, QEC_QRI_CTRL, v);
|
||||
}
|
||||
|
||||
/*
|
||||
* Common routine to initialize the QEC packet ring buffer.
|
||||
* Called from be & qe drivers.
|
||||
*/
|
||||
void
|
||||
qec_meminit(qr, pktbufsz)
|
||||
struct qec_ring *qr;
|
||||
unsigned int pktbufsz;
|
||||
{
|
||||
bus_addr_t txbufdma, rxbufdma;
|
||||
bus_addr_t dma;
|
||||
caddr_t p;
|
||||
unsigned int ntbuf, nrbuf, i;
|
||||
|
||||
p = qr->rb_membase;
|
||||
dma = qr->rb_dmabase;
|
||||
|
||||
ntbuf = qr->rb_ntbuf;
|
||||
nrbuf = qr->rb_nrbuf;
|
||||
|
||||
/*
|
||||
* Allocate transmit descriptors
|
||||
*/
|
||||
qr->rb_txd = (struct qec_xd *)p;
|
||||
qr->rb_txddma = dma;
|
||||
p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
|
||||
dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
|
||||
|
||||
/*
|
||||
* Allocate receive descriptors
|
||||
*/
|
||||
qr->rb_rxd = (struct qec_xd *)p;
|
||||
qr->rb_rxddma = dma;
|
||||
p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
|
||||
dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
|
||||
|
||||
|
||||
/*
|
||||
* Allocate transmit buffers
|
||||
*/
|
||||
qr->rb_txbuf = p;
|
||||
txbufdma = dma;
|
||||
p += ntbuf * pktbufsz;
|
||||
dma += ntbuf * pktbufsz;
|
||||
|
||||
/*
|
||||
* Allocate receive buffers
|
||||
*/
|
||||
qr->rb_rxbuf = p;
|
||||
rxbufdma = dma;
|
||||
p += nrbuf * pktbufsz;
|
||||
dma += nrbuf * pktbufsz;
|
||||
|
||||
/*
|
||||
* Initialize transmit buffer descriptors
|
||||
*/
|
||||
for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) {
|
||||
qr->rb_txd[i].xd_addr = (u_int32_t)
|
||||
(txbufdma + (i % ntbuf) * pktbufsz);
|
||||
qr->rb_txd[i].xd_flags = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize receive buffer descriptors
|
||||
*/
|
||||
for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) {
|
||||
qr->rb_rxd[i].xd_addr = (u_int32_t)
|
||||
(rxbufdma + (i % nrbuf) * pktbufsz);
|
||||
qr->rb_rxd[i].xd_flags = (i < nrbuf)
|
||||
? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH)
|
||||
: 0;
|
||||
}
|
||||
|
||||
qr->rb_tdhead = qr->rb_tdtail = 0;
|
||||
qr->rb_td_nbusy = 0;
|
||||
qr->rb_rdtail = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: qecvar.h,v 1.3 1999/01/16 12:46:08 pk Exp $ */
|
||||
/* $NetBSD: qecvar.h,v 1.4 1999/01/17 20:47:50 pk Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
|
|
@ -43,6 +43,7 @@ struct qec_softc {
|
|||
bus_dma_tag_t sc_dmatag;
|
||||
struct sbus_range *sc_range; /* PROM ranges */
|
||||
int sc_nrange; /* */
|
||||
struct sbus_intr *sc_intr; /* interrupt info */
|
||||
|
||||
bus_space_handle_t sc_regs; /* QEC registers */
|
||||
int sc_nchannels; /* # of channels on board */
|
||||
|
|
@ -53,3 +54,24 @@ struct qec_softc {
|
|||
u_int sc_msize; /* QEC buffer offset per channel */
|
||||
u_int sc_rsize; /* QEC buffer size for receive */
|
||||
};
|
||||
|
||||
struct qec_ring {
|
||||
/* Ring Descriptors */
|
||||
caddr_t rb_membase; /* Packet buffer: CPU address */
|
||||
bus_addr_t rb_dmabase; /* Packet buffer: DMA address */
|
||||
struct qec_xd *rb_txd; /* Transmit descriptors */
|
||||
bus_addr_t rb_txddma; /* DMA address of same */
|
||||
struct qec_xd *rb_rxd; /* Receive descriptors */
|
||||
bus_addr_t rb_rxddma; /* DMA address of same */
|
||||
caddr_t rb_txbuf; /* Transmit buffers */
|
||||
caddr_t rb_rxbuf; /* Receive buffers */
|
||||
int rb_ntbuf; /* # of transmit buffers */
|
||||
int rb_nrbuf; /* # of receive buffers */
|
||||
|
||||
/* Ring Descriptor state */
|
||||
int rb_tdhead, rb_tdtail;
|
||||
int rb_rdtail;
|
||||
int rb_td_nbusy;
|
||||
};
|
||||
|
||||
void qec_meminit __P((struct qec_ring *, unsigned int));
|
||||
|
|
|
|||
Loading…
Reference in New Issue