2015-03-28 11:19:20 +03:00
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/* $NetBSD: xhcireg.h,v 1.3 2015/03/28 08:19:20 skrll Exp $ */
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2013-09-14 04:40:31 +04:00
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _XHCIREG_H_
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#define _XHCIREG_H_
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/* XHCI PCI config registers */
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#define PCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_INTERFACE_XHCI 0x30
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#define PCI_USBREV 0x60 /* RO USB protocol revision */
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#define PCI_USBREV_MASK 0xFF
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#define PCI_USBREV_3_0 0x30 /* USB 3.0 */
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#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */
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2015-03-28 11:19:20 +03:00
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#define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */
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#define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */
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#define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */
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#define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */
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2013-09-14 04:40:31 +04:00
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/* XHCI capability registers */
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#define XHCI_CAPLENGTH 0x00 /* RO capability */
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#define XHCI_CAP_CAPLENGTH(x) ((x) & 0xFF)
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#define XHCI_CAP_HCIVERSION(x) (((x) >> 16) & 0xFFFF) /* RO Interface version number */
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#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */
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#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */
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#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */
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#define XHCI_HCS1_MAXSLOTS(x) ((x) & 0xFF)
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#define XHCI_HCS1_MAXINTRS(x) (((x) >> 8) & 0x3FF)
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#define XHCI_HCS1_MAXPORTS(x) (((x) >> 24) & 0xFF)
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#define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */
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#define XHCI_HCS2_IST(x) ((x) & 0xF)
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#define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF)
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#define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1)
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#define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)
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#define XHCI_HCSPARAMS3 0x0C /* RO structual parameters 3 */
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#define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF)
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#define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */
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#define XHCI_HCC_AC64(x) ((x) & 0x1) /* 64-bit capable */
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#define XHCI_HCC_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */
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#define XHCI_HCC_CSZ(x) (((x) >> 2) & 0x1) /* context size */
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#define XHCI_HCC_PPC(x) (((x) >> 3) & 0x1) /* port power control */
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#define XHCI_HCC_PIND(x) (((x) >> 4) & 0x1) /* port indicators */
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#define XHCI_HCC_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */
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#define XHCI_HCC_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */
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#define XHCI_HCC_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */
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#define XHCI_HCC_MAXPSASIZE(x) (((x) >> 12) & 0xF) /* max pri. stream array size */
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#define XHCI_HCC_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */
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#define XHCI_DBOFF 0x14 /* RO doorbell offset */
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#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */
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/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */
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#define XHCI_USBCMD 0x00 /* XHCI command */
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#define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */
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#define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */
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#define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */
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#define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */
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#define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */
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#define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */
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#define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */
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#define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */
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#define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */
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#define XHCI_USBSTS 0x04 /* XHCI status */
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#define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */
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#define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */
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#define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */
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#define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */
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#define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */
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#define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */
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#define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */
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#define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */
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#define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */
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#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */
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#define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */
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#define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */
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#define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */
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#define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */
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#define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */
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#define XHCI_DNCTRL 0x14 /* XHCI device notification control */
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#define XHCI_DNCTRL_MASK(n) (1U << (n))
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#define XHCI_CRCR 0x18 /* XHCI command ring control */
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#define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */
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#define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */
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#define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */
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#define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */
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#define XHCI_CRCR_LO_MASK 0x0000000F
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#define XHCI_CRCR_HI 0x1C /* XHCI command ring control */
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#define XHCI_DCBAAP 0x30 /* XHCI dev context BA pointer */
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#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */
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#define XHCI_CONFIG 0x38
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#define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
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/* XHCI port status registers */
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#define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */
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#define XHCI_PS_CCS 0x00000001 /* RO - current connect status */
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#define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
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#define XHCI_PS_OCA 0x00000008 /* RO - over current active */
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#define XHCI_PS_PR 0x00000010 /* RW - port reset */
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#define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
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#define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
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#define XHCI_PS_PP 0x00000200 /* RW - port power */
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#define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */
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#define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
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#define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
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#define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
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#define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
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#define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
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#define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
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#define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
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#define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
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#define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
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#define XHCI_PS_CEC 0x00800000 /* RW - config error change */
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#define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */
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#define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
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#define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
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#define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
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#define XHCI_PS_DR 0x40000000 /* RO - device removable */
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#define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
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#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */
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#define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */
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#define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
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#define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
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#define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
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#define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
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#define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
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#define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */
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#define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
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#define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
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#define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
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#define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
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#define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
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#define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
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#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */
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#define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */
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#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */
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/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
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#define XHCI_MFINDEX 0x0000 /* RO - microframe index */
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#define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF)
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#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */
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#define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
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#define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
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#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */
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#define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */
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#define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */
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#define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */
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#define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */
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#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */
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#define XHCI_IMOD_DEFAULT_LP 0x000003E8U /* 4000 IRQ/sec for LynxPoint */
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#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */
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#define XHCI_ERSTS_GET(x) ((x) & 0xFFFF)
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#define XHCI_ERSTS_SET(x) ((x) & 0xFFFF)
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#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */
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#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */
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#define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */
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#define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */
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#define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
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#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */
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/* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
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#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
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#define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
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#define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
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#define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
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#define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */
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/* XHCI legacy support */
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#define XHCI_XECP_ID(x) ((x) & 0xFF)
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#define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF)
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#define XHCI_XECP_BIOS_SEM 0x0002
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#define XHCI_XECP_OS_SEM 0x0003
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/* XHCI extended capability ID's */
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#define XHCI_ID_USB_LEGACY 0x0001 /* USB Legacy Support */
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#define XHCI_XECP_USBLESUP 0x0000 /* Legacy Support Capability Reg */
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#define XHCI_XECP_USBLEGCTLSTS 0x0004 /* Legacy Support Ctrl & Status Reg */
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#define XHCI_ID_PROTOCOLS 0x0002 /* Supported Protocol */
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#define XHCI_ID_POWER_MGMT 0x0003 /* Extended Power Management */
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#define XHCI_ID_VIRTUALIZATION 0x0004 /* I/O Virtualization */
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#define XHCI_ID_MSG_IRQ 0x0005 /* Message Interrupt */
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#define XHCI_ID_USB_LOCAL_MEM 0x0006 /* Local Memory */
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#define XHCI_ID_USB_DEBUG 0x000A /* USB Debug Capability */
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#define XHCI_ID_XMSG_IRQ 0x0011 /* Extended Message Interrupt */
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#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz)
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/* Chapter 6, Table 49 */
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#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64
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#define XHCI_DEVICE_CONTEXT_ALIGN 64
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#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64
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#define XHCI_SLOT_CONTEXT_ALIGN 32
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#define XHCI_ENDPOINT_CONTEXT_ALIGN 32
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#define XHCI_STREAM_CONTEXT_ALIGN 16
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#define XHCI_STREAM_ARRAY_ALIGN 16
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#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16
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2014-11-18 13:18:45 +03:00
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#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 64
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2013-09-14 04:40:31 +04:00
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#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64
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#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64
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#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64
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#define XHCI_SCRATCHPAD_BUFFERS_ALIGN XHCI_PAGE_SIZE
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#define XHCI_ERSTE_ALIGN 16
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#define XHCI_TRB_ALIGN 16
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struct xhci_trb {
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uint64_t trb_0;
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uint32_t trb_2;
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#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
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#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
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#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
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#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
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#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
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#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
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#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
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#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
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#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
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#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
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#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
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uint32_t trb_3;
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#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
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#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
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#define XHCI_TRB_3_CYCLE_BIT (1U << 0)
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#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
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#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
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#define XHCI_TRB_3_ISP_BIT (1U << 2)
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#define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
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#define XHCI_TRB_3_CHAIN_BIT (1U << 4)
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#define XHCI_TRB_3_IOC_BIT (1U << 5)
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#define XHCI_TRB_3_IDT_BIT (1U << 6)
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#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
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#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
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#define XHCI_TRB_3_BEI_BIT (1U << 9)
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#define XHCI_TRB_3_DCEP_BIT (1U << 9)
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#define XHCI_TRB_3_PRSV_BIT (1U << 9)
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#define XHCI_TRB_3_BSR_BIT (1U << 9)
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#define XHCI_TRB_3_TRT_MASK (3U << 16)
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#define XHCI_TRB_3_TRT_NONE (0U << 16)
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#define XHCI_TRB_3_TRT_OUT (2U << 16)
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#define XHCI_TRB_3_TRT_IN (3U << 16)
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#define XHCI_TRB_3_DIR_IN (1U << 16)
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#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
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#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
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#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
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#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
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#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
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#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
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#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
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#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
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2015-03-28 11:19:20 +03:00
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#define XHCI_TRB_3_VFID_GET(x) (((x) >> 16) & 0xFF)
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#define XHCI_TRB_3_VFID_SET(x) (((x) & 0xFF) << 16)
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2013-09-14 04:40:31 +04:00
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#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
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#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
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/* Commands */
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#define XHCI_TRB_TYPE_RESERVED 0x00
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#define XHCI_TRB_TYPE_NORMAL 0x01
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#define XHCI_TRB_TYPE_SETUP_STAGE 0x02
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#define XHCI_TRB_TYPE_DATA_STAGE 0x03
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#define XHCI_TRB_TYPE_STATUS_STAGE 0x04
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#define XHCI_TRB_TYPE_ISOCH 0x05
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#define XHCI_TRB_TYPE_LINK 0x06
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#define XHCI_TRB_TYPE_EVENT_DATA 0x07
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#define XHCI_TRB_TYPE_NOOP 0x08
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#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
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#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
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#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
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#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
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#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
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#define XHCI_TRB_TYPE_RESET_EP 0x0E
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#define XHCI_TRB_TYPE_STOP_EP 0x0F
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#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
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#define XHCI_TRB_TYPE_RESET_DEVICE 0x11
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#define XHCI_TRB_TYPE_FORCE_EVENT 0x12
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#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
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#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
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#define XHCI_TRB_TYPE_GET_PORT_BW 0x15
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#define XHCI_TRB_TYPE_FORCE_HEADER 0x16
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#define XHCI_TRB_TYPE_NOOP_CMD 0x17
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/* Events */
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#define XHCI_TRB_EVENT_TRANSFER 0x20
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#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
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#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
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#define XHCI_TRB_EVENT_BW_REQUEST 0x23
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#define XHCI_TRB_EVENT_DOORBELL 0x24
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#define XHCI_TRB_EVENT_HOST_CTRL 0x25
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#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
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#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
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/* Error codes */
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#define XHCI_TRB_ERROR_INVALID 0x00
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#define XHCI_TRB_ERROR_SUCCESS 0x01
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#define XHCI_TRB_ERROR_DATA_BUF 0x02
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#define XHCI_TRB_ERROR_BABBLE 0x03
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#define XHCI_TRB_ERROR_XACT 0x04
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#define XHCI_TRB_ERROR_TRB 0x05
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#define XHCI_TRB_ERROR_STALL 0x06
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#define XHCI_TRB_ERROR_RESOURCE 0x07
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#define XHCI_TRB_ERROR_BANDWIDTH 0x08
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#define XHCI_TRB_ERROR_NO_SLOTS 0x09
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#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
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#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
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#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
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#define XHCI_TRB_ERROR_SHORT_PKT 0x0D
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#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
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#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
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#define XHCI_TRB_ERROR_VF_RING_FULL 0x10
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#define XHCI_TRB_ERROR_PARAMETER 0x11
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#define XHCI_TRB_ERROR_BW_OVERRUN 0x12
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#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
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#define XHCI_TRB_ERROR_NO_PING_RESP 0x14
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#define XHCI_TRB_ERROR_EV_RING_FULL 0x15
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#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
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#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
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#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
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#define XHCI_TRB_ERROR_CMD_ABORTED 0x19
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#define XHCI_TRB_ERROR_STOPPED 0x1A
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#define XHCI_TRB_ERROR_LENGTH 0x1B
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#define XHCI_TRB_ERROR_BAD_MELAT 0x1D
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#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
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#define XHCI_TRB_ERROR_EVENT_LOST 0x20
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#define XHCI_TRB_ERROR_UNDEFINED 0x21
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#define XHCI_TRB_ERROR_INVALID_SID 0x22
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#define XHCI_TRB_ERROR_SEC_BW 0x23
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#define XHCI_TRB_ERROR_SPLIT_XACT 0x24
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} __packed __aligned(XHCI_TRB_ALIGN);
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#define XHCI_TRB_SIZE sizeof(struct xhci_trb)
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#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
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#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
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#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
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#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
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#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
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#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
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#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
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#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
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#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
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#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
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#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
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#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
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#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
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#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
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#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
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#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
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#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
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#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
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#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
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#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
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#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
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#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
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#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
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#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
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#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
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#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
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#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
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#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
|
2015-03-28 11:19:20 +03:00
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#define XHCI_SLOTSTATE_DISABLED 0 /* disabled or enabled */
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#define XHCI_SLOTSTATE_ENABLED 0
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#define XHCI_SLOTSTATE_DEFAULT 1
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#define XHCI_SLOTSTATE_ADDRESSED 2
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#define XHCI_SLOTSTATE_CONFIGURED 3
|
2013-09-14 04:40:31 +04:00
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#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
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#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
|
2015-03-28 11:19:20 +03:00
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#define XHCI_EPSTATE_DISABLED 0
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#define XHCI_EPSTATE_RUNNING 1
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#define XHCI_EPSTATE_HALTED 2
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#define XHCI_EPSTATE_STOPPED 3
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#define XHCI_EPSTATE_ERROR 4
|
2013-09-14 04:40:31 +04:00
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#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
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#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
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#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
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#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
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#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
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#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
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#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
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#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
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#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
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#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
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#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
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#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
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#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
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#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
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#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
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#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
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#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
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#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
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#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
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#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
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#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
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#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
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#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
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#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
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#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
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#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
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struct xhci_erste {
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uint64_t erste_0; /* 63:6 base */
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uint32_t erste_2; /* 15:0 trb count (16 to 4096) */
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uint32_t erste_3; /* RsvdZ */
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} __packed __aligned(XHCI_ERSTE_ALIGN);
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#define XHCI_ERSTE_SIZE sizeof(struct xhci_erste)
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#endif /* _XHCIREG_H_ */
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