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NetBSD/sys/dev/mii/miidevs

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Add entry for Broadcom's BCM5214 Quad 10/100 media interface.
2003-05-02 23:39:29 +04:00
$NetBSD: miidevs,v 1.47 2003/05/02 19:39:29 scw Exp $
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/*-
Silicon Integrated Systems OUI and the SiS 900 PHY model number.
1999-03-25 00:07:04 +03:00
* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
* List of known MII OUIs.
* For a complete list see http://standards.ieee.org/regauth/oui/
*
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
* XXX Vendors do obviously not agree how OUIs (24 bit) are mapped
* to the 22 bits available in the id registers.
* IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
* mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
* (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
* about this.)
* The MII_OUI() macro in "mii.h" reflects this.
* If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
* which is mangled accordingly to compensate.
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
*/
Add an Altima PHY.
2001-01-07 18:00:46 +03:00
oui ALTIMA 0x0010a9 Altima Communications
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
oui AMD 0x00001a Advanced Micro Devices
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
oui BROADCOM 0x001018 Broadcom Corporation
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
oui DAVICOM 0x00606e Davicom Semiconductor
Add an Altima PHY.
2001-01-07 18:00:46 +03:00
oui ENABLESEMI 0x0010dd Enable Semiconductor
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
oui ICS 0x00a0be Integrated Circuit Systems
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
oui INTEL 0x00aa00 Intel
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
oui LEVEL1 0x00207b Level 1
Bleh, I don't like the way our miidevs works now. Repair the Marvell Semiconductor entry.
2001-07-20 11:06:42 +04:00
oui MARVELL 0x005043 Marvell Semiconductor
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
oui MYSON 0x00c0b4 Myson Technology
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
oui NATSEMI 0x080017 National Semiconductor
argh - the OUI of PMC-Sierra is 00-e0-04, according to IEEE. They managed to mess it up in a new way.
2001-05-17 21:39:00 +04:00
oui PMCSIERRA 0x00e004 PMC-Sierra
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
oui QUALSEMI 0x006051 Quality Semiconductor
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
oui SEEQ 0x00a07d Seeq
oui SIS 0x00e006 Silicon Integrated Systems
oui TI 0x080028 Texas Instruments
Add Intel 82553 and TSC 78Q2120.
1999-09-05 03:58:55 +04:00
oui TSC 0x00c039 TDK Semiconductor
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
oui XAQTI 0x00e0ae XaQti Corp.
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
Add Intel 82553 and TSC 78Q2120.
1999-09-05 03:58:55 +04:00
/* Some Intel 82553's use an alternative OUI. */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
oui xxINTEL 0x001f00 Intel
Add Intel 82553 and TSC 78Q2120.
1999-09-05 03:58:55 +04:00
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
/* bad bitorder (bits "g" and "h" (= MSBs byte 1) lost) */
oui yyAMD 0x000058 Advanced Micro Devices
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
oui xxBROADCOM 0x000818 Broadcom Corporation
After I found a press release of 1998 which states that AMD sold Davicom PHY chips, merge the identical entries for DM9101 and Am79c873 into one. Should also fix PR kern/17369 by Dave Huang.
2002-06-25 16:25:56 +04:00
oui xxDAVICOM 0x000676 Davicom Semiconductor
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
oui yyINTEL 0x005500 Intel
After I found a press release of 1998 which states that AMD sold Davicom PHY chips, merge the identical entries for DM9101 and Am79c873 into one. Should also fix PR kern/17369 by Dave Huang.
2002-06-25 16:25:56 +04:00
oui xxMARVELL 0x000ac2 Marvell Semiconductor
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
oui xxMYSON 0x00032d Myson Technology
oui xxNATSEMI 0x1000e8 National Semiconductor
oui xxQUALSEMI 0x00068a Quality Semiconductor
oui xxTSC 0x00039c TDK Semiconductor
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
/* bad byteorder (bits "q" and "r" (= LSBs byte 3) lost) */
oui xxLEVEL1 0x782000 Level 1
oui xxXAQTI 0xace000 XaQti Corp.
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
/* Don't know what's going on here. */
argh - the OUI of PMC-Sierra is 00-e0-04, according to IEEE. They managed to mess it up in a new way.
2001-05-17 21:39:00 +04:00
oui xxPMCSIERRA 0x0009c0 PMC-Sierra
Correct/add more PMC-Sierra PHYs
2002-05-16 02:48:17 +04:00
oui xxPMCSIERRA2 0x009057 PMC-Sierra
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/*
* List of known models. Grouped by oui.
*/
Add an Altima PHY.
2001-01-07 18:00:46 +03:00
/* Altima Communications PHYs */
Add another Altima PHY. From Peter Seebach.
2001-12-15 03:31:03 +03:00
/* Don't know the model for ACXXX */
model ALTIMA ACXXX 0x0001 ACXXX 10/100 media interface
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model ALTIMA AC101 0x0021 AC101 10/100 media interface
Add altima (broadcom) AC101L, phy for 3com 3c905cx-tx on nForce2 MCP-T.
2003-01-17 09:20:07 +03:00
model ALTIMA AC101L 0x0012 AC101L 10/100 media interface
Add AMD Am79C87[45] (which use the Altima OUI).
2003-01-26 09:20:30 +03:00
/* AMD Am79C87[45] have ALTIMA OUI */
model ALTIMA Am79C875 0x0014 Am79C875 10/100 media interface
model ALTIMA Am79C874 0x0021 Am79C874 10/100 media interface
Add an Altima PHY.
2001-01-07 18:00:46 +03:00
Add AMD's OUI, and the model number for the AMD 79C873 10/100 Ethernet PHY.
1998-11-05 06:43:43 +03:00
/* Advanced Micro Devices PHYs */
After I found a press release of 1998 which states that AMD sold Davicom PHY chips, merge the identical entries for DM9101 and Am79c873 into one. Should also fix PR kern/17369 by Dave Huang.
2002-06-25 16:25:56 +04:00
/* see Davicom DM9101 for Am79C873 */
The Am79c972 PCnet-FAST+ has its built-in 10BASE-T interface mapped onto the MII bus. Recognize it.
2001-08-23 08:47:05 +04:00
model yyAMD 79C972_10T 0x0001 Am79C972 internal 10BASE-T interface
Improve the AMD PHY names.
2001-08-25 05:39:22 +04:00
model yyAMD 79c973phy 0x0036 Am79C973 internal 10/100 media interface
model yyAMD 79c901 0x0037 Am79C901 10BASE-T interface
model yyAMD 79c901home 0x0039 Am79C901 HomePNA 1.0 interface
Add AMD's OUI, and the model number for the AMD 79C873 10/100 Ethernet PHY.
1998-11-05 06:43:43 +03:00
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
/* Broadcom Corp. PHYs */
Fixup some Broadcom entries, add an entry for Broadcom PHY that is built-in to some 3Com 3c905B cards.
2001-07-27 21:54:40 +04:00
model xxBROADCOM 3C905B 0x0012 Broadcom 3c905B internal PHY
model xxBROADCOM 3C905C 0x0017 Broadcom 3c905C internal PHY
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model xxBROADCOM BCM5201 0x0021 BCM5201 10/100 media interface
Add entry for Broadcom's BCM5214 Quad 10/100 media interface.
2003-05-02 23:39:29 +04:00
model xxBROADCOM BCM5214 0x0028 BCM5214 Quad 10/100 media interface
Fixup some Broadcom entries, add an entry for Broadcom PHY that is built-in to some 3Com 3c905B cards.
2001-07-27 21:54:40 +04:00
model xxBROADCOM BCM5221 0x001e BCM5221 10/100 media interface
Add LevelOne LXT-1000 10/100/1000 PHY, clean up some Gig-E PHY names.
2001-07-13 01:25:07 +04:00
model BROADCOM BCM5400 0x0004 BCM5400 1000BASE-T media interface
model BROADCOM BCM5401 0x0005 BCM5401 1000BASE-T media interface
model BROADCOM BCM5411 0x0007 BCM5411 1000BASE-T media interface
Add Broadcom BCM5421
2002-07-10 03:24:33 +04:00
model BROADCOM BCM5421 0x000e BCM5421 1000BASE-T media interface
Aff BCM 5701 PHY Id.
2002-06-22 18:35:52 +04:00
model BROADCOM BCM5701 0x0011 BCM5701 1000BASE-T media interface
Add BCM5703.
2002-12-27 06:14:06 +03:00
model BROADCOM BCM5703 0x0016 BCM5703 1000BASE-T media interface
Add PHY entry for bcm5704c (copper) integral phy to miidevs. Add 5704 phy and dsp patch, and untestsed dsp patch for 5703, to brgphy.c.
2003-01-16 21:43:40 +03:00
model BROADCOM BCM5704 0x0019 BCM5704 1000BASE-T media interface
Add a Broadcom PHy used in the D-Link USB100 adapter. There's no special driver for this PHY (yet).
2000-01-13 23:16:08 +03:00
Add oui for Davicom Semiconductor, and add Davicom DM9101 10/100 PHY.
1999-02-05 23:19:44 +03:00
/* Davicom Semiconductor PHYs */
After I found a press release of 1998 which states that AMD sold Davicom PHY chips, merge the identical entries for DM9101 and Am79c873 into one. Should also fix PR kern/17369 by Dave Huang.
2002-06-25 16:25:56 +04:00
/* AMD Am79C873 seems to be a relabeled DM9101 */
model xxDAVICOM DM9101 0x0000 DM9101 (AMD Am79C873) 10/100 media interface
Add oui for Davicom Semiconductor, and add Davicom DM9101 10/100 PHY.
1999-02-05 23:19:44 +03:00
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* Integrated Circuit Systems PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model ICS 1890 0x0002 ICS1890 10/100 media interface
Add ICS 1893
2002-02-10 20:08:24 +03:00
model ICS 1893 0x0004 ICS1893 10/100 media interface
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* Intel PHYs */
Add Intel 82553 and TSC 78Q2120.
1999-09-05 03:58:55 +04:00
model xxINTEL I82553 0x0000 i82553 10/100 media interface
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model yyINTEL I82555 0x0015 i82555 10/100 media interface
add media options for the Intel UCH2 internal ethernet controller
2001-04-09 13:39:24 +04:00
model yyINTEL I82562EH 0x0017 i82562EH HomePNA interface
model yyINTEL I82562EM 0x0032 i82562EM 10/100 media interface
Add i82562ET id.
2001-05-22 20:04:27 +04:00
model yyINTEL I82562ET 0x0033 i82562ET 10/100 media interface
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model yyINTEL I82553 0x0035 i82553 10/100 media interface
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* Level 1 PHYs */
Define OUIs in a more uniform way. OUIs are fixed entities registered with IEEE, so use the "real" OUIs for definitions. Now unfortunately vendors differ in how the MII ID register bits are used wrt bit and byte ordering. There is a straightforward way - bits numbered from LSB to MSB - used by AMD, Intel, NS and QS. This is used by the current MII_OUI() conversion macro. ICS, Seeq, SiS and TI count the bits as they appear on the wire, and some differ completely. Account for these cases by "xx" prefixed OUI definitions which compensate for this, so the MII_OUI() macro can still be used. Add AMD (the "real" AMD this time) and the 79c973 PCnet internal PHY.
1999-05-14 15:37:30 +04:00
model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface
add support for LXT971 PHYs.
2002-03-14 07:40:26 +03:00
model LEVEL1 LXT971 0x000e LXT971 10/100 media interface
Add LevelOne LXT-1000 10/100/1000 PHY, clean up some Gig-E PHY names.
2001-07-13 01:25:07 +04:00
model LEVEL1 LXT1000_OLD 0x0003 LXT1000 1000BASE-T media interface
model LEVEL1 LXT1000 0x000c LXT1000 1000BASE-T media interface
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
Add several additional PHYs.
2001-05-31 23:40:33 +04:00
/* Marvell Semiconductor PHYs */
Add ID for Marvell 881011 phy found on newer i8254x-based gig-e cards.
2002-08-08 04:03:42 +04:00
model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY
Add another Marvell 88E1000 PHY model number.
2002-01-15 23:59:52 +03:00
model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY
model xxMARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY
Add several additional PHYs.
2001-05-31 23:40:33 +04:00
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
/* Myson Technology PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model xxMYSON MTD972 0x0000 MTD972 10/100 media interface
Add MYSON MTD803
2002-11-07 23:35:55 +03:00
model MYSON MTD803 0x0000 MTD803 3-in-1 media interface
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* National Semiconductor PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model xxNATSEMI DP83840 0x0000 DP83840 10/100 media interface
model xxNATSEMI DP83843 0x0001 DP83843 10/100 media interface
Add several additional PHYs.
2001-05-31 23:40:33 +04:00
model xxNATSEMI DP83815 0x0002 DP83815 10/100 media interface
Add LevelOne LXT-1000 10/100/1000 PHY, clean up some Gig-E PHY names.
2001-07-13 01:25:07 +04:00
model xxNATSEMI DP83891 0x0005 DP83891 1000BASE-T media interface
model xxNATSEMI DP83861 0x0006 DP83861 1000BASE-T media interface
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
argh - the OUI of PMC-Sierra is 00-e0-04, according to IEEE. They managed to mess it up in a new way.
2001-05-17 21:39:00 +04:00
/* PMC Sierra PHYs */
model xxPMCSIERRA PM8351 0x0000 PM8351 OctalPHY Gigabit interface
Correct/add more PMC-Sierra PHYs
2002-05-16 02:48:17 +04:00
model xxPMCSIERRA2 PM8352 0x0002 PM8352 OctalPHY Gigabit interface
Add another PMC-SIERRA phy
2002-05-16 01:24:59 +04:00
model xxPMCSIERRA2 PM8353 0x0003 PM8353 QuadPHY Gigabit interface
Correct/add more PMC-Sierra PHYs
2002-05-16 02:48:17 +04:00
model PMCSIERRA PM8354 0x0004 PM8354 QuadPHY Gigabit interface
Add OUI for PMC-Sierra. Add BCM5221 Phy. Add PM8351 Phy.
2001-05-16 03:17:48 +04:00
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* Quality Semiconductor PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model xxQUALSEMI QS6612 0x0000 QS6612 10/100 media interface
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* Seeq PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model SEEQ 80220 0x0003 Seeq 80220 10/100 media interface
model SEEQ 84220 0x0004 Seeq 84220 10/100 media interface
Add Seeq 80225 10/100 PHY.
2001-06-19 23:51:04 +04:00
model SEEQ 80225 0x0008 Seeq 80225 10/100 media interface
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
Silicon Integrated Systems OUI and the SiS 900 PHY model number.
1999-03-25 00:07:04 +03:00
/* Silicon Integrated Systems PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model SIS 900 0x0000 SiS 900 10/100 media interface
Silicon Integrated Systems OUI and the SiS 900 PHY model number.
1999-03-25 00:07:04 +03:00
Near complete rewrite of the MII layer to present an interface compatible with BSDI's MII layer to device drivers.
1998-08-11 03:55:16 +04:00
/* Texas Instruments PHYs */
Add LevelOne LXT-1000 10/100/1000 PHY, clean up some Gig-E PHY names.
2001-07-13 01:25:07 +04:00
model TI TLAN10T 0x0001 ThunderLAN 10BASE-T media interface
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model TI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface
model TI TNETE2101 0x0003 TNETE2101 media interface
Add Intel 82553 and TSC 78Q2120.
1999-09-05 03:58:55 +04:00
/* TDK Semiconductor PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model xxTSC 78Q2120 0x0014 78Q2120 10/100 media interface
Add LevelOne LXT-1000 10/100/1000 PHY, clean up some Gig-E PHY names.
2001-07-13 01:25:07 +04:00
model xxTSC 78Q2121 0x0015 78Q2121 100BASE-TX media interface
Add some OUIs and models. From OpenBSD.
2000-11-07 01:32:26 +03:00
/* XaQti Corp. PHYs */
adapt to corrected OUI calculation
2001-03-28 18:14:57 +04:00
model xxXAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface
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