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NetBSD/lib/libarch/arm32/arm32_sync_icache.2

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Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
.\" Copyright (c) 1996 Mark Brinicombe
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Mark Brinicombe
.\" 4. Neither the name of the University nor the names of its contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
Updated to actually pass an address and length of the virtual memory area for which the CPU caches and main memory should be synchronised.
1997-02-10 06:20:48 +03:00
.\" $NetBSD: arm32_sync_icache.2,v 1.2 1997/02/10 03:20:48 mark Exp $
Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
.\"
.Dd October 14, 1996
.Dt ARM32_SYNC_ICACHE 2
.Os NetBSD
.Sh NAME
.Nm arm32_sync_icache
Updated to actually pass an address and length of the virtual memory area for which the CPU caches and main memory should be synchronised.
1997-02-10 06:20:48 +03:00
.Nd clean the cpu data cache and flush the cpu instruction cache
Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
.Sh SYNOPSIS
.Fd #include <machine/sysarch.h>
.Ft int
Updated to actually pass an address and length of the virtual memory area for which the CPU caches and main memory should be synchronised.
1997-02-10 06:20:48 +03:00
.Fn arm32_sync_icache "u_int addr" "int len"
Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
.Sh DESCRIPTION
.Fn arm32_sync_icache
will make sure that all the entries in the processor instruction cache
Updated to actually pass an address and length of the virtual memory area for which the CPU caches and main memory should be synchronised.
1997-02-10 06:20:48 +03:00
are synchorised with main memory and that any data in a write back cache
has been cleaned.
Some ARM processors (e.g SA110) have separate instruction and data
caches thus any dynamically generated or modified code needs to be
written back from any data caches to main memory and the instruction
cache needs to be synchronised with main memory.
.Pp
On such processors
Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
.Fn arm32_sync_icache
Updated to actually pass an address and length of the virtual memory area for which the CPU caches and main memory should be synchronised.
1997-02-10 06:20:48 +03:00
will clean the data cache and invalidate the processor instruction cache
to force reloading from main memory. On processors that have a shared
instruction and data cache and have a write through cache (.e.g ARM6)
Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
no action needs to be taken.
Updated to actually pass an address and length of the virtual memory area for which the CPU caches and main memory should be synchronised.
1997-02-10 06:20:48 +03:00
.Pp
The routine takes a start address
.Fa addr
and a length
.Fa len
to describe the area of memory that needs to be cleaned and synchronised.
Initial commit of the arm32_sync_icache() function in libarm32. This uses the ARM32_SYNC_ICACHE op to sysarch() to ensure that the processor instruction cache is in sync with main memory and the data cache.
1996-10-16 03:01:41 +04:00
.Sh ERRORS
.Fn arm32_sync_icache
will never fail so will always return 0.
.Sh REFERENCES
StrongARM Data Sheet