NetBSD/lib/libarch/arm32/arm32_sync_icache.2

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.\" Copyright (c) 1996 Mark Brinicombe
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Mark Brinicombe
.\" 4. Neither the name of the University nor the names of its contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" SUCH DAMAGE.
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.\" $NetBSD: arm32_sync_icache.2,v 1.1 1996/10/15 23:01:41 mark Exp $
.\"
.Dd October 14, 1996
.Dt ARM32_SYNC_ICACHE 2
.Os NetBSD
.Sh NAME
.Nm arm32_sync_icache
.Nd flush the cpu instruction cache
.Sh SYNOPSIS
.Fd #include <machine/sysarch.h>
.Ft int
.Fn arm32_sync_icache
.Sh DESCRIPTION
.Fn arm32_sync_icache
will make sure that all the entries in the processor instruction cache
are synchorised with main memory.
Some ARM processors (StrongARM) have separate instruction and data
caches thus following modification of the text area of a process the
contents of main memory and the contents of the instruction cache may
differ. On such processors
.Fn arm32_sync_icache
will invalidate the processor instruction cache to force reloading from
main memory. On processors that have a shared instruction and data cache
no action needs to be taken.
.Sh ERRORS
.Fn arm32_sync_icache
will never fail so will always return 0.
.Sh REFERENCES
StrongARM Data Sheet