60 lines
2.7 KiB
Groff
60 lines
2.7 KiB
Groff
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.\" Copyright (c) 1996 Mark Brinicombe
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\" 3. All advertising materials mentioning features or use of this software
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.\" must display the following acknowledgement:
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.\" This product includes software developed by Mark Brinicombe
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.\" 4. Neither the name of the University nor the names of its contributors
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.\" may be used to endorse or promote products derived from this software
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.\" without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $NetBSD: arm32_sync_icache.2,v 1.1 1996/10/15 23:01:41 mark Exp $
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.\"
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.Dd October 14, 1996
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.Dt ARM32_SYNC_ICACHE 2
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.Os NetBSD
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.Sh NAME
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.Nm arm32_sync_icache
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.Nd flush the cpu instruction cache
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.Sh SYNOPSIS
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.Fd #include <machine/sysarch.h>
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.Ft int
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.Fn arm32_sync_icache
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.Sh DESCRIPTION
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.Fn arm32_sync_icache
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will make sure that all the entries in the processor instruction cache
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are synchorised with main memory.
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Some ARM processors (StrongARM) have separate instruction and data
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caches thus following modification of the text area of a process the
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contents of main memory and the contents of the instruction cache may
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differ. On such processors
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.Fn arm32_sync_icache
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will invalidate the processor instruction cache to force reloading from
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main memory. On processors that have a shared instruction and data cache
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no action needs to be taken.
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.Sh ERRORS
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.Fn arm32_sync_icache
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will never fail so will always return 0.
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.Sh REFERENCES
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StrongARM Data Sheet
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