2008-01-10 10:44:07 +03:00
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/* $NetBSD: wdc_isa.c,v 1.53 2008/01/10 07:44:08 dyoung Exp $ */
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1998-01-15 02:41:59 +03:00
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1998-08-15 14:10:47 +04:00
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/*-
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2003-09-20 01:35:56 +04:00
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* Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
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1998-08-15 14:10:47 +04:00
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* All rights reserved.
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1998-01-15 02:41:59 +03:00
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*
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1998-08-15 14:10:47 +04:00
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Onno van der Linden.
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1998-01-15 02:41:59 +03:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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1998-08-15 14:10:47 +04:00
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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1998-01-15 02:41:59 +03:00
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*
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1998-08-15 14:10:47 +04:00
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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1998-01-15 02:41:59 +03:00
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*/
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2001-11-13 11:01:09 +03:00
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#include <sys/cdefs.h>
|
2008-01-10 10:44:07 +03:00
|
|
|
__KERNEL_RCSID(0, "$NetBSD: wdc_isa.c,v 1.53 2008/01/10 07:44:08 dyoung Exp $");
|
2001-11-13 11:01:09 +03:00
|
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|
|
1998-01-15 02:41:59 +03:00
|
|
|
#include <sys/param.h>
|
|
|
|
#include <sys/systm.h>
|
|
|
|
#include <sys/device.h>
|
1998-10-12 20:09:10 +04:00
|
|
|
#include <sys/malloc.h>
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2007-10-19 15:59:34 +04:00
|
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#include <sys/bus.h>
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|
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#include <sys/intr.h>
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1998-01-15 02:41:59 +03:00
|
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|
|
|
|
#include <dev/isa/isavar.h>
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|
|
|
#include <dev/isa/isadmavar.h>
|
1998-01-23 02:42:39 +03:00
|
|
|
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
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|
#include <dev/ic/wdcreg.h>
|
1998-10-12 20:09:10 +04:00
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#include <dev/ata/atavar.h>
|
1998-01-15 02:41:59 +03:00
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#include <dev/ic/wdcvar.h>
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#define WDC_ISA_REG_NPORTS 8
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#define WDC_ISA_AUXREG_OFFSET 0x206
|
1998-01-27 22:14:18 +03:00
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#define WDC_ISA_AUXREG_NPORTS 1 /* XXX "fdc" owns ports 0x3f7/0x377 */
|
1998-01-15 02:41:59 +03:00
|
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|
1999-05-19 18:41:25 +04:00
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|
/* options passed via the 'flags' config keyword */
|
2001-03-11 08:10:58 +03:00
|
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|
#define WDC_OPTIONS_32 0x01 /* try to use 32bit data I/O */
|
2001-06-07 10:33:48 +04:00
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|
#define WDC_OPTIONS_ATA_NOSTREAM 0x04
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|
|
|
#define WDC_OPTIONS_ATAPI_NOSTREAM 0x08
|
1998-01-15 02:41:59 +03:00
|
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|
|
|
|
struct wdc_isa_softc {
|
1998-10-12 20:09:10 +04:00
|
|
|
struct wdc_softc sc_wdcdev;
|
2004-08-14 19:08:04 +04:00
|
|
|
struct ata_channel *wdc_chanlist[1];
|
|
|
|
struct ata_channel ata_channel;
|
2004-01-01 20:18:53 +03:00
|
|
|
struct ata_queue wdc_chqueue;
|
2004-08-14 19:08:04 +04:00
|
|
|
struct wdc_regs wdc_regs;
|
1998-06-09 04:05:44 +04:00
|
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|
isa_chipset_tag_t sc_ic;
|
1998-01-15 02:41:59 +03:00
|
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|
void *sc_ih;
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|
|
|
int sc_drq;
|
|
|
|
};
|
|
|
|
|
2008-01-10 10:44:07 +03:00
|
|
|
static int wdc_isa_probe(device_t , struct cfdata *, void *);
|
|
|
|
static void wdc_isa_attach(device_t, device_t, void *);
|
|
|
|
static int wdc_isa_detach(device_t, int);
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2008-01-10 10:44:07 +03:00
|
|
|
CFATTACH_DECL2(wdc_isa, sizeof(struct wdc_isa_softc),
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|
|
|
wdc_isa_probe, wdc_isa_attach, wdc_isa_detach, NULL, NULL,
|
|
|
|
wdc_childdetached);
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2003-03-04 01:07:21 +03:00
|
|
|
#if 0
|
2004-08-20 03:30:09 +04:00
|
|
|
static void wdc_isa_dma_setup(struct wdc_isa_softc *);
|
|
|
|
static int wdc_isa_dma_init(void*, int, int, void *, size_t, int);
|
|
|
|
static void wdc_isa_dma_start(void*, int, int);
|
|
|
|
static int wdc_isa_dma_finish(void*, int, int, int);
|
2003-03-04 01:07:21 +03:00
|
|
|
#endif
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2004-08-20 03:30:09 +04:00
|
|
|
static int
|
2008-01-10 10:44:07 +03:00
|
|
|
wdc_isa_probe(device_t parent, struct cfdata *match, void *aux)
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
2004-08-14 19:08:04 +04:00
|
|
|
struct ata_channel ch;
|
1998-01-15 02:41:59 +03:00
|
|
|
struct isa_attach_args *ia = aux;
|
2004-08-14 19:08:04 +04:00
|
|
|
struct wdc_softc wdc;
|
|
|
|
struct wdc_regs wdr;
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
int result = 0, i;
|
1998-01-15 02:41:59 +03:00
|
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|
|
2002-01-08 00:46:56 +03:00
|
|
|
if (ia->ia_nio < 1)
|
|
|
|
return (0);
|
|
|
|
if (ia->ia_nirq < 1)
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
if (ISA_DIRECT_CONFIG(ia))
|
|
|
|
return (0);
|
|
|
|
|
2004-09-15 00:20:46 +04:00
|
|
|
if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
|
2002-01-08 00:46:56 +03:00
|
|
|
return (0);
|
2004-09-15 00:20:46 +04:00
|
|
|
if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ)
|
2002-01-08 00:46:56 +03:00
|
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|
return (0);
|
2004-09-15 00:20:46 +04:00
|
|
|
if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq == ISA_UNKNOWN_DRQ)
|
2002-04-19 09:27:04 +04:00
|
|
|
ia->ia_ndrq = 0;
|
2002-01-08 00:46:56 +03:00
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
memset(&wdc, 0, sizeof(wdc));
|
2000-03-23 10:01:25 +03:00
|
|
|
memset(&ch, 0, sizeof(ch));
|
2004-08-20 10:39:37 +04:00
|
|
|
ch.ch_atac = &wdc.sc_atac;
|
2004-08-14 19:08:04 +04:00
|
|
|
wdc.regs = &wdr;
|
2000-03-23 10:01:25 +03:00
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
wdr.cmd_iot = ia->ia_iot;
|
2002-01-08 00:46:56 +03:00
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
if (bus_space_map(wdr.cmd_iot, ia->ia_io[0].ir_addr,
|
|
|
|
WDC_ISA_REG_NPORTS, 0, &wdr.cmd_baseioh))
|
1998-01-15 02:41:59 +03:00
|
|
|
goto out;
|
|
|
|
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
for (i = 0; i < WDC_ISA_REG_NPORTS; i++) {
|
2004-08-14 19:08:04 +04:00
|
|
|
if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i,
|
|
|
|
i == 0 ? 4 : 1, &wdr.cmd_iohs[i]) != 0)
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
goto outunmap;
|
|
|
|
}
|
2004-05-26 00:42:40 +04:00
|
|
|
wdc_init_shadow_regs(&ch);
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
wdr.ctl_iot = ia->ia_iot;
|
|
|
|
if (bus_space_map(wdr.ctl_iot, ia->ia_io[0].ir_addr +
|
|
|
|
WDC_ISA_AUXREG_OFFSET, WDC_ISA_AUXREG_NPORTS, 0, &wdr.ctl_ioh))
|
1998-01-15 02:41:59 +03:00
|
|
|
goto outunmap;
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
result = wdcprobe(&ch);
|
1998-01-15 02:41:59 +03:00
|
|
|
if (result) {
|
2002-01-08 00:46:56 +03:00
|
|
|
ia->ia_nio = 1;
|
|
|
|
ia->ia_io[0].ir_size = WDC_ISA_REG_NPORTS;
|
|
|
|
|
|
|
|
ia->ia_nirq = 1;
|
|
|
|
|
|
|
|
ia->ia_niomem = 0;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_ISA_AUXREG_NPORTS);
|
1998-01-17 03:40:45 +03:00
|
|
|
outunmap:
|
2004-08-14 19:08:04 +04:00
|
|
|
bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_ISA_REG_NPORTS);
|
1998-01-17 03:40:45 +03:00
|
|
|
out:
|
1998-01-15 02:41:59 +03:00
|
|
|
return (result);
|
|
|
|
}
|
|
|
|
|
2008-01-10 10:44:07 +03:00
|
|
|
static int
|
|
|
|
wdc_isa_detach(device_t self, int flags)
|
|
|
|
{
|
|
|
|
struct wdc_isa_softc *sc = device_private(self);
|
|
|
|
struct wdc_regs *wdr = &sc->wdc_regs;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if ((rc = wdcdetach(self, flags)) != 0)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
|
|
|
|
|
|
|
|
bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, WDC_ISA_AUXREG_NPORTS);
|
|
|
|
bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, WDC_ISA_REG_NPORTS);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-08-20 03:30:09 +04:00
|
|
|
static void
|
2008-01-10 10:44:07 +03:00
|
|
|
wdc_isa_attach(device_t parent, device_t self, void *aux)
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
2008-01-10 10:44:07 +03:00
|
|
|
struct wdc_isa_softc *sc = device_private(self);
|
2004-08-14 19:08:04 +04:00
|
|
|
struct wdc_regs *wdr;
|
1998-01-15 02:41:59 +03:00
|
|
|
struct isa_attach_args *ia = aux;
|
2006-03-29 08:16:44 +04:00
|
|
|
int wdc_cf_flags = device_cfdata(self)->cf_flags;
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
int i;
|
1998-01-23 04:04:54 +03:00
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
|
|
|
|
wdr->cmd_iot = ia->ia_iot;
|
|
|
|
wdr->ctl_iot = ia->ia_iot;
|
1998-06-09 04:05:44 +04:00
|
|
|
sc->sc_ic = ia->ia_ic;
|
2004-08-14 19:08:04 +04:00
|
|
|
if (bus_space_map(wdr->cmd_iot, ia->ia_io[0].ir_addr,
|
|
|
|
WDC_ISA_REG_NPORTS, 0, &wdr->cmd_baseioh) ||
|
|
|
|
bus_space_map(wdr->ctl_iot,
|
2002-01-08 00:46:56 +03:00
|
|
|
ia->ia_io[0].ir_addr + WDC_ISA_AUXREG_OFFSET,
|
2004-08-14 19:08:04 +04:00
|
|
|
WDC_ISA_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) {
|
2003-03-22 22:57:14 +03:00
|
|
|
printf(": couldn't map registers\n");
|
|
|
|
return;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
|
|
|
|
for (i = 0; i < WDC_ISA_REG_NPORTS; i++) {
|
2004-08-14 19:08:04 +04:00
|
|
|
if (bus_space_subregion(wdr->cmd_iot,
|
|
|
|
wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
|
|
|
|
&wdr->cmd_iohs[i]) != 0) {
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
printf(": couldn't subregion registers\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
wdr->data32iot = wdr->cmd_iot;
|
|
|
|
wdr->data32ioh = wdr->cmd_iohs[0];
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2003-03-04 01:07:21 +03:00
|
|
|
#if 0
|
2004-09-15 00:20:46 +04:00
|
|
|
if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) {
|
2002-01-08 00:46:56 +03:00
|
|
|
sc->sc_drq = ia->ia_drq[0].ir_drq;
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
|
1998-10-12 20:09:10 +04:00
|
|
|
sc->sc_wdcdev.dma_arg = sc;
|
|
|
|
sc->sc_wdcdev.dma_init = wdc_isa_dma_init;
|
|
|
|
sc->sc_wdcdev.dma_start = wdc_isa_dma_start;
|
|
|
|
sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish;
|
|
|
|
wdc_isa_dma_setup(sc);
|
1998-03-13 19:50:07 +03:00
|
|
|
}
|
2003-03-04 01:07:21 +03:00
|
|
|
#endif
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA;
|
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
|
2003-03-22 22:57:14 +03:00
|
|
|
if (wdc_cf_flags & WDC_OPTIONS_32)
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32;
|
2003-03-22 22:57:14 +03:00
|
|
|
if (wdc_cf_flags & WDC_OPTIONS_ATA_NOSTREAM)
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATA_NOSTREAM;
|
2003-03-22 22:57:14 +03:00
|
|
|
if (wdc_cf_flags & WDC_OPTIONS_ATAPI_NOSTREAM)
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATAPI_NOSTREAM;
|
2003-03-22 22:57:14 +03:00
|
|
|
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
|
2004-08-14 19:08:04 +04:00
|
|
|
sc->wdc_chanlist[0] = &sc->ata_channel;
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
|
|
|
|
sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
|
2004-08-14 19:08:04 +04:00
|
|
|
sc->ata_channel.ch_channel = 0;
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
|
2004-08-14 19:08:04 +04:00
|
|
|
sc->ata_channel.ch_queue = &sc->wdc_chqueue;
|
2006-01-16 23:30:18 +03:00
|
|
|
sc->ata_channel.ch_ndrive = 2;
|
2004-08-16 18:47:31 +04:00
|
|
|
wdc_init_shadow_regs(&sc->ata_channel);
|
2003-03-22 22:57:14 +03:00
|
|
|
|
|
|
|
printf("\n");
|
|
|
|
|
2004-08-16 18:47:31 +04:00
|
|
|
sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq,
|
|
|
|
IST_EDGE, IPL_BIO, wdcintr, &sc->ata_channel);
|
|
|
|
|
2004-08-14 19:08:04 +04:00
|
|
|
wdcattach(&sc->ata_channel);
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
|
2003-03-04 01:07:21 +03:00
|
|
|
#if 0
|
1998-01-15 02:41:59 +03:00
|
|
|
static void
|
2004-08-20 03:30:09 +04:00
|
|
|
wdc_isa_dma_setup(struct wdc_isa_softc *sc)
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
2000-02-08 01:07:27 +03:00
|
|
|
bus_size_t maxsize;
|
|
|
|
|
|
|
|
if ((maxsize = isa_dmamaxsize(sc->sc_ic, sc->sc_drq)) < MAXPHYS) {
|
2000-02-08 21:40:51 +03:00
|
|
|
printf("%s: max DMA size %lu is less than required %d\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, (u_long)maxsize, MAXPHYS);
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
|
2000-02-08 01:07:27 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2003-05-10 03:51:25 +04:00
|
|
|
if (isa_drq_alloc(sc->sc_ic, sc->sc_drq) != 0) {
|
|
|
|
printf("%s: can't reserve drq %d\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
|
2003-05-10 03:51:25 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
1998-06-09 04:05:44 +04:00
|
|
|
if (isa_dmamap_create(sc->sc_ic, sc->sc_drq,
|
1998-01-15 02:41:59 +03:00
|
|
|
MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) {
|
|
|
|
printf("%s: can't create map for drq %d\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
|
2004-08-20 10:39:37 +04:00
|
|
|
sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
static int
|
2004-08-20 03:30:09 +04:00
|
|
|
wdc_isa_dma_init(void *v, int channel, int drive, void *databuf,
|
|
|
|
size_t datalen, int read)
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
1998-10-12 20:09:10 +04:00
|
|
|
struct wdc_isa_softc *sc = v;
|
1998-01-15 02:41:59 +03:00
|
|
|
|
1999-02-22 06:24:33 +03:00
|
|
|
isa_dmastart(sc->sc_ic, sc->sc_drq, databuf, datalen, NULL,
|
|
|
|
(read ? DMAMODE_READ : DMAMODE_WRITE) | DMAMODE_DEMAND,
|
1998-01-15 02:41:59 +03:00
|
|
|
BUS_DMA_NOWAIT);
|
1998-10-12 20:09:10 +04:00
|
|
|
return 0;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2004-08-20 03:30:09 +04:00
|
|
|
wdc_isa_dma_start(void *v, int channel, int drive)
|
1998-10-12 20:09:10 +04:00
|
|
|
{
|
|
|
|
/* nothing to do */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2004-08-20 03:30:09 +04:00
|
|
|
wdc_isa_dma_finish(void *v, int channel, int drive, int read)
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
1998-10-12 20:09:10 +04:00
|
|
|
struct wdc_isa_softc *sc = v;
|
1998-01-15 02:41:59 +03:00
|
|
|
|
1998-06-09 04:05:44 +04:00
|
|
|
isa_dmadone(sc->sc_ic, sc->sc_drq);
|
1998-10-12 20:09:10 +04:00
|
|
|
return 0;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
2003-03-04 01:07:21 +03:00
|
|
|
#endif
|