There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
/* $NetBSD: wdc_isa.c,v 1.37 2003/11/27 23:02:40 fvdl Exp $ */
|
1998-01-15 02:41:59 +03:00
|
|
|
|
1998-08-15 14:10:47 +04:00
|
|
|
/*-
|
2003-09-20 01:35:56 +04:00
|
|
|
* Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
|
1998-08-15 14:10:47 +04:00
|
|
|
* All rights reserved.
|
1998-01-15 02:41:59 +03:00
|
|
|
*
|
1998-08-15 14:10:47 +04:00
|
|
|
* This code is derived from software contributed to The NetBSD Foundation
|
|
|
|
* by Charles M. Hannum and by Onno van der Linden.
|
1998-01-15 02:41:59 +03:00
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
* 3. All advertising materials mentioning features or use of this software
|
|
|
|
* must display the following acknowledgement:
|
1998-08-15 14:10:47 +04:00
|
|
|
* This product includes software developed by the NetBSD
|
|
|
|
* Foundation, Inc. and its contributors.
|
|
|
|
* 4. Neither the name of The NetBSD Foundation nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived
|
|
|
|
* from this software without specific prior written permission.
|
1998-01-15 02:41:59 +03:00
|
|
|
*
|
1998-08-15 14:10:47 +04:00
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
|
|
|
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
|
|
|
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
|
|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
|
|
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
1998-01-15 02:41:59 +03:00
|
|
|
*/
|
|
|
|
|
2001-11-13 11:01:09 +03:00
|
|
|
#include <sys/cdefs.h>
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
__KERNEL_RCSID(0, "$NetBSD: wdc_isa.c,v 1.37 2003/11/27 23:02:40 fvdl Exp $");
|
2001-11-13 11:01:09 +03:00
|
|
|
|
1998-01-15 02:41:59 +03:00
|
|
|
#include <sys/param.h>
|
|
|
|
#include <sys/systm.h>
|
|
|
|
#include <sys/device.h>
|
1998-10-12 20:09:10 +04:00
|
|
|
#include <sys/malloc.h>
|
1998-01-15 02:41:59 +03:00
|
|
|
|
|
|
|
#include <machine/bus.h>
|
1998-01-23 02:42:39 +03:00
|
|
|
#include <machine/intr.h>
|
1998-01-15 02:41:59 +03:00
|
|
|
|
|
|
|
#include <dev/isa/isavar.h>
|
|
|
|
#include <dev/isa/isadmavar.h>
|
1998-01-23 02:42:39 +03:00
|
|
|
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
#include <dev/ic/wdcreg.h>
|
1998-10-12 20:09:10 +04:00
|
|
|
#include <dev/ata/atavar.h>
|
1998-01-15 02:41:59 +03:00
|
|
|
#include <dev/ic/wdcvar.h>
|
|
|
|
|
|
|
|
#define WDC_ISA_REG_NPORTS 8
|
|
|
|
#define WDC_ISA_AUXREG_OFFSET 0x206
|
1998-01-27 22:14:18 +03:00
|
|
|
#define WDC_ISA_AUXREG_NPORTS 1 /* XXX "fdc" owns ports 0x3f7/0x377 */
|
1998-01-15 02:41:59 +03:00
|
|
|
|
1999-05-19 18:41:25 +04:00
|
|
|
/* options passed via the 'flags' config keyword */
|
2001-03-11 08:10:58 +03:00
|
|
|
#define WDC_OPTIONS_32 0x01 /* try to use 32bit data I/O */
|
2001-06-07 10:33:48 +04:00
|
|
|
#define WDC_OPTIONS_ATA_NOSTREAM 0x04
|
|
|
|
#define WDC_OPTIONS_ATAPI_NOSTREAM 0x08
|
1998-01-15 02:41:59 +03:00
|
|
|
|
|
|
|
struct wdc_isa_softc {
|
1998-10-12 20:09:10 +04:00
|
|
|
struct wdc_softc sc_wdcdev;
|
2003-03-22 22:57:14 +03:00
|
|
|
struct channel_softc *wdc_chanlist[1];
|
1998-10-12 20:09:10 +04:00
|
|
|
struct channel_softc wdc_channel;
|
2003-03-22 22:57:14 +03:00
|
|
|
struct channel_queue wdc_chqueue;
|
1998-06-09 04:05:44 +04:00
|
|
|
isa_chipset_tag_t sc_ic;
|
1998-01-15 02:41:59 +03:00
|
|
|
void *sc_ih;
|
|
|
|
int sc_drq;
|
|
|
|
};
|
|
|
|
|
|
|
|
int wdc_isa_probe __P((struct device *, struct cfdata *, void *));
|
|
|
|
void wdc_isa_attach __P((struct device *, struct device *, void *));
|
|
|
|
|
2002-10-02 06:00:07 +04:00
|
|
|
CFATTACH_DECL(wdc_isa, sizeof(struct wdc_isa_softc),
|
2002-10-02 07:10:45 +04:00
|
|
|
wdc_isa_probe, wdc_isa_attach, NULL, NULL);
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2003-03-04 01:07:21 +03:00
|
|
|
#if 0
|
1998-10-12 20:09:10 +04:00
|
|
|
static void wdc_isa_dma_setup __P((struct wdc_isa_softc *));
|
|
|
|
static int wdc_isa_dma_init __P((void*, int, int, void *, size_t, int));
|
2000-04-02 06:07:52 +04:00
|
|
|
static void wdc_isa_dma_start __P((void*, int, int));
|
1998-10-12 20:09:10 +04:00
|
|
|
static int wdc_isa_dma_finish __P((void*, int, int, int));
|
2003-03-04 01:07:21 +03:00
|
|
|
#endif
|
1998-01-15 02:41:59 +03:00
|
|
|
|
|
|
|
int
|
|
|
|
wdc_isa_probe(parent, match, aux)
|
|
|
|
struct device *parent;
|
|
|
|
struct cfdata *match;
|
|
|
|
void *aux;
|
|
|
|
{
|
2000-03-23 10:01:25 +03:00
|
|
|
struct channel_softc ch;
|
1998-01-15 02:41:59 +03:00
|
|
|
struct isa_attach_args *ia = aux;
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
int result = 0, i;
|
1998-01-15 02:41:59 +03:00
|
|
|
|
2002-01-08 00:46:56 +03:00
|
|
|
if (ia->ia_nio < 1)
|
|
|
|
return (0);
|
|
|
|
if (ia->ia_nirq < 1)
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
if (ISA_DIRECT_CONFIG(ia))
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
if (ia->ia_io[0].ir_addr == ISACF_PORT_DEFAULT)
|
|
|
|
return (0);
|
|
|
|
if (ia->ia_irq[0].ir_irq == ISACF_IRQ_DEFAULT)
|
|
|
|
return (0);
|
2002-04-19 09:27:04 +04:00
|
|
|
if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq == ISACF_DRQ_DEFAULT)
|
|
|
|
ia->ia_ndrq = 0;
|
2002-01-08 00:46:56 +03:00
|
|
|
|
2000-03-23 10:01:25 +03:00
|
|
|
memset(&ch, 0, sizeof(ch));
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
ch.cmd_iot = ia->ia_iot;
|
2002-01-08 00:46:56 +03:00
|
|
|
|
|
|
|
if (bus_space_map(ch.cmd_iot, ia->ia_io[0].ir_addr,
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
WDC_ISA_REG_NPORTS, 0, &ch.cmd_baseioh))
|
1998-01-15 02:41:59 +03:00
|
|
|
goto out;
|
|
|
|
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
for (i = 0; i < WDC_ISA_REG_NPORTS; i++) {
|
|
|
|
if (bus_space_subregion(ch.cmd_iot, ch.cmd_baseioh, i,
|
|
|
|
i == 0 ? 4 : 1, &ch.cmd_iohs[i]) != 0)
|
|
|
|
goto outunmap;
|
|
|
|
}
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
ch.ctl_iot = ia->ia_iot;
|
2002-01-08 00:46:56 +03:00
|
|
|
if (bus_space_map(ch.ctl_iot, ia->ia_io[0].ir_addr +
|
|
|
|
WDC_ISA_AUXREG_OFFSET, WDC_ISA_AUXREG_NPORTS, 0, &ch.ctl_ioh))
|
1998-01-15 02:41:59 +03:00
|
|
|
goto outunmap;
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
result = wdcprobe(&ch);
|
1998-01-15 02:41:59 +03:00
|
|
|
if (result) {
|
2002-01-08 00:46:56 +03:00
|
|
|
ia->ia_nio = 1;
|
|
|
|
ia->ia_io[0].ir_size = WDC_ISA_REG_NPORTS;
|
|
|
|
|
|
|
|
ia->ia_nirq = 1;
|
|
|
|
|
|
|
|
ia->ia_niomem = 0;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
bus_space_unmap(ch.ctl_iot, ch.ctl_ioh, WDC_ISA_AUXREG_NPORTS);
|
1998-01-17 03:40:45 +03:00
|
|
|
outunmap:
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
bus_space_unmap(ch.cmd_iot, ch.cmd_baseioh, WDC_ISA_REG_NPORTS);
|
1998-01-17 03:40:45 +03:00
|
|
|
out:
|
1998-01-15 02:41:59 +03:00
|
|
|
return (result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
wdc_isa_attach(parent, self, aux)
|
|
|
|
struct device *parent, *self;
|
|
|
|
void *aux;
|
|
|
|
{
|
1998-01-23 04:04:54 +03:00
|
|
|
struct wdc_isa_softc *sc = (void *)self;
|
1998-01-15 02:41:59 +03:00
|
|
|
struct isa_attach_args *ia = aux;
|
2003-03-22 22:57:14 +03:00
|
|
|
int wdc_cf_flags = self->dv_cfdata->cf_flags;
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
int i;
|
1998-01-23 04:04:54 +03:00
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
sc->wdc_channel.cmd_iot = ia->ia_iot;
|
|
|
|
sc->wdc_channel.ctl_iot = ia->ia_iot;
|
1998-06-09 04:05:44 +04:00
|
|
|
sc->sc_ic = ia->ia_ic;
|
2002-01-08 00:46:56 +03:00
|
|
|
if (bus_space_map(sc->wdc_channel.cmd_iot, ia->ia_io[0].ir_addr,
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
WDC_ISA_REG_NPORTS, 0, &sc->wdc_channel.cmd_baseioh) ||
|
1998-10-12 20:09:10 +04:00
|
|
|
bus_space_map(sc->wdc_channel.ctl_iot,
|
2002-01-08 00:46:56 +03:00
|
|
|
ia->ia_io[0].ir_addr + WDC_ISA_AUXREG_OFFSET,
|
|
|
|
WDC_ISA_AUXREG_NPORTS, 0, &sc->wdc_channel.ctl_ioh)) {
|
2003-03-22 22:57:14 +03:00
|
|
|
printf(": couldn't map registers\n");
|
|
|
|
return;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
|
|
|
|
|
|
|
for (i = 0; i < WDC_ISA_REG_NPORTS; i++) {
|
|
|
|
if (bus_space_subregion(sc->wdc_channel.cmd_iot,
|
|
|
|
sc->wdc_channel.cmd_baseioh, i, i == 0 ? 4 : 1,
|
|
|
|
&sc->wdc_channel.cmd_iohs[i]) != 0) {
|
|
|
|
printf(": couldn't subregion registers\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
sc->wdc_channel.data32iot = sc->wdc_channel.cmd_iot;
|
There are some cards that map the ATA control and IDE DMA registers
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
2003-11-28 02:02:40 +03:00
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sc->wdc_channel.data32ioh = sc->wdc_channel.cmd_iohs[0];
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1998-01-15 02:41:59 +03:00
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2002-01-08 00:46:56 +03:00
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sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq,
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IST_EDGE, IPL_BIO, wdcintr, &sc->wdc_channel);
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1998-01-15 02:41:59 +03:00
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2003-03-04 01:07:21 +03:00
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#if 0
|
2002-01-08 00:46:56 +03:00
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if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq != ISACF_DRQ_DEFAULT) {
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sc->sc_drq = ia->ia_drq[0].ir_drq;
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1998-01-15 02:41:59 +03:00
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1998-10-12 20:09:10 +04:00
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA;
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = wdc_isa_dma_init;
|
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sc->sc_wdcdev.dma_start = wdc_isa_dma_start;
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sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish;
|
|
|
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wdc_isa_dma_setup(sc);
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1998-03-13 19:50:07 +03:00
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}
|
2003-03-04 01:07:21 +03:00
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#endif
|
1999-05-19 18:41:25 +04:00
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_PREATA;
|
2003-03-22 22:57:14 +03:00
|
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if (wdc_cf_flags & WDC_OPTIONS_32)
|
1999-05-19 18:41:25 +04:00
|
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|
sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32;
|
2003-03-22 22:57:14 +03:00
|
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if (wdc_cf_flags & WDC_OPTIONS_ATA_NOSTREAM)
|
2001-06-07 10:33:48 +04:00
|
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_ATA_NOSTREAM;
|
2003-03-22 22:57:14 +03:00
|
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if (wdc_cf_flags & WDC_OPTIONS_ATAPI_NOSTREAM)
|
2001-06-07 10:33:48 +04:00
|
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_ATAPI_NOSTREAM;
|
2003-03-22 22:57:14 +03:00
|
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|
1998-12-03 21:24:30 +03:00
|
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|
sc->sc_wdcdev.PIO_cap = 0;
|
2003-03-22 22:57:14 +03:00
|
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|
sc->wdc_chanlist[0] = &sc->wdc_channel;
|
|
|
|
sc->sc_wdcdev.channels = sc->wdc_chanlist;
|
1998-10-12 20:09:10 +04:00
|
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|
sc->sc_wdcdev.nchannels = 1;
|
|
|
|
sc->wdc_channel.channel = 0;
|
|
|
|
sc->wdc_channel.wdc = &sc->sc_wdcdev;
|
2003-03-22 22:57:14 +03:00
|
|
|
sc->wdc_channel.ch_queue = &sc->wdc_chqueue;
|
|
|
|
|
|
|
|
printf("\n");
|
|
|
|
|
2003-10-08 14:58:12 +04:00
|
|
|
wdcattach(&sc->wdc_channel);
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
|
2003-03-04 01:07:21 +03:00
|
|
|
#if 0
|
1998-01-15 02:41:59 +03:00
|
|
|
static void
|
1998-10-12 20:09:10 +04:00
|
|
|
wdc_isa_dma_setup(sc)
|
|
|
|
struct wdc_isa_softc *sc;
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
2000-02-08 01:07:27 +03:00
|
|
|
bus_size_t maxsize;
|
|
|
|
|
|
|
|
if ((maxsize = isa_dmamaxsize(sc->sc_ic, sc->sc_drq)) < MAXPHYS) {
|
2000-02-08 21:40:51 +03:00
|
|
|
printf("%s: max DMA size %lu is less than required %d\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, (u_long)maxsize, MAXPHYS);
|
2000-02-08 01:07:27 +03:00
|
|
|
sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2003-05-10 03:51:25 +04:00
|
|
|
if (isa_drq_alloc(sc->sc_ic, sc->sc_drq) != 0) {
|
|
|
|
printf("%s: can't reserve drq %d\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
|
|
|
|
sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
1998-06-09 04:05:44 +04:00
|
|
|
if (isa_dmamap_create(sc->sc_ic, sc->sc_drq,
|
1998-01-15 02:41:59 +03:00
|
|
|
MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) {
|
|
|
|
printf("%s: can't create map for drq %d\n",
|
|
|
|
sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
|
1998-10-12 20:09:10 +04:00
|
|
|
sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1998-10-12 20:09:10 +04:00
|
|
|
static int
|
|
|
|
wdc_isa_dma_init(v, channel, drive, databuf, datalen, read)
|
|
|
|
void *v;
|
|
|
|
void *databuf;
|
|
|
|
size_t datalen;
|
1998-01-15 02:41:59 +03:00
|
|
|
int read;
|
|
|
|
{
|
1998-10-12 20:09:10 +04:00
|
|
|
struct wdc_isa_softc *sc = v;
|
1998-01-15 02:41:59 +03:00
|
|
|
|
1999-02-22 06:24:33 +03:00
|
|
|
isa_dmastart(sc->sc_ic, sc->sc_drq, databuf, datalen, NULL,
|
|
|
|
(read ? DMAMODE_READ : DMAMODE_WRITE) | DMAMODE_DEMAND,
|
1998-01-15 02:41:59 +03:00
|
|
|
BUS_DMA_NOWAIT);
|
1998-10-12 20:09:10 +04:00
|
|
|
return 0;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2000-04-02 06:07:52 +04:00
|
|
|
wdc_isa_dma_start(v, channel, drive)
|
1998-10-12 20:09:10 +04:00
|
|
|
void *v;
|
|
|
|
int channel, drive;
|
|
|
|
{
|
|
|
|
/* nothing to do */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
wdc_isa_dma_finish(v, channel, drive, read)
|
|
|
|
void *v;
|
|
|
|
int channel, drive;
|
|
|
|
int read;
|
1998-01-15 02:41:59 +03:00
|
|
|
{
|
1998-10-12 20:09:10 +04:00
|
|
|
struct wdc_isa_softc *sc = v;
|
1998-01-15 02:41:59 +03:00
|
|
|
|
1998-06-09 04:05:44 +04:00
|
|
|
isa_dmadone(sc->sc_ic, sc->sc_drq);
|
1998-10-12 20:09:10 +04:00
|
|
|
return 0;
|
1998-01-15 02:41:59 +03:00
|
|
|
}
|
2003-03-04 01:07:21 +03:00
|
|
|
#endif
|