Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
NetBSD/sys/arch/mips/include/mips3_pte.h

128 lines
4.7 KiB
C
Raw Normal View History

Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
/* $NetBSD: mips3_pte.h,v 1.7 1997/06/16 23:41:44 jonathan Exp $ */
RCS id police.
1996-07-17 03:23:55 +04:00
First commit of Per Fogelstrom's port to the Acer pica r4400/isa machine.
1996-03-13 07:58:04 +03:00
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: pte.h 1.11 89/09/03
*
* from: @(#)pte.h 8.1 (Berkeley) 6/10/93
*/
/*
* R4000 hardware page table entry
*/
* Apply LOCORE -> _LOCORE change so locore.S doesn't #include struct definitions. * Include <mips/cpuregs.h> in <cpu.h> so kern_clock.c has user/kernel status bits in scope. Still needs work; r2k/r4k previous-mode bits are different. * Include <mips/mips_param.h> in pica/include/param.h, for locore declarations, and definitions of vm and other constants that should be shared across NetBSD/mips systems to esnsure user-level binary compatibility.
1996-08-12 03:30:22 +04:00
#ifndef _LOCORE
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
struct mips3_pte {
First commit of Per Fogelstrom's port to the Acer pica r4400/isa machine.
1996-03-13 07:58:04 +03:00
#if BYTE_ORDER == BIG_ENDIAN
unsigned int pg_prot:2, /* SW: access control */
pg_pfnum:24, /* HW: core page frame number or 0 */
pg_attr:3, /* HW: cache attribute */
pg_m:1, /* HW: modified (dirty) bit */
pg_v:1, /* HW: valid bit */
pg_g:1; /* HW: ignore pid bit */
#endif
#if BYTE_ORDER == LITTLE_ENDIAN
unsigned int pg_g:1, /* HW: ignore pid bit */
pg_v:1, /* HW: valid bit */
pg_m:1, /* HW: modified (dirty) bit */
pg_attr:3, /* HW: cache attribute */
pg_pfnum:24, /* HW: core page frame number or 0 */
pg_prot:2; /* SW: access control */
#endif
};
/*
* Structure defining an tlb entry data set.
*/
struct tlb {
int tlb_mask;
int tlb_hi;
int tlb_lo0;
int tlb_lo1;
};
* Apply LOCORE -> _LOCORE change so locore.S doesn't #include struct definitions. * Include <mips/cpuregs.h> in <cpu.h> so kern_clock.c has user/kernel status bits in scope. Still needs work; r2k/r4k previous-mode bits are different. * Include <mips/mips_param.h> in pica/include/param.h, for locore declarations, and definitions of vm and other constants that should be shared across NetBSD/mips systems to esnsure user-level binary compatibility.
1996-08-12 03:30:22 +04:00
#endif /* _LOCORE */
First commit of Per Fogelstrom's port to the Acer pica r4400/isa machine.
1996-03-13 07:58:04 +03:00
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS3_PG_WIRED 0x80000000 /* SW */
#define MIPS3_PG_RO 0x40000000 /* SW */
#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */
#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */
#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
#define MIPS3_PG_V 0x00000002 /* Valid */
#define MIPS3_PG_NV 0x00000000
#define MIPS3_PG_M 0x00000004 /* Dirty; i.e. writable */
#define MIPS3_PG_ATTR 0x0000003f
#define MIPS3_PG_UNCACHED 0x00000010
#define MIPS3_PG_CACHED 0x00000018 /* Cacheable noncoherent */
#define MIPS3_PG_CACHEMODE 0x00000038
/* Write protected */
#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
/* Not wr-prot not clean */
#define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_M | MIPS3_PG_CACHED)
/* Not wr-prot but clean */
#define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED)
#define MIPS3_PG_IOPAGE \
(MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_M | MIPS3_PG_UNCACHED)
#define MIPS3_PG_FRAME 0x3fffffc0
#define MIPS3_PG_SHIFT 6
Merge mips1 and mips3 pte/pmap code, pass 0; * Move mips-I pte (TLBlo) definitions from pmax/include/pte.h to mips/include/mips1_pte.h * Move mips-III pte (TLBlo) definitions from pica/include/pte.h to mips/include/mips3_pte.h * Add new mips/include/pte.h, which includes exactly one of mips1_pte.h or mips3_pte.h (which still have namespace collisions), depending on "options MIPS1" or "options MIPS3". (hack). Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h * Add macro PTE_TO_PADDR() to hide the different hardware TLB formats when mapping from pte to physical address. * Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in the kernel pmap.) * Use macros (not direct TLB frobbing) in mips/trap.c, to make it mips-1/mips-III indepenndet. * Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
1996-10-13 13:28:53 +04:00
/* pte accessor macros */
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define mips3_vad_to_pfn(x) (((unsigned)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
#define mips3_pfn_to_vad(x) (((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
#define mips3_vad_to_vpn(x) ((unsigned)(x) & MIPS3_PG_SVPN)
#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
Merge mips1 and mips3 pte/pmap code, pass 0; * Move mips-I pte (TLBlo) definitions from pmax/include/pte.h to mips/include/mips1_pte.h * Move mips-III pte (TLBlo) definitions from pica/include/pte.h to mips/include/mips3_pte.h * Add new mips/include/pte.h, which includes exactly one of mips1_pte.h or mips3_pte.h (which still have namespace collisions), depending on "options MIPS1" or "options MIPS3". (hack). Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h * Add macro PTE_TO_PADDR() to hide the different hardware TLB formats when mapping from pte to physical address. * Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in the kernel pmap.) * Use macros (not direct TLB frobbing) in mips/trap.c, to make it mips-1/mips-III indepenndet. * Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
1996-10-13 13:28:53 +04:00
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS3_PTE_TO_PADDR(pte) (mips3_pfn_to_vad(pte))
#define MIPS3_PAGE_IS_RDONLY(pte,va) \
Add (missing) PAGE_IS_RDONLY() macro to test for readonly pages, in both mips-I and mips-II versions, and use it in arch/mips/mips/trap.c.
1996-10-13 13:54:39 +04:00
(pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte)))
Merge mips1 and mips3 pte/pmap code, pass 0; * Move mips-I pte (TLBlo) definitions from pmax/include/pte.h to mips/include/mips1_pte.h * Move mips-III pte (TLBlo) definitions from pica/include/pte.h to mips/include/mips3_pte.h * Add new mips/include/pte.h, which includes exactly one of mips1_pte.h or mips3_pte.h (which still have namespace collisions), depending on "options MIPS1" or "options MIPS3". (hack). Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h * Add macro PTE_TO_PADDR() to hide the different hardware TLB formats when mapping from pte to physical address. * Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in the kernel pmap.) * Use macros (not direct TLB frobbing) in mips/trap.c, to make it mips-1/mips-III indepenndet. * Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.
1996-10-13 13:28:53 +04:00
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS3_PG_SIZE_4K 0x00000000
#define MIPS3_PG_SIZE_16K 0x00006000
#define MIPS3_PG_SIZE_64K 0x0001e000
#define MIPS3_PG_SIZE_256K 0x0007e000
#define MIPS3_PG_SIZE_1M 0x001fe000
#define MIPS3_PG_SIZE_4M 0x007fe000
#define MIPS3_PG_SIZE_16M 0x01ffe000